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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / sound / soc / codecs / rt5645.c
blob: 6aab552eda777fc91df10334f6d90d1e8b5329b1 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * rt5645.c -- RT5645 ALSA SoC audio codec driver
4 *
5 * Copyright 2013 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9#include <linux/module.h>
10#include <linux/moduleparam.h>
11#include <linux/init.h>
12#include <linux/delay.h>
13#include <linux/pm.h>
14#include <linux/i2c.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17#include <linux/gpio.h>
18#include <linux/gpio/consumer.h>
19#include <linux/acpi.h>
20#include <linux/dmi.h>
21#include <linux/regulator/consumer.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/jack.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include "rl6231.h"
32#include "rt5645.h"
33
34#define QUIRK_INV_JD1_1(q) ((q) & 1)
35#define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1)
36#define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1)
37#define QUIRK_JD_MODE(q) (((q) >> 4) & 7)
38#define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3)
39#define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3)
40
41static unsigned int quirk = -1;
42module_param(quirk, uint, 0444);
43MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override");
44
45#define RT5645_DEVICE_ID 0x6308
46#define RT5650_DEVICE_ID 0x6419
47
48#define RT5645_PR_RANGE_BASE (0xff + 1)
49#define RT5645_PR_SPACING 0x100
50
51#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
52
53#define RT5645_HWEQ_NUM 57
54
55#define TIME_TO_POWER_MS 400
56
57static const struct regmap_range_cfg rt5645_ranges[] = {
58 {
59 .name = "PR",
60 .range_min = RT5645_PR_BASE,
61 .range_max = RT5645_PR_BASE + 0xf8,
62 .selector_reg = RT5645_PRIV_INDEX,
63 .selector_mask = 0xff,
64 .selector_shift = 0x0,
65 .window_start = RT5645_PRIV_DATA,
66 .window_len = 0x1,
67 },
68};
69
70static const struct reg_sequence init_list[] = {
71 {RT5645_PR_BASE + 0x3d, 0x3600},
72 {RT5645_PR_BASE + 0x1c, 0xfd70},
73 {RT5645_PR_BASE + 0x20, 0x611f},
74 {RT5645_PR_BASE + 0x21, 0x4040},
75 {RT5645_PR_BASE + 0x23, 0x0004},
76 {RT5645_ASRC_4, 0x0120},
77};
78
79static const struct reg_sequence rt5650_init_list[] = {
80 {0xf6, 0x0100},
81};
82
83static const struct reg_default rt5645_reg[] = {
84 { 0x00, 0x0000 },
85 { 0x01, 0xc8c8 },
86 { 0x02, 0xc8c8 },
87 { 0x03, 0xc8c8 },
88 { 0x0a, 0x0002 },
89 { 0x0b, 0x2827 },
90 { 0x0c, 0xe000 },
91 { 0x0d, 0x0000 },
92 { 0x0e, 0x0000 },
93 { 0x0f, 0x0808 },
94 { 0x14, 0x3333 },
95 { 0x16, 0x4b00 },
96 { 0x18, 0x018b },
97 { 0x19, 0xafaf },
98 { 0x1a, 0xafaf },
99 { 0x1b, 0x0001 },
100 { 0x1c, 0x2f2f },
101 { 0x1d, 0x2f2f },
102 { 0x1e, 0x0000 },
103 { 0x20, 0x0000 },
104 { 0x27, 0x7060 },
105 { 0x28, 0x7070 },
106 { 0x29, 0x8080 },
107 { 0x2a, 0x5656 },
108 { 0x2b, 0x5454 },
109 { 0x2c, 0xaaa0 },
110 { 0x2d, 0x0000 },
111 { 0x2f, 0x1002 },
112 { 0x31, 0x5000 },
113 { 0x32, 0x0000 },
114 { 0x33, 0x0000 },
115 { 0x34, 0x0000 },
116 { 0x35, 0x0000 },
117 { 0x3b, 0x0000 },
118 { 0x3c, 0x007f },
119 { 0x3d, 0x0000 },
120 { 0x3e, 0x007f },
121 { 0x3f, 0x0000 },
122 { 0x40, 0x001f },
123 { 0x41, 0x0000 },
124 { 0x42, 0x001f },
125 { 0x45, 0x6000 },
126 { 0x46, 0x003e },
127 { 0x47, 0x003e },
128 { 0x48, 0xf807 },
129 { 0x4a, 0x0004 },
130 { 0x4d, 0x0000 },
131 { 0x4e, 0x0000 },
132 { 0x4f, 0x01ff },
133 { 0x50, 0x0000 },
134 { 0x51, 0x0000 },
135 { 0x52, 0x01ff },
136 { 0x53, 0xf000 },
137 { 0x56, 0x0111 },
138 { 0x57, 0x0064 },
139 { 0x58, 0xef0e },
140 { 0x59, 0xf0f0 },
141 { 0x5a, 0xef0e },
142 { 0x5b, 0xf0f0 },
143 { 0x5c, 0xef0e },
144 { 0x5d, 0xf0f0 },
145 { 0x5e, 0xf000 },
146 { 0x5f, 0x0000 },
147 { 0x61, 0x0300 },
148 { 0x62, 0x0000 },
149 { 0x63, 0x00c2 },
150 { 0x64, 0x0000 },
151 { 0x65, 0x0000 },
152 { 0x66, 0x0000 },
153 { 0x6a, 0x0000 },
154 { 0x6c, 0x0aaa },
155 { 0x70, 0x8000 },
156 { 0x71, 0x8000 },
157 { 0x72, 0x8000 },
158 { 0x73, 0x7770 },
159 { 0x74, 0x3e00 },
160 { 0x75, 0x2409 },
161 { 0x76, 0x000a },
162 { 0x77, 0x0c00 },
163 { 0x78, 0x0000 },
164 { 0x79, 0x0123 },
165 { 0x80, 0x0000 },
166 { 0x81, 0x0000 },
167 { 0x82, 0x0000 },
168 { 0x83, 0x0000 },
169 { 0x84, 0x0000 },
170 { 0x85, 0x0000 },
171 { 0x8a, 0x0120 },
172 { 0x8e, 0x0004 },
173 { 0x8f, 0x1100 },
174 { 0x90, 0x0646 },
175 { 0x91, 0x0c06 },
176 { 0x93, 0x0000 },
177 { 0x94, 0x0200 },
178 { 0x95, 0x0000 },
179 { 0x9a, 0x2184 },
180 { 0x9b, 0x010a },
181 { 0x9c, 0x0aea },
182 { 0x9d, 0x000c },
183 { 0x9e, 0x0400 },
184 { 0xa0, 0xa0a8 },
185 { 0xa1, 0x0059 },
186 { 0xa2, 0x0001 },
187 { 0xae, 0x6000 },
188 { 0xaf, 0x0000 },
189 { 0xb0, 0x6000 },
190 { 0xb1, 0x0000 },
191 { 0xb2, 0x0000 },
192 { 0xb3, 0x001f },
193 { 0xb4, 0x020c },
194 { 0xb5, 0x1f00 },
195 { 0xb6, 0x0000 },
196 { 0xbb, 0x0000 },
197 { 0xbc, 0x0000 },
198 { 0xbd, 0x0000 },
199 { 0xbe, 0x0000 },
200 { 0xbf, 0x3100 },
201 { 0xc0, 0x0000 },
202 { 0xc1, 0x0000 },
203 { 0xc2, 0x0000 },
204 { 0xc3, 0x2000 },
205 { 0xcd, 0x0000 },
206 { 0xce, 0x0000 },
207 { 0xcf, 0x1813 },
208 { 0xd0, 0x0690 },
209 { 0xd1, 0x1c17 },
210 { 0xd3, 0xb320 },
211 { 0xd4, 0x0000 },
212 { 0xd6, 0x0400 },
213 { 0xd9, 0x0809 },
214 { 0xda, 0x0000 },
215 { 0xdb, 0x0003 },
216 { 0xdc, 0x0049 },
217 { 0xdd, 0x001b },
218 { 0xdf, 0x0008 },
219 { 0xe0, 0x4000 },
220 { 0xe6, 0x8000 },
221 { 0xe7, 0x0200 },
222 { 0xec, 0xb300 },
223 { 0xed, 0x0000 },
224 { 0xf0, 0x001f },
225 { 0xf1, 0x020c },
226 { 0xf2, 0x1f00 },
227 { 0xf3, 0x0000 },
228 { 0xf4, 0x4000 },
229 { 0xf8, 0x0000 },
230 { 0xf9, 0x0000 },
231 { 0xfa, 0x2060 },
232 { 0xfb, 0x4040 },
233 { 0xfc, 0x0000 },
234 { 0xfd, 0x0002 },
235 { 0xfe, 0x10ec },
236 { 0xff, 0x6308 },
237};
238
239static const struct reg_default rt5650_reg[] = {
240 { 0x00, 0x0000 },
241 { 0x01, 0xc8c8 },
242 { 0x02, 0xc8c8 },
243 { 0x03, 0xc8c8 },
244 { 0x0a, 0x0002 },
245 { 0x0b, 0x2827 },
246 { 0x0c, 0xe000 },
247 { 0x0d, 0x0000 },
248 { 0x0e, 0x0000 },
249 { 0x0f, 0x0808 },
250 { 0x14, 0x3333 },
251 { 0x16, 0x4b00 },
252 { 0x18, 0x018b },
253 { 0x19, 0xafaf },
254 { 0x1a, 0xafaf },
255 { 0x1b, 0x0001 },
256 { 0x1c, 0x2f2f },
257 { 0x1d, 0x2f2f },
258 { 0x1e, 0x0000 },
259 { 0x20, 0x0000 },
260 { 0x27, 0x7060 },
261 { 0x28, 0x7070 },
262 { 0x29, 0x8080 },
263 { 0x2a, 0x5656 },
264 { 0x2b, 0x5454 },
265 { 0x2c, 0xaaa0 },
266 { 0x2d, 0x0000 },
267 { 0x2f, 0x5002 },
268 { 0x31, 0x5000 },
269 { 0x32, 0x0000 },
270 { 0x33, 0x0000 },
271 { 0x34, 0x0000 },
272 { 0x35, 0x0000 },
273 { 0x3b, 0x0000 },
274 { 0x3c, 0x007f },
275 { 0x3d, 0x0000 },
276 { 0x3e, 0x007f },
277 { 0x3f, 0x0000 },
278 { 0x40, 0x001f },
279 { 0x41, 0x0000 },
280 { 0x42, 0x001f },
281 { 0x45, 0x6000 },
282 { 0x46, 0x003e },
283 { 0x47, 0x003e },
284 { 0x48, 0xf807 },
285 { 0x4a, 0x0004 },
286 { 0x4d, 0x0000 },
287 { 0x4e, 0x0000 },
288 { 0x4f, 0x01ff },
289 { 0x50, 0x0000 },
290 { 0x51, 0x0000 },
291 { 0x52, 0x01ff },
292 { 0x53, 0xf000 },
293 { 0x56, 0x0111 },
294 { 0x57, 0x0064 },
295 { 0x58, 0xef0e },
296 { 0x59, 0xf0f0 },
297 { 0x5a, 0xef0e },
298 { 0x5b, 0xf0f0 },
299 { 0x5c, 0xef0e },
300 { 0x5d, 0xf0f0 },
301 { 0x5e, 0xf000 },
302 { 0x5f, 0x0000 },
303 { 0x61, 0x0300 },
304 { 0x62, 0x0000 },
305 { 0x63, 0x00c2 },
306 { 0x64, 0x0000 },
307 { 0x65, 0x0000 },
308 { 0x66, 0x0000 },
309 { 0x6a, 0x0000 },
310 { 0x6c, 0x0aaa },
311 { 0x70, 0x8000 },
312 { 0x71, 0x8000 },
313 { 0x72, 0x8000 },
314 { 0x73, 0x7770 },
315 { 0x74, 0x3e00 },
316 { 0x75, 0x2409 },
317 { 0x76, 0x000a },
318 { 0x77, 0x0c00 },
319 { 0x78, 0x0000 },
320 { 0x79, 0x0123 },
321 { 0x7a, 0x0123 },
322 { 0x80, 0x0000 },
323 { 0x81, 0x0000 },
324 { 0x82, 0x0000 },
325 { 0x83, 0x0000 },
326 { 0x84, 0x0000 },
327 { 0x85, 0x0000 },
328 { 0x8a, 0x0120 },
329 { 0x8e, 0x0004 },
330 { 0x8f, 0x1100 },
331 { 0x90, 0x0646 },
332 { 0x91, 0x0c06 },
333 { 0x93, 0x0000 },
334 { 0x94, 0x0200 },
335 { 0x95, 0x0000 },
336 { 0x9a, 0x2184 },
337 { 0x9b, 0x010a },
338 { 0x9c, 0x0aea },
339 { 0x9d, 0x000c },
340 { 0x9e, 0x0400 },
341 { 0xa0, 0xa0a8 },
342 { 0xa1, 0x0059 },
343 { 0xa2, 0x0001 },
344 { 0xae, 0x6000 },
345 { 0xaf, 0x0000 },
346 { 0xb0, 0x6000 },
347 { 0xb1, 0x0000 },
348 { 0xb2, 0x0000 },
349 { 0xb3, 0x001f },
350 { 0xb4, 0x020c },
351 { 0xb5, 0x1f00 },
352 { 0xb6, 0x0000 },
353 { 0xbb, 0x0000 },
354 { 0xbc, 0x0000 },
355 { 0xbd, 0x0000 },
356 { 0xbe, 0x0000 },
357 { 0xbf, 0x3100 },
358 { 0xc0, 0x0000 },
359 { 0xc1, 0x0000 },
360 { 0xc2, 0x0000 },
361 { 0xc3, 0x2000 },
362 { 0xcd, 0x0000 },
363 { 0xce, 0x0000 },
364 { 0xcf, 0x1813 },
365 { 0xd0, 0x0690 },
366 { 0xd1, 0x1c17 },
367 { 0xd3, 0xb320 },
368 { 0xd4, 0x0000 },
369 { 0xd6, 0x0400 },
370 { 0xd9, 0x0809 },
371 { 0xda, 0x0000 },
372 { 0xdb, 0x0003 },
373 { 0xdc, 0x0049 },
374 { 0xdd, 0x001b },
375 { 0xdf, 0x0008 },
376 { 0xe0, 0x4000 },
377 { 0xe6, 0x8000 },
378 { 0xe7, 0x0200 },
379 { 0xec, 0xb300 },
380 { 0xed, 0x0000 },
381 { 0xf0, 0x001f },
382 { 0xf1, 0x020c },
383 { 0xf2, 0x1f00 },
384 { 0xf3, 0x0000 },
385 { 0xf4, 0x4000 },
386 { 0xf8, 0x0000 },
387 { 0xf9, 0x0000 },
388 { 0xfa, 0x2060 },
389 { 0xfb, 0x4040 },
390 { 0xfc, 0x0000 },
391 { 0xfd, 0x0002 },
392 { 0xfe, 0x10ec },
393 { 0xff, 0x6308 },
394};
395
396struct rt5645_eq_param_s {
397 unsigned short reg;
398 unsigned short val;
399};
400
401struct rt5645_eq_param_s_be16 {
402 __be16 reg;
403 __be16 val;
404};
405
406static const char *const rt5645_supply_names[] = {
407 "avdd",
408 "cpvdd",
409};
410
411struct rt5645_priv {
412 struct snd_soc_component *component;
413 struct rt5645_platform_data pdata;
414 struct regmap *regmap;
415 struct i2c_client *i2c;
416 struct gpio_desc *gpiod_hp_det;
417 struct gpio_desc *gpiod_cbj_sleeve;
418 struct snd_soc_jack *hp_jack;
419 struct snd_soc_jack *mic_jack;
420 struct snd_soc_jack *btn_jack;
421 struct delayed_work jack_detect_work, rcclock_work;
422 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
423 struct rt5645_eq_param_s *eq_param;
424 struct timer_list btn_check_timer;
425 struct mutex jd_mutex;
426
427 int codec_type;
428 int sysclk;
429 int sysclk_src;
430 int lrck[RT5645_AIFS];
431 int bclk[RT5645_AIFS];
432 int master[RT5645_AIFS];
433
434 int pll_src;
435 int pll_in;
436 int pll_out;
437
438 int jack_type;
439 bool en_button_func;
440 bool hp_on;
441 int v_id;
442};
443
444static int rt5645_reset(struct snd_soc_component *component)
445{
446 return snd_soc_component_write(component, RT5645_RESET, 0);
447}
448
449static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
450{
451 int i;
452
453 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
454 if (reg >= rt5645_ranges[i].range_min &&
455 reg <= rt5645_ranges[i].range_max) {
456 return true;
457 }
458 }
459
460 switch (reg) {
461 case RT5645_RESET:
462 case RT5645_PRIV_INDEX:
463 case RT5645_PRIV_DATA:
464 case RT5645_IN1_CTRL1:
465 case RT5645_IN1_CTRL2:
466 case RT5645_IN1_CTRL3:
467 case RT5645_A_JD_CTRL1:
468 case RT5645_ADC_EQ_CTRL1:
469 case RT5645_EQ_CTRL1:
470 case RT5645_ALC_CTRL_1:
471 case RT5645_IRQ_CTRL2:
472 case RT5645_IRQ_CTRL3:
473 case RT5645_INT_IRQ_ST:
474 case RT5645_IL_CMD:
475 case RT5650_4BTN_IL_CMD1:
476 case RT5645_VENDOR_ID:
477 case RT5645_VENDOR_ID1:
478 case RT5645_VENDOR_ID2:
479 return true;
480 default:
481 return false;
482 }
483}
484
485static bool rt5645_readable_register(struct device *dev, unsigned int reg)
486{
487 int i;
488
489 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
490 if (reg >= rt5645_ranges[i].range_min &&
491 reg <= rt5645_ranges[i].range_max) {
492 return true;
493 }
494 }
495
496 switch (reg) {
497 case RT5645_RESET:
498 case RT5645_SPK_VOL:
499 case RT5645_HP_VOL:
500 case RT5645_LOUT1:
501 case RT5645_IN1_CTRL1:
502 case RT5645_IN1_CTRL2:
503 case RT5645_IN1_CTRL3:
504 case RT5645_IN2_CTRL:
505 case RT5645_INL1_INR1_VOL:
506 case RT5645_SPK_FUNC_LIM:
507 case RT5645_ADJ_HPF_CTRL:
508 case RT5645_DAC1_DIG_VOL:
509 case RT5645_DAC2_DIG_VOL:
510 case RT5645_DAC_CTRL:
511 case RT5645_STO1_ADC_DIG_VOL:
512 case RT5645_MONO_ADC_DIG_VOL:
513 case RT5645_ADC_BST_VOL1:
514 case RT5645_ADC_BST_VOL2:
515 case RT5645_STO1_ADC_MIXER:
516 case RT5645_MONO_ADC_MIXER:
517 case RT5645_AD_DA_MIXER:
518 case RT5645_STO_DAC_MIXER:
519 case RT5645_MONO_DAC_MIXER:
520 case RT5645_DIG_MIXER:
521 case RT5650_A_DAC_SOUR:
522 case RT5645_DIG_INF1_DATA:
523 case RT5645_PDM_OUT_CTRL:
524 case RT5645_REC_L1_MIXER:
525 case RT5645_REC_L2_MIXER:
526 case RT5645_REC_R1_MIXER:
527 case RT5645_REC_R2_MIXER:
528 case RT5645_HPMIXL_CTRL:
529 case RT5645_HPOMIXL_CTRL:
530 case RT5645_HPMIXR_CTRL:
531 case RT5645_HPOMIXR_CTRL:
532 case RT5645_HPO_MIXER:
533 case RT5645_SPK_L_MIXER:
534 case RT5645_SPK_R_MIXER:
535 case RT5645_SPO_MIXER:
536 case RT5645_SPO_CLSD_RATIO:
537 case RT5645_OUT_L1_MIXER:
538 case RT5645_OUT_R1_MIXER:
539 case RT5645_OUT_L_GAIN1:
540 case RT5645_OUT_L_GAIN2:
541 case RT5645_OUT_R_GAIN1:
542 case RT5645_OUT_R_GAIN2:
543 case RT5645_LOUT_MIXER:
544 case RT5645_HAPTIC_CTRL1:
545 case RT5645_HAPTIC_CTRL2:
546 case RT5645_HAPTIC_CTRL3:
547 case RT5645_HAPTIC_CTRL4:
548 case RT5645_HAPTIC_CTRL5:
549 case RT5645_HAPTIC_CTRL6:
550 case RT5645_HAPTIC_CTRL7:
551 case RT5645_HAPTIC_CTRL8:
552 case RT5645_HAPTIC_CTRL9:
553 case RT5645_HAPTIC_CTRL10:
554 case RT5645_PWR_DIG1:
555 case RT5645_PWR_DIG2:
556 case RT5645_PWR_ANLG1:
557 case RT5645_PWR_ANLG2:
558 case RT5645_PWR_MIXER:
559 case RT5645_PWR_VOL:
560 case RT5645_PRIV_INDEX:
561 case RT5645_PRIV_DATA:
562 case RT5645_I2S1_SDP:
563 case RT5645_I2S2_SDP:
564 case RT5645_ADDA_CLK1:
565 case RT5645_ADDA_CLK2:
566 case RT5645_DMIC_CTRL1:
567 case RT5645_DMIC_CTRL2:
568 case RT5645_TDM_CTRL_1:
569 case RT5645_TDM_CTRL_2:
570 case RT5645_TDM_CTRL_3:
571 case RT5650_TDM_CTRL_4:
572 case RT5645_GLB_CLK:
573 case RT5645_PLL_CTRL1:
574 case RT5645_PLL_CTRL2:
575 case RT5645_ASRC_1:
576 case RT5645_ASRC_2:
577 case RT5645_ASRC_3:
578 case RT5645_ASRC_4:
579 case RT5645_DEPOP_M1:
580 case RT5645_DEPOP_M2:
581 case RT5645_DEPOP_M3:
582 case RT5645_CHARGE_PUMP:
583 case RT5645_MICBIAS:
584 case RT5645_A_JD_CTRL1:
585 case RT5645_VAD_CTRL4:
586 case RT5645_CLSD_OUT_CTRL:
587 case RT5645_ADC_EQ_CTRL1:
588 case RT5645_ADC_EQ_CTRL2:
589 case RT5645_EQ_CTRL1:
590 case RT5645_EQ_CTRL2:
591 case RT5645_ALC_CTRL_1:
592 case RT5645_ALC_CTRL_2:
593 case RT5645_ALC_CTRL_3:
594 case RT5645_ALC_CTRL_4:
595 case RT5645_ALC_CTRL_5:
596 case RT5645_JD_CTRL:
597 case RT5645_IRQ_CTRL1:
598 case RT5645_IRQ_CTRL2:
599 case RT5645_IRQ_CTRL3:
600 case RT5645_INT_IRQ_ST:
601 case RT5645_GPIO_CTRL1:
602 case RT5645_GPIO_CTRL2:
603 case RT5645_GPIO_CTRL3:
604 case RT5645_BASS_BACK:
605 case RT5645_MP3_PLUS1:
606 case RT5645_MP3_PLUS2:
607 case RT5645_ADJ_HPF1:
608 case RT5645_ADJ_HPF2:
609 case RT5645_HP_CALIB_AMP_DET:
610 case RT5645_SV_ZCD1:
611 case RT5645_SV_ZCD2:
612 case RT5645_IL_CMD:
613 case RT5645_IL_CMD2:
614 case RT5645_IL_CMD3:
615 case RT5650_4BTN_IL_CMD1:
616 case RT5650_4BTN_IL_CMD2:
617 case RT5645_DRC1_HL_CTRL1:
618 case RT5645_DRC2_HL_CTRL1:
619 case RT5645_ADC_MONO_HP_CTRL1:
620 case RT5645_ADC_MONO_HP_CTRL2:
621 case RT5645_DRC2_CTRL1:
622 case RT5645_DRC2_CTRL2:
623 case RT5645_DRC2_CTRL3:
624 case RT5645_DRC2_CTRL4:
625 case RT5645_DRC2_CTRL5:
626 case RT5645_JD_CTRL3:
627 case RT5645_JD_CTRL4:
628 case RT5645_GEN_CTRL1:
629 case RT5645_GEN_CTRL2:
630 case RT5645_GEN_CTRL3:
631 case RT5645_VENDOR_ID:
632 case RT5645_VENDOR_ID1:
633 case RT5645_VENDOR_ID2:
634 return true;
635 default:
636 return false;
637 }
638}
639
640static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
641static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
642static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
643static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
644static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
645
646/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
647static const DECLARE_TLV_DB_RANGE(bst_tlv,
648 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
649 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
650 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
651 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
652 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
653 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
654 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
655);
656
657/* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */
658static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,
659 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),
660 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),
661 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),
662 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)
663);
664
665static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,
666 struct snd_ctl_elem_info *uinfo)
667{
668 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
669 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);
670
671 return 0;
672}
673
674static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,
675 struct snd_ctl_elem_value *ucontrol)
676{
677 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
678 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
679 struct rt5645_eq_param_s_be16 *eq_param =
680 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
681 int i;
682
683 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
684 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);
685 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);
686 }
687
688 return 0;
689}
690
691static bool rt5645_validate_hweq(unsigned short reg)
692{
693 if ((reg >= 0x1a4 && reg <= 0x1cd) | (reg >= 0x1e5 && reg <= 0x1f8) |
694 (reg == RT5645_EQ_CTRL2))
695 return true;
696
697 return false;
698}
699
700static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,
701 struct snd_ctl_elem_value *ucontrol)
702{
703 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
704 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
705 struct rt5645_eq_param_s_be16 *eq_param =
706 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
707 int i;
708
709 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
710 rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg);
711 rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val);
712 }
713
714 /* The final setting of the table should be RT5645_EQ_CTRL2 */
715 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {
716 if (rt5645->eq_param[i].reg == 0)
717 continue;
718 else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2)
719 return 0;
720 else
721 break;
722 }
723
724 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
725 if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) &&
726 rt5645->eq_param[i].reg != 0)
727 return 0;
728 else if (rt5645->eq_param[i].reg == 0)
729 break;
730 }
731
732 return 0;
733}
734
735#define RT5645_HWEQ(xname) \
736{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
737 .info = rt5645_hweq_info, \
738 .get = rt5645_hweq_get, \
739 .put = rt5645_hweq_put \
740}
741
742static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,
743 struct snd_ctl_elem_value *ucontrol)
744{
745 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
746 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
747 int ret;
748
749 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
750 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);
751
752 ret = snd_soc_put_volsw(kcontrol, ucontrol);
753
754 mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,
755 msecs_to_jiffies(200));
756
757 return ret;
758}
759
760static const char * const rt5645_dac1_vol_ctrl_mode_text[] = {
761 "immediately", "zero crossing", "soft ramp"
762};
763
764static SOC_ENUM_SINGLE_DECL(
765 rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE,
766 RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text);
767
768static const struct snd_kcontrol_new rt5645_snd_controls[] = {
769 /* Speaker Output Volume */
770 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
771 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
772 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
773 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,
774 rt5645_spk_put_volsw, out_vol_tlv),
775
776 /* ClassD modulator Speaker Gain Ratio */
777 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,
778 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),
779
780 /* Headphone Output Volume */
781 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
782 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
783 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
784 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
785
786 /* OUTPUT Control */
787 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
788 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
789 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
790 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
791 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
792 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
793
794 /* DAC Digital Volume */
795 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
796 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
797 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
798 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
799 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
800 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
801
802 /* IN1/IN2 Control */
803 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
804 RT5645_BST_SFT1, 12, 0, bst_tlv),
805 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
806 RT5645_BST_SFT2, 8, 0, bst_tlv),
807
808 /* INL/INR Volume Control */
809 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
810 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
811
812 /* ADC Digital Volume Control */
813 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
814 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
815 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
816 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
817 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
818 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
819 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
820 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
821
822 /* ADC Boost Volume Control */
823 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,
824 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
825 adc_bst_tlv),
826 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,
827 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,
828 adc_bst_tlv),
829
830 /* I2S2 function select */
831 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
832 1, 1),
833 RT5645_HWEQ("Speaker HWEQ"),
834
835 /* Digital Soft Volume Control */
836 SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode),
837};
838
839/**
840 * set_dmic_clk - Set parameter of dmic.
841 *
842 * @w: DAPM widget.
843 * @kcontrol: The kcontrol of this widget.
844 * @event: Event id.
845 *
846 */
847static int set_dmic_clk(struct snd_soc_dapm_widget *w,
848 struct snd_kcontrol *kcontrol, int event)
849{
850 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
851 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
852 int idx, rate;
853
854 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
855 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
856 idx = rl6231_calc_dmic_clk(rate);
857 if (idx < 0)
858 dev_err(component->dev, "Failed to set DMIC clock\n");
859 else
860 snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1,
861 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
862 return idx;
863}
864
865static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
866 struct snd_soc_dapm_widget *sink)
867{
868 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
869 unsigned int val;
870
871 val = snd_soc_component_read32(component, RT5645_GLB_CLK);
872 val &= RT5645_SCLK_SRC_MASK;
873 if (val == RT5645_SCLK_SRC_PLL1)
874 return 1;
875 else
876 return 0;
877}
878
879static int is_using_asrc(struct snd_soc_dapm_widget *source,
880 struct snd_soc_dapm_widget *sink)
881{
882 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
883 unsigned int reg, shift, val;
884
885 switch (source->shift) {
886 case 0:
887 reg = RT5645_ASRC_3;
888 shift = 0;
889 break;
890 case 1:
891 reg = RT5645_ASRC_3;
892 shift = 4;
893 break;
894 case 3:
895 reg = RT5645_ASRC_2;
896 shift = 0;
897 break;
898 case 8:
899 reg = RT5645_ASRC_2;
900 shift = 4;
901 break;
902 case 9:
903 reg = RT5645_ASRC_2;
904 shift = 8;
905 break;
906 case 10:
907 reg = RT5645_ASRC_2;
908 shift = 12;
909 break;
910 default:
911 return 0;
912 }
913
914 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
915 switch (val) {
916 case 1:
917 case 2:
918 case 3:
919 case 4:
920 return 1;
921 default:
922 return 0;
923 }
924
925}
926
927static int rt5645_enable_hweq(struct snd_soc_component *component)
928{
929 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
930 int i;
931
932 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
933 if (rt5645_validate_hweq(rt5645->eq_param[i].reg))
934 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,
935 rt5645->eq_param[i].val);
936 else
937 break;
938 }
939
940 return 0;
941}
942
943/**
944 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
945 * @component: SoC audio component device.
946 * @filter_mask: mask of filters.
947 * @clk_src: clock source
948 *
949 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
950 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
951 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
952 * ASRC function will track i2s clock and generate a corresponding system clock
953 * for codec. This function provides an API to select the clock source for a
954 * set of filters specified by the mask. And the codec driver will turn on ASRC
955 * for these filters if ASRC is selected as their clock source.
956 */
957int rt5645_sel_asrc_clk_src(struct snd_soc_component *component,
958 unsigned int filter_mask, unsigned int clk_src)
959{
960 unsigned int asrc2_mask = 0;
961 unsigned int asrc2_value = 0;
962 unsigned int asrc3_mask = 0;
963 unsigned int asrc3_value = 0;
964
965 switch (clk_src) {
966 case RT5645_CLK_SEL_SYS:
967 case RT5645_CLK_SEL_I2S1_ASRC:
968 case RT5645_CLK_SEL_I2S2_ASRC:
969 case RT5645_CLK_SEL_SYS2:
970 break;
971
972 default:
973 return -EINVAL;
974 }
975
976 if (filter_mask & RT5645_DA_STEREO_FILTER) {
977 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
978 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
979 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
980 }
981
982 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
983 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
984 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
985 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
986 }
987
988 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
989 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
990 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
991 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
992 }
993
994 if (filter_mask & RT5645_AD_STEREO_FILTER) {
995 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
996 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
997 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
998 }
999
1000 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
1001 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
1002 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
1003 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
1004 }
1005
1006 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
1007 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
1008 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
1009 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
1010 }
1011
1012 if (asrc2_mask)
1013 snd_soc_component_update_bits(component, RT5645_ASRC_2,
1014 asrc2_mask, asrc2_value);
1015
1016 if (asrc3_mask)
1017 snd_soc_component_update_bits(component, RT5645_ASRC_3,
1018 asrc3_mask, asrc3_value);
1019
1020 return 0;
1021}
1022EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
1023
1024/* Digital Mixer */
1025static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
1026 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1027 RT5645_M_ADC_L1_SFT, 1, 1),
1028 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1029 RT5645_M_ADC_L2_SFT, 1, 1),
1030};
1031
1032static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
1033 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1034 RT5645_M_ADC_R1_SFT, 1, 1),
1035 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1036 RT5645_M_ADC_R2_SFT, 1, 1),
1037};
1038
1039static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
1040 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1041 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
1042 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1043 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
1044};
1045
1046static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
1047 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1048 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
1049 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1050 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
1051};
1052
1053static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
1054 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1055 RT5645_M_ADCMIX_L_SFT, 1, 1),
1056 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1057 RT5645_M_DAC1_L_SFT, 1, 1),
1058};
1059
1060static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
1061 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1062 RT5645_M_ADCMIX_R_SFT, 1, 1),
1063 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1064 RT5645_M_DAC1_R_SFT, 1, 1),
1065};
1066
1067static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
1068 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1069 RT5645_M_DAC_L1_SFT, 1, 1),
1070 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
1071 RT5645_M_DAC_L2_SFT, 1, 1),
1072 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1073 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
1074};
1075
1076static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
1077 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1078 RT5645_M_DAC_R1_SFT, 1, 1),
1079 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
1080 RT5645_M_DAC_R2_SFT, 1, 1),
1081 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1082 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
1083};
1084
1085static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
1086 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
1087 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
1088 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1089 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
1090 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1091 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
1092};
1093
1094static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
1095 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
1096 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
1097 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1098 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
1099 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1100 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
1101};
1102
1103static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
1104 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
1105 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
1106 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1107 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
1108 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1109 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
1110};
1111
1112static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
1113 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
1114 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
1115 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1116 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
1117 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1118 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
1119};
1120
1121/* Analog Input Mixer */
1122static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
1123 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
1124 RT5645_M_HP_L_RM_L_SFT, 1, 1),
1125 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
1126 RT5645_M_IN_L_RM_L_SFT, 1, 1),
1127 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
1128 RT5645_M_BST2_RM_L_SFT, 1, 1),
1129 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
1130 RT5645_M_BST1_RM_L_SFT, 1, 1),
1131 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
1132 RT5645_M_OM_L_RM_L_SFT, 1, 1),
1133};
1134
1135static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
1136 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
1137 RT5645_M_HP_R_RM_R_SFT, 1, 1),
1138 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
1139 RT5645_M_IN_R_RM_R_SFT, 1, 1),
1140 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
1141 RT5645_M_BST2_RM_R_SFT, 1, 1),
1142 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
1143 RT5645_M_BST1_RM_R_SFT, 1, 1),
1144 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
1145 RT5645_M_OM_R_RM_R_SFT, 1, 1),
1146};
1147
1148static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
1149 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
1150 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
1151 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
1152 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
1153 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
1154 RT5645_M_IN_L_SM_L_SFT, 1, 1),
1155 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
1156 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
1157};
1158
1159static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
1160 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
1161 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
1162 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
1163 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
1164 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
1165 RT5645_M_IN_R_SM_R_SFT, 1, 1),
1166 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
1167 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
1168};
1169
1170static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
1171 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
1172 RT5645_M_BST1_OM_L_SFT, 1, 1),
1173 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
1174 RT5645_M_IN_L_OM_L_SFT, 1, 1),
1175 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
1176 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
1177 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
1178 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
1179};
1180
1181static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
1182 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
1183 RT5645_M_BST2_OM_R_SFT, 1, 1),
1184 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
1185 RT5645_M_IN_R_OM_R_SFT, 1, 1),
1186 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
1187 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
1188 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
1189 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
1190};
1191
1192static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
1193 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1194 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
1195 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
1196 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
1197 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1198 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
1199 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
1200 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
1201};
1202
1203static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
1204 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1205 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
1206 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1207 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
1208};
1209
1210static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
1211 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
1212 RT5645_M_DAC1_HM_SFT, 1, 1),
1213 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
1214 RT5645_M_HPVOL_HM_SFT, 1, 1),
1215};
1216
1217static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
1218 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
1219 RT5645_M_DAC1_HV_SFT, 1, 1),
1220 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
1221 RT5645_M_DAC2_HV_SFT, 1, 1),
1222 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
1223 RT5645_M_IN_HV_SFT, 1, 1),
1224 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
1225 RT5645_M_BST1_HV_SFT, 1, 1),
1226};
1227
1228static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
1229 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
1230 RT5645_M_DAC1_HV_SFT, 1, 1),
1231 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
1232 RT5645_M_DAC2_HV_SFT, 1, 1),
1233 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
1234 RT5645_M_IN_HV_SFT, 1, 1),
1235 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
1236 RT5645_M_BST2_HV_SFT, 1, 1),
1237};
1238
1239static const struct snd_kcontrol_new rt5645_lout_mix[] = {
1240 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
1241 RT5645_M_DAC_L1_LM_SFT, 1, 1),
1242 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
1243 RT5645_M_DAC_R1_LM_SFT, 1, 1),
1244 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
1245 RT5645_M_OV_L_LM_SFT, 1, 1),
1246 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
1247 RT5645_M_OV_R_LM_SFT, 1, 1),
1248};
1249
1250/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
1251static const char * const rt5645_dac1_src[] = {
1252 "IF1 DAC", "IF2 DAC", "IF3 DAC"
1253};
1254
1255static SOC_ENUM_SINGLE_DECL(
1256 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
1257 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
1258
1259static const struct snd_kcontrol_new rt5645_dac1l_mux =
1260 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
1261
1262static SOC_ENUM_SINGLE_DECL(
1263 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
1264 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
1265
1266static const struct snd_kcontrol_new rt5645_dac1r_mux =
1267 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
1268
1269/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
1270static const char * const rt5645_dac12_src[] = {
1271 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
1272};
1273
1274static SOC_ENUM_SINGLE_DECL(
1275 rt5645_dac2l_enum, RT5645_DAC_CTRL,
1276 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
1277
1278static const struct snd_kcontrol_new rt5645_dac_l2_mux =
1279 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
1280
1281static const char * const rt5645_dacr2_src[] = {
1282 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
1283};
1284
1285static SOC_ENUM_SINGLE_DECL(
1286 rt5645_dac2r_enum, RT5645_DAC_CTRL,
1287 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
1288
1289static const struct snd_kcontrol_new rt5645_dac_r2_mux =
1290 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
1291
1292/* Stereo1 ADC source */
1293/* MX-27 [12] */
1294static const char * const rt5645_stereo_adc1_src[] = {
1295 "DAC MIX", "ADC"
1296};
1297
1298static SOC_ENUM_SINGLE_DECL(
1299 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1300 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1301
1302static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1303 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1304
1305/* MX-27 [11] */
1306static const char * const rt5645_stereo_adc2_src[] = {
1307 "DAC MIX", "DMIC"
1308};
1309
1310static SOC_ENUM_SINGLE_DECL(
1311 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1312 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1313
1314static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1315 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1316
1317/* MX-27 [8] */
1318static const char * const rt5645_stereo_dmic_src[] = {
1319 "DMIC1", "DMIC2"
1320};
1321
1322static SOC_ENUM_SINGLE_DECL(
1323 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1324 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1325
1326static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1327 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1328
1329/* Mono ADC source */
1330/* MX-28 [12] */
1331static const char * const rt5645_mono_adc_l1_src[] = {
1332 "Mono DAC MIXL", "ADC"
1333};
1334
1335static SOC_ENUM_SINGLE_DECL(
1336 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1337 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1338
1339static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1340 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1341/* MX-28 [11] */
1342static const char * const rt5645_mono_adc_l2_src[] = {
1343 "Mono DAC MIXL", "DMIC"
1344};
1345
1346static SOC_ENUM_SINGLE_DECL(
1347 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1348 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1349
1350static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1351 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1352
1353/* MX-28 [8] */
1354static const char * const rt5645_mono_dmic_src[] = {
1355 "DMIC1", "DMIC2"
1356};
1357
1358static SOC_ENUM_SINGLE_DECL(
1359 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1360 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1361
1362static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1363 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1364/* MX-28 [1:0] */
1365static SOC_ENUM_SINGLE_DECL(
1366 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1367 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1368
1369static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1370 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1371/* MX-28 [4] */
1372static const char * const rt5645_mono_adc_r1_src[] = {
1373 "Mono DAC MIXR", "ADC"
1374};
1375
1376static SOC_ENUM_SINGLE_DECL(
1377 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1378 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1379
1380static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1381 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1382/* MX-28 [3] */
1383static const char * const rt5645_mono_adc_r2_src[] = {
1384 "Mono DAC MIXR", "DMIC"
1385};
1386
1387static SOC_ENUM_SINGLE_DECL(
1388 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1389 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1390
1391static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1392 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1393
1394/* MX-77 [9:8] */
1395static const char * const rt5645_if1_adc_in_src[] = {
1396 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1397 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1398};
1399
1400static SOC_ENUM_SINGLE_DECL(
1401 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1402 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1403
1404static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1405 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1406
1407/* MX-78 [4:0] */
1408static const char * const rt5650_if1_adc_in_src[] = {
1409 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1410 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1411 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1412 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1413 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1414 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1415
1416 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1417 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1418 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1419 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1420 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1421 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1422
1423 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1424 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1425 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1426 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1427 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1428 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1429
1430 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1431 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1432 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1433 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1434 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1435 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1436};
1437
1438static SOC_ENUM_SINGLE_DECL(
1439 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1440 0, rt5650_if1_adc_in_src);
1441
1442static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1443 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1444
1445/* MX-78 [15:14][13:12][11:10] */
1446static const char * const rt5645_tdm_adc_swap_select[] = {
1447 "L/R", "R/L", "L/L", "R/R"
1448};
1449
1450static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1451 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1452
1453static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1454 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1455
1456static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1457 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1458
1459static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1460 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1461
1462static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1463 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1464
1465static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1466 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1467
1468/* MX-77 [7:6][5:4][3:2] */
1469static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1470 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1471
1472static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1473 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1474
1475static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1476 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1477
1478static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1479 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1480
1481static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1482 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1483
1484static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1485 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1486
1487/* MX-79 [14:12][10:8][6:4][2:0] */
1488static const char * const rt5645_tdm_dac_swap_select[] = {
1489 "Slot0", "Slot1", "Slot2", "Slot3"
1490};
1491
1492static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1493 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1494
1495static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1496 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1497
1498static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1499 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1500
1501static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1502 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1503
1504static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1505 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1506
1507static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1508 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1509
1510static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1511 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1512
1513static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1514 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1515
1516/* MX-7a [14:12][10:8][6:4][2:0] */
1517static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1518 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1519
1520static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1521 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1522
1523static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1524 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1525
1526static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1527 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1528
1529static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1530 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1531
1532static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1533 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1534
1535static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1536 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1537
1538static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1539 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1540
1541/* MX-2d [3] [2] */
1542static const char * const rt5650_a_dac1_src[] = {
1543 "DAC1", "Stereo DAC Mixer"
1544};
1545
1546static SOC_ENUM_SINGLE_DECL(
1547 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1548 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1549
1550static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1551 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1552
1553static SOC_ENUM_SINGLE_DECL(
1554 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1555 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1556
1557static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1558 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1559
1560/* MX-2d [1] [0] */
1561static const char * const rt5650_a_dac2_src[] = {
1562 "Stereo DAC Mixer", "Mono DAC Mixer"
1563};
1564
1565static SOC_ENUM_SINGLE_DECL(
1566 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1567 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1568
1569static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1570 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1571
1572static SOC_ENUM_SINGLE_DECL(
1573 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1574 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1575
1576static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1577 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1578
1579/* MX-2F [13:12] */
1580static const char * const rt5645_if2_adc_in_src[] = {
1581 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1582};
1583
1584static SOC_ENUM_SINGLE_DECL(
1585 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1586 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1587
1588static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1589 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1590
1591/* MX-31 [15] [13] [11] [9] */
1592static const char * const rt5645_pdm_src[] = {
1593 "Mono DAC", "Stereo DAC"
1594};
1595
1596static SOC_ENUM_SINGLE_DECL(
1597 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1598 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1599
1600static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1601 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1602
1603static SOC_ENUM_SINGLE_DECL(
1604 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1605 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1606
1607static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1608 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1609
1610/* MX-9D [9:8] */
1611static const char * const rt5645_vad_adc_src[] = {
1612 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1613};
1614
1615static SOC_ENUM_SINGLE_DECL(
1616 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1617 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1618
1619static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1620 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1621
1622static const struct snd_kcontrol_new spk_l_vol_control =
1623 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1624 RT5645_L_MUTE_SFT, 1, 1);
1625
1626static const struct snd_kcontrol_new spk_r_vol_control =
1627 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1628 RT5645_R_MUTE_SFT, 1, 1);
1629
1630static const struct snd_kcontrol_new hp_l_vol_control =
1631 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1632 RT5645_L_MUTE_SFT, 1, 1);
1633
1634static const struct snd_kcontrol_new hp_r_vol_control =
1635 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1636 RT5645_R_MUTE_SFT, 1, 1);
1637
1638static const struct snd_kcontrol_new pdm1_l_vol_control =
1639 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1640 RT5645_M_PDM1_L, 1, 1);
1641
1642static const struct snd_kcontrol_new pdm1_r_vol_control =
1643 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1644 RT5645_M_PDM1_R, 1, 1);
1645
1646static void hp_amp_power(struct snd_soc_component *component, int on)
1647{
1648 static int hp_amp_power_count;
1649 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1650
1651 if (on) {
1652 if (hp_amp_power_count <= 0) {
1653 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1654 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100);
1655 snd_soc_component_write(component, RT5645_CHARGE_PUMP,
1656 0x0e06);
1657 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
1658 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1659 RT5645_HP_DCC_INT1, 0x9f01);
1660 msleep(20);
1661 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1662 RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
1663 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1664 0x3e, 0x7400);
1665 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
1666 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1667 RT5645_MAMP_INT_REG2, 0xfc00);
1668 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
1669 msleep(90);
1670 rt5645->hp_on = true;
1671 } else {
1672 /* depop parameters */
1673 snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
1674 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1675 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
1676 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1677 RT5645_HP_DCC_INT1, 0x9f01);
1678 mdelay(150);
1679 /* headphone amp power on */
1680 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1681 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1682 snd_soc_component_update_bits(component, RT5645_PWR_VOL,
1683 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1684 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1685 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1686 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1687 RT5645_PWR_HA,
1688 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1689 RT5645_PWR_HA);
1690 mdelay(5);
1691 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1692 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1693 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1694
1695 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1696 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1697 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1698 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1699 0x14, 0x1aaa);
1700 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1701 0x24, 0x0430);
1702 }
1703 }
1704 hp_amp_power_count++;
1705 } else {
1706 hp_amp_power_count--;
1707 if (hp_amp_power_count <= 0) {
1708 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1709 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1710 0x3e, 0x7400);
1711 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
1712 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1713 RT5645_MAMP_INT_REG2, 0xfc00);
1714 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
1715 msleep(100);
1716 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001);
1717
1718 } else {
1719 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1720 RT5645_HP_SG_MASK |
1721 RT5645_HP_L_SMT_MASK |
1722 RT5645_HP_R_SMT_MASK,
1723 RT5645_HP_SG_DIS |
1724 RT5645_HP_L_SMT_DIS |
1725 RT5645_HP_R_SMT_DIS);
1726 /* headphone amp power down */
1727 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000);
1728 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1729 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1730 RT5645_PWR_HA, 0);
1731 snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
1732 RT5645_DEPOP_MASK, 0);
1733 }
1734 }
1735 }
1736}
1737
1738static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1739 struct snd_kcontrol *kcontrol, int event)
1740{
1741 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1742 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1743
1744 switch (event) {
1745 case SND_SOC_DAPM_POST_PMU:
1746 hp_amp_power(component, 1);
1747 /* headphone unmute sequence */
1748 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1749 snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
1750 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1751 RT5645_CP_FQ3_MASK,
1752 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1753 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1754 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1755 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1756 RT5645_MAMP_INT_REG2, 0xfc00);
1757 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1758 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1759 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1760 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1761 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1762 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1763 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1764 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1765 msleep(40);
1766 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1767 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1768 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1769 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1770 }
1771 break;
1772
1773 case SND_SOC_DAPM_PRE_PMD:
1774 /* headphone mute sequence */
1775 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1776 snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
1777 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1778 RT5645_CP_FQ3_MASK,
1779 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1780 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1781 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1782 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1783 RT5645_MAMP_INT_REG2, 0xfc00);
1784 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1785 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1786 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1787 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1788 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1789 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1790 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1791 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1792 msleep(30);
1793 }
1794 hp_amp_power(component, 0);
1795 break;
1796
1797 default:
1798 return 0;
1799 }
1800
1801 return 0;
1802}
1803
1804static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1805 struct snd_kcontrol *kcontrol, int event)
1806{
1807 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1808
1809 switch (event) {
1810 case SND_SOC_DAPM_POST_PMU:
1811 rt5645_enable_hweq(component);
1812 snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
1813 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1814 RT5645_PWR_CLS_D_L,
1815 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1816 RT5645_PWR_CLS_D_L);
1817 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
1818 RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);
1819 break;
1820
1821 case SND_SOC_DAPM_PRE_PMD:
1822 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
1823 RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);
1824 snd_soc_component_write(component, RT5645_EQ_CTRL2, 0);
1825 snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
1826 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1827 RT5645_PWR_CLS_D_L, 0);
1828 break;
1829
1830 default:
1831 return 0;
1832 }
1833
1834 return 0;
1835}
1836
1837static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1838 struct snd_kcontrol *kcontrol, int event)
1839{
1840 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1841
1842 switch (event) {
1843 case SND_SOC_DAPM_POST_PMU:
1844 hp_amp_power(component, 1);
1845 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1846 RT5645_PWR_LM, RT5645_PWR_LM);
1847 snd_soc_component_update_bits(component, RT5645_LOUT1,
1848 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1849 break;
1850
1851 case SND_SOC_DAPM_PRE_PMD:
1852 snd_soc_component_update_bits(component, RT5645_LOUT1,
1853 RT5645_L_MUTE | RT5645_R_MUTE,
1854 RT5645_L_MUTE | RT5645_R_MUTE);
1855 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1856 RT5645_PWR_LM, 0);
1857 hp_amp_power(component, 0);
1858 break;
1859
1860 default:
1861 return 0;
1862 }
1863
1864 return 0;
1865}
1866
1867static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1868 struct snd_kcontrol *kcontrol, int event)
1869{
1870 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1871
1872 switch (event) {
1873 case SND_SOC_DAPM_POST_PMU:
1874 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
1875 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1876 break;
1877
1878 case SND_SOC_DAPM_PRE_PMD:
1879 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
1880 RT5645_PWR_BST2_P, 0);
1881 break;
1882
1883 default:
1884 return 0;
1885 }
1886
1887 return 0;
1888}
1889
1890static int rt5650_hp_event(struct snd_soc_dapm_widget *w,
1891 struct snd_kcontrol *k, int event)
1892{
1893 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1894 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1895
1896 switch (event) {
1897 case SND_SOC_DAPM_POST_PMU:
1898 if (rt5645->hp_on) {
1899 msleep(100);
1900 rt5645->hp_on = false;
1901 }
1902 break;
1903
1904 default:
1905 return 0;
1906 }
1907
1908 return 0;
1909}
1910
1911static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w,
1912 struct snd_kcontrol *k, int event)
1913{
1914 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1915
1916 switch (event) {
1917 case SND_SOC_DAPM_PRE_PMU:
1918 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1919 RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
1920 RT5645_MICBIAS1_POW_CTRL_SEL_M);
1921 break;
1922
1923 case SND_SOC_DAPM_POST_PMD:
1924 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1925 RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
1926 RT5645_MICBIAS1_POW_CTRL_SEL_A);
1927 break;
1928
1929 default:
1930 return 0;
1931 }
1932
1933 return 0;
1934}
1935
1936static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w,
1937 struct snd_kcontrol *k, int event)
1938{
1939 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1940
1941 switch (event) {
1942 case SND_SOC_DAPM_PRE_PMU:
1943 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1944 RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
1945 RT5645_MICBIAS2_POW_CTRL_SEL_M);
1946 break;
1947
1948 case SND_SOC_DAPM_POST_PMD:
1949 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1950 RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
1951 RT5645_MICBIAS2_POW_CTRL_SEL_A);
1952 break;
1953
1954 default:
1955 return 0;
1956 }
1957
1958 return 0;
1959}
1960
1961static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1962 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1963 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1964 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1965 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1966
1967 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1968 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1969 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1970 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1971
1972 /* ASRC */
1973 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1974 11, 0, NULL, 0),
1975 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1976 12, 0, NULL, 0),
1977 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1978 10, 0, NULL, 0),
1979 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1980 9, 0, NULL, 0),
1981 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1982 8, 0, NULL, 0),
1983 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1984 7, 0, NULL, 0),
1985 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1986 5, 0, NULL, 0),
1987 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1988 4, 0, NULL, 0),
1989 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1990 3, 0, NULL, 0),
1991 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1992 1, 0, NULL, 0),
1993 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1994 0, 0, NULL, 0),
1995
1996 /* Input Side */
1997 /* micbias */
1998 SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2,
1999 RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event,
2000 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2001 SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2,
2002 RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event,
2003 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2004 /* Input Lines */
2005 SND_SOC_DAPM_INPUT("DMIC L1"),
2006 SND_SOC_DAPM_INPUT("DMIC R1"),
2007 SND_SOC_DAPM_INPUT("DMIC L2"),
2008 SND_SOC_DAPM_INPUT("DMIC R2"),
2009
2010 SND_SOC_DAPM_INPUT("IN1P"),
2011 SND_SOC_DAPM_INPUT("IN1N"),
2012 SND_SOC_DAPM_INPUT("IN2P"),
2013 SND_SOC_DAPM_INPUT("IN2N"),
2014
2015 SND_SOC_DAPM_INPUT("Haptic Generator"),
2016
2017 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2018 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2019 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2020 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2021 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
2022 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
2023 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
2024 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
2025 /* Boost */
2026 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
2027 RT5645_PWR_BST1_BIT, 0, NULL, 0),
2028 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
2029 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
2030 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2031 /* Input Volume */
2032 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
2033 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
2034 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
2035 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
2036 /* REC Mixer */
2037 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
2038 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
2039 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
2040 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
2041 /* ADCs */
2042 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2043 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2044
2045 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
2046 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
2047 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
2048 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
2049
2050 /* ADC Mux */
2051 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2052 &rt5645_sto1_dmic_mux),
2053 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2054 &rt5645_sto_adc2_mux),
2055 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2056 &rt5645_sto_adc2_mux),
2057 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2058 &rt5645_sto_adc1_mux),
2059 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2060 &rt5645_sto_adc1_mux),
2061 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2062 &rt5645_mono_dmic_l_mux),
2063 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2064 &rt5645_mono_dmic_r_mux),
2065 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2066 &rt5645_mono_adc_l2_mux),
2067 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2068 &rt5645_mono_adc_l1_mux),
2069 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2070 &rt5645_mono_adc_r1_mux),
2071 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2072 &rt5645_mono_adc_r2_mux),
2073 /* ADC Mixer */
2074
2075 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
2076 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
2077 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2078 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
2079 NULL, 0),
2080 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2081 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
2082 NULL, 0),
2083 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
2084 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2085 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2086 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
2087 NULL, 0),
2088 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
2089 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2090 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2091 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
2092 NULL, 0),
2093
2094 /* ADC PGA */
2095 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2096 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2097 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2098 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2099 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2100 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2101 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2102 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2103 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2104 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2105
2106 /* IF1 2 Mux */
2107 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
2108 0, 0, &rt5645_if2_adc_in_mux),
2109
2110 /* Digital Interface */
2111 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
2112 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
2113 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2114 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2115 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2116 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2117 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2118 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2119 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2120 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
2121 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
2122 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2123 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2124 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2125 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2126
2127 /* Digital Interface Select */
2128 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
2129 0, 0, &rt5645_vad_adc_mux),
2130
2131 /* Audio Interface */
2132 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2133 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2134 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2135 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2136
2137 /* Output Side */
2138 /* DAC mixer before sound effect */
2139 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2140 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
2141 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2142 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
2143
2144 /* DAC2 channel Mux */
2145 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
2146 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
2147 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
2148 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
2149 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
2150 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
2151
2152 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
2153 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
2154
2155 /* DAC Mixer */
2156 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
2157 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
2158 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
2159 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2160 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
2161 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2162 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2163 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
2164 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2165 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
2166 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2167 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
2168 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2169 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
2170 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2171 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
2172 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2173 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
2174
2175 /* DACs */
2176 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
2177 0),
2178 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
2179 0),
2180 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
2181 0),
2182 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
2183 0),
2184 /* OUT Mixer */
2185 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
2186 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
2187 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
2188 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
2189 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
2190 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
2191 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
2192 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
2193 /* Ouput Volume */
2194 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
2195 &spk_l_vol_control),
2196 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
2197 &spk_r_vol_control),
2198 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
2199 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
2200 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
2201 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
2202 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
2203 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
2204 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
2205 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
2206 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
2207 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
2208 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
2209 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
2210 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
2211
2212 /* HPO/LOUT/Mono Mixer */
2213 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
2214 ARRAY_SIZE(rt5645_spo_l_mix)),
2215 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
2216 ARRAY_SIZE(rt5645_spo_r_mix)),
2217 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
2218 ARRAY_SIZE(rt5645_hpo_mix)),
2219 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
2220 ARRAY_SIZE(rt5645_lout_mix)),
2221
2222 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
2223 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2224 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
2225 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2226 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
2227 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2228
2229 /* PDM */
2230 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
2231 0, NULL, 0),
2232 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
2233 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
2234
2235 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
2236 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
2237
2238 /* Output Lines */
2239 SND_SOC_DAPM_OUTPUT("HPOL"),
2240 SND_SOC_DAPM_OUTPUT("HPOR"),
2241 SND_SOC_DAPM_OUTPUT("LOUTL"),
2242 SND_SOC_DAPM_OUTPUT("LOUTR"),
2243 SND_SOC_DAPM_OUTPUT("PDM1L"),
2244 SND_SOC_DAPM_OUTPUT("PDM1R"),
2245 SND_SOC_DAPM_OUTPUT("SPOL"),
2246 SND_SOC_DAPM_OUTPUT("SPOR"),
2247 SND_SOC_DAPM_POST("DAPM_POST", rt5650_hp_event),
2248};
2249
2250static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
2251 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2252 &rt5645_if1_dac0_tdm_sel_mux),
2253 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2254 &rt5645_if1_dac1_tdm_sel_mux),
2255 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2256 &rt5645_if1_dac2_tdm_sel_mux),
2257 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2258 &rt5645_if1_dac3_tdm_sel_mux),
2259 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
2260 0, 0, &rt5645_if1_adc_in_mux),
2261 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2262 0, 0, &rt5645_if1_adc1_in_mux),
2263 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2264 0, 0, &rt5645_if1_adc2_in_mux),
2265 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2266 0, 0, &rt5645_if1_adc3_in_mux),
2267};
2268
2269static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
2270 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
2271 0, 0, &rt5650_a_dac1_l_mux),
2272 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
2273 0, 0, &rt5650_a_dac1_r_mux),
2274 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
2275 0, 0, &rt5650_a_dac2_l_mux),
2276 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
2277 0, 0, &rt5650_a_dac2_r_mux),
2278
2279 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2280 0, 0, &rt5650_if1_adc1_in_mux),
2281 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2282 0, 0, &rt5650_if1_adc2_in_mux),
2283 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2284 0, 0, &rt5650_if1_adc3_in_mux),
2285 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
2286 0, 0, &rt5650_if1_adc_in_mux),
2287
2288 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2289 &rt5650_if1_dac0_tdm_sel_mux),
2290 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2291 &rt5650_if1_dac1_tdm_sel_mux),
2292 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2293 &rt5650_if1_dac2_tdm_sel_mux),
2294 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2295 &rt5650_if1_dac3_tdm_sel_mux),
2296};
2297
2298static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
2299 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2300 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2301 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2302 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
2303 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
2304 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2305
2306 { "I2S1", NULL, "I2S1 ASRC" },
2307 { "I2S2", NULL, "I2S2 ASRC" },
2308
2309 { "IN1P", NULL, "LDO2" },
2310 { "IN2P", NULL, "LDO2" },
2311
2312 { "DMIC1", NULL, "DMIC L1" },
2313 { "DMIC1", NULL, "DMIC R1" },
2314 { "DMIC2", NULL, "DMIC L2" },
2315 { "DMIC2", NULL, "DMIC R2" },
2316
2317 { "BST1", NULL, "IN1P" },
2318 { "BST1", NULL, "IN1N" },
2319 { "BST1", NULL, "JD Power" },
2320 { "BST1", NULL, "Mic Det Power" },
2321 { "BST2", NULL, "IN2P" },
2322 { "BST2", NULL, "IN2N" },
2323
2324 { "INL VOL", NULL, "IN2P" },
2325 { "INR VOL", NULL, "IN2N" },
2326
2327 { "RECMIXL", "HPOL Switch", "HPOL" },
2328 { "RECMIXL", "INL Switch", "INL VOL" },
2329 { "RECMIXL", "BST2 Switch", "BST2" },
2330 { "RECMIXL", "BST1 Switch", "BST1" },
2331 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
2332
2333 { "RECMIXR", "HPOR Switch", "HPOR" },
2334 { "RECMIXR", "INR Switch", "INR VOL" },
2335 { "RECMIXR", "BST2 Switch", "BST2" },
2336 { "RECMIXR", "BST1 Switch", "BST1" },
2337 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
2338
2339 { "ADC L", NULL, "RECMIXL" },
2340 { "ADC L", NULL, "ADC L power" },
2341 { "ADC R", NULL, "RECMIXR" },
2342 { "ADC R", NULL, "ADC R power" },
2343
2344 {"DMIC L1", NULL, "DMIC CLK"},
2345 {"DMIC L1", NULL, "DMIC1 Power"},
2346 {"DMIC R1", NULL, "DMIC CLK"},
2347 {"DMIC R1", NULL, "DMIC1 Power"},
2348 {"DMIC L2", NULL, "DMIC CLK"},
2349 {"DMIC L2", NULL, "DMIC2 Power"},
2350 {"DMIC R2", NULL, "DMIC CLK"},
2351 {"DMIC R2", NULL, "DMIC2 Power"},
2352
2353 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2354 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2355 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
2356
2357 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
2358 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
2359 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
2360
2361 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2362 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
2363 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
2364
2365 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2366 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2367 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
2368 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2369
2370 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
2371 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2372 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2373 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2374
2375 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2376 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2377 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2378 { "Mono ADC L1 Mux", "ADC", "ADC L" },
2379
2380 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2381 { "Mono ADC R1 Mux", "ADC", "ADC R" },
2382 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2383 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2384
2385 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2386 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2387 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2388 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2389
2390 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2391 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2392 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2393
2394 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2395 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2396 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2397
2398 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2399 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2400 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2401 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2402
2403 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2404 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2405 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2406 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2407
2408 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2409 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2410 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2411
2412 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2413 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2414 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2415 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2416 { "VAD_ADC", NULL, "VAD ADC Mux" },
2417
2418 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2419 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2420 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2421
2422 { "IF1 ADC", NULL, "I2S1" },
2423 { "IF2 ADC", NULL, "I2S2" },
2424 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2425
2426 { "AIF2TX", NULL, "IF2 ADC" },
2427
2428 { "IF1 DAC0", NULL, "AIF1RX" },
2429 { "IF1 DAC1", NULL, "AIF1RX" },
2430 { "IF1 DAC2", NULL, "AIF1RX" },
2431 { "IF1 DAC3", NULL, "AIF1RX" },
2432 { "IF2 DAC", NULL, "AIF2RX" },
2433
2434 { "IF1 DAC0", NULL, "I2S1" },
2435 { "IF1 DAC1", NULL, "I2S1" },
2436 { "IF1 DAC2", NULL, "I2S1" },
2437 { "IF1 DAC3", NULL, "I2S1" },
2438 { "IF2 DAC", NULL, "I2S2" },
2439
2440 { "IF2 DAC L", NULL, "IF2 DAC" },
2441 { "IF2 DAC R", NULL, "IF2 DAC" },
2442
2443 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
2444 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2445
2446 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2447 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2448 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2449 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2450 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2451 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2452
2453 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2454 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2455 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2456 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2457 { "DAC L2 Volume", NULL, "dac mono left filter" },
2458
2459 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2460 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2461 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2462 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2463 { "DAC R2 Volume", NULL, "dac mono right filter" },
2464
2465 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2466 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2467 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2468 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2469 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2470 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2471 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2472 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2473
2474 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2475 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2476 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2477 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2478 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2479 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2480 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2481 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2482
2483 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2484 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2485 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2486 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2487 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2488 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2489
2490 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
2491 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
2492 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
2493 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2494
2495 { "SPK MIXL", "BST1 Switch", "BST1" },
2496 { "SPK MIXL", "INL Switch", "INL VOL" },
2497 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2498 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2499 { "SPK MIXR", "BST2 Switch", "BST2" },
2500 { "SPK MIXR", "INR Switch", "INR VOL" },
2501 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2502 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2503
2504 { "OUT MIXL", "BST1 Switch", "BST1" },
2505 { "OUT MIXL", "INL Switch", "INL VOL" },
2506 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2507 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2508
2509 { "OUT MIXR", "BST2 Switch", "BST2" },
2510 { "OUT MIXR", "INR Switch", "INR VOL" },
2511 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2512 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2513
2514 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2515 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2516 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2517 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2518 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2519 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2520 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2521 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2522 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2523 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2524
2525 { "DAC 2", NULL, "DAC L2" },
2526 { "DAC 2", NULL, "DAC R2" },
2527 { "DAC 1", NULL, "DAC L1" },
2528 { "DAC 1", NULL, "DAC R1" },
2529 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2530 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2531 { "HPOVOL", NULL, "HPOVOL L" },
2532 { "HPOVOL", NULL, "HPOVOL R" },
2533 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2534 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2535
2536 { "SPKVOL L", "Switch", "SPK MIXL" },
2537 { "SPKVOL R", "Switch", "SPK MIXR" },
2538
2539 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2540 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2541 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2542 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2543
2544 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2545 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2546 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2547 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2548
2549 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2550 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2551 { "PDM1 L Mux", NULL, "PDM1 Power" },
2552 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2553 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2554 { "PDM1 R Mux", NULL, "PDM1 Power" },
2555
2556 { "HP amp", NULL, "HPO MIX" },
2557 { "HP amp", NULL, "JD Power" },
2558 { "HP amp", NULL, "Mic Det Power" },
2559 { "HP amp", NULL, "LDO2" },
2560 { "HPOL", NULL, "HP amp" },
2561 { "HPOR", NULL, "HP amp" },
2562
2563 { "LOUT amp", NULL, "LOUT MIX" },
2564 { "LOUTL", NULL, "LOUT amp" },
2565 { "LOUTR", NULL, "LOUT amp" },
2566
2567 { "PDM1 L", "Switch", "PDM1 L Mux" },
2568 { "PDM1 R", "Switch", "PDM1 R Mux" },
2569
2570 { "PDM1L", NULL, "PDM1 L" },
2571 { "PDM1R", NULL, "PDM1 R" },
2572
2573 { "SPK amp", NULL, "SPOL MIX" },
2574 { "SPK amp", NULL, "SPOR MIX" },
2575 { "SPOL", NULL, "SPK amp" },
2576 { "SPOR", NULL, "SPK amp" },
2577};
2578
2579static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2580 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2581 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2582 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2583 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2584
2585 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2586 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2587 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2588 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2589
2590 { "DAC L1", NULL, "A DAC1 L Mux" },
2591 { "DAC R1", NULL, "A DAC1 R Mux" },
2592 { "DAC L2", NULL, "A DAC2 L Mux" },
2593 { "DAC R2", NULL, "A DAC2 R Mux" },
2594
2595 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2596 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2597 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2598 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2599
2600 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2601 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2602 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2603 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2604
2605 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2606 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2607 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2608 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2609
2610 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2611 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2612 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2613
2614 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2615 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2616 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2617 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2618 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2619 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2620
2621 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2622 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2623 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2624 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2625 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2626 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2627
2628 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2629 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2630 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2631 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2632 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2633 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2634
2635 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2636 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2637 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2638 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2639 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2640 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2641 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2642
2643 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2644 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2645 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2646 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2647
2648 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2649 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2650 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2651 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2652
2653 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2654 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2655 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2656 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2657
2658 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2659 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2660 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2661 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2662
2663 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2664 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2665
2666 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2667 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
2668};
2669
2670static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2671 { "DAC L1", NULL, "Stereo DAC MIXL" },
2672 { "DAC R1", NULL, "Stereo DAC MIXR" },
2673 { "DAC L2", NULL, "Mono DAC MIXL" },
2674 { "DAC R2", NULL, "Mono DAC MIXR" },
2675
2676 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2677 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2678 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2679 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2680
2681 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2682 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2683 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2684 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2685
2686 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2687 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2688 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2689 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2690
2691 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2692 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2693 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2694
2695 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2696 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2697 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2698 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2699 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2700
2701 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2702 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2703 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2704 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2705
2706 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2707 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2708 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2709 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2710
2711 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2712 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2713 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2714 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2715
2716 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2717 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2718 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2719 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2720
2721 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2722 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2723
2724 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2725 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
2726};
2727
2728static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = {
2729 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2730 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2731};
2732
2733static int rt5645_hw_params(struct snd_pcm_substream *substream,
2734 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2735{
2736 struct snd_soc_component *component = dai->component;
2737 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2738 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
2739 int pre_div, bclk_ms, frame_size;
2740
2741 rt5645->lrck[dai->id] = params_rate(params);
2742 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
2743 if (pre_div < 0) {
2744 dev_err(component->dev, "Unsupported clock setting\n");
2745 return -EINVAL;
2746 }
2747 frame_size = snd_soc_params_to_frame_size(params);
2748 if (frame_size < 0) {
2749 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2750 return -EINVAL;
2751 }
2752
2753 switch (rt5645->codec_type) {
2754 case CODEC_TYPE_RT5650:
2755 dl_sft = 4;
2756 break;
2757 default:
2758 dl_sft = 2;
2759 break;
2760 }
2761
2762 bclk_ms = frame_size > 32;
2763 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2764
2765 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2766 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2767 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2768 bclk_ms, pre_div, dai->id);
2769
2770 switch (params_width(params)) {
2771 case 16:
2772 break;
2773 case 20:
2774 val_len = 0x1;
2775 break;
2776 case 24:
2777 val_len = 0x2;
2778 break;
2779 case 8:
2780 val_len = 0x3;
2781 break;
2782 default:
2783 return -EINVAL;
2784 }
2785
2786 switch (dai->id) {
2787 case RT5645_AIF1:
2788 mask_clk = RT5645_I2S_PD1_MASK;
2789 val_clk = pre_div << RT5645_I2S_PD1_SFT;
2790 snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
2791 (0x3 << dl_sft), (val_len << dl_sft));
2792 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
2793 break;
2794 case RT5645_AIF2:
2795 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2796 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2797 pre_div << RT5645_I2S_PD2_SFT;
2798 snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
2799 (0x3 << dl_sft), (val_len << dl_sft));
2800 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
2801 break;
2802 default:
2803 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2804 return -EINVAL;
2805 }
2806
2807 return 0;
2808}
2809
2810static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2811{
2812 struct snd_soc_component *component = dai->component;
2813 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2814 unsigned int reg_val = 0, pol_sft;
2815
2816 switch (rt5645->codec_type) {
2817 case CODEC_TYPE_RT5650:
2818 pol_sft = 8;
2819 break;
2820 default:
2821 pol_sft = 7;
2822 break;
2823 }
2824
2825 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2826 case SND_SOC_DAIFMT_CBM_CFM:
2827 rt5645->master[dai->id] = 1;
2828 break;
2829 case SND_SOC_DAIFMT_CBS_CFS:
2830 reg_val |= RT5645_I2S_MS_S;
2831 rt5645->master[dai->id] = 0;
2832 break;
2833 default:
2834 return -EINVAL;
2835 }
2836
2837 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2838 case SND_SOC_DAIFMT_NB_NF:
2839 break;
2840 case SND_SOC_DAIFMT_IB_NF:
2841 reg_val |= (1 << pol_sft);
2842 break;
2843 default:
2844 return -EINVAL;
2845 }
2846
2847 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2848 case SND_SOC_DAIFMT_I2S:
2849 break;
2850 case SND_SOC_DAIFMT_LEFT_J:
2851 reg_val |= RT5645_I2S_DF_LEFT;
2852 break;
2853 case SND_SOC_DAIFMT_DSP_A:
2854 reg_val |= RT5645_I2S_DF_PCM_A;
2855 break;
2856 case SND_SOC_DAIFMT_DSP_B:
2857 reg_val |= RT5645_I2S_DF_PCM_B;
2858 break;
2859 default:
2860 return -EINVAL;
2861 }
2862 switch (dai->id) {
2863 case RT5645_AIF1:
2864 snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
2865 RT5645_I2S_MS_MASK | (1 << pol_sft) |
2866 RT5645_I2S_DF_MASK, reg_val);
2867 break;
2868 case RT5645_AIF2:
2869 snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
2870 RT5645_I2S_MS_MASK | (1 << pol_sft) |
2871 RT5645_I2S_DF_MASK, reg_val);
2872 break;
2873 default:
2874 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2875 return -EINVAL;
2876 }
2877 return 0;
2878}
2879
2880static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2881 int clk_id, unsigned int freq, int dir)
2882{
2883 struct snd_soc_component *component = dai->component;
2884 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2885 unsigned int reg_val = 0;
2886
2887 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2888 return 0;
2889
2890 switch (clk_id) {
2891 case RT5645_SCLK_S_MCLK:
2892 reg_val |= RT5645_SCLK_SRC_MCLK;
2893 break;
2894 case RT5645_SCLK_S_PLL1:
2895 reg_val |= RT5645_SCLK_SRC_PLL1;
2896 break;
2897 case RT5645_SCLK_S_RCCLK:
2898 reg_val |= RT5645_SCLK_SRC_RCCLK;
2899 break;
2900 default:
2901 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2902 return -EINVAL;
2903 }
2904 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2905 RT5645_SCLK_SRC_MASK, reg_val);
2906 rt5645->sysclk = freq;
2907 rt5645->sysclk_src = clk_id;
2908
2909 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2910
2911 return 0;
2912}
2913
2914static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2915 unsigned int freq_in, unsigned int freq_out)
2916{
2917 struct snd_soc_component *component = dai->component;
2918 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2919 struct rl6231_pll_code pll_code;
2920 int ret;
2921
2922 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2923 freq_out == rt5645->pll_out)
2924 return 0;
2925
2926 if (!freq_in || !freq_out) {
2927 dev_dbg(component->dev, "PLL disabled\n");
2928
2929 rt5645->pll_in = 0;
2930 rt5645->pll_out = 0;
2931 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2932 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2933 return 0;
2934 }
2935
2936 switch (source) {
2937 case RT5645_PLL1_S_MCLK:
2938 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2939 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2940 break;
2941 case RT5645_PLL1_S_BCLK1:
2942 case RT5645_PLL1_S_BCLK2:
2943 switch (dai->id) {
2944 case RT5645_AIF1:
2945 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2946 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2947 break;
2948 case RT5645_AIF2:
2949 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2950 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2951 break;
2952 default:
2953 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2954 return -EINVAL;
2955 }
2956 break;
2957 default:
2958 dev_err(component->dev, "Unknown PLL source %d\n", source);
2959 return -EINVAL;
2960 }
2961
2962 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2963 if (ret < 0) {
2964 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2965 return ret;
2966 }
2967
2968 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2969 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2970 pll_code.n_code, pll_code.k_code);
2971
2972 snd_soc_component_write(component, RT5645_PLL_CTRL1,
2973 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2974 snd_soc_component_write(component, RT5645_PLL_CTRL2,
2975 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2976 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2977
2978 rt5645->pll_in = freq_in;
2979 rt5645->pll_out = freq_out;
2980 rt5645->pll_src = source;
2981
2982 return 0;
2983}
2984
2985static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2986 unsigned int rx_mask, int slots, int slot_width)
2987{
2988 struct snd_soc_component *component = dai->component;
2989 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2990 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2991 unsigned int mask, val = 0;
2992
2993 switch (rt5645->codec_type) {
2994 case CODEC_TYPE_RT5650:
2995 en_sft = 15;
2996 i_slot_sft = 10;
2997 o_slot_sft = 8;
2998 i_width_sht = 6;
2999 o_width_sht = 4;
3000 mask = 0x8ff0;
3001 break;
3002 default:
3003 en_sft = 14;
3004 i_slot_sft = o_slot_sft = 12;
3005 i_width_sht = o_width_sht = 10;
3006 mask = 0x7c00;
3007 break;
3008 }
3009 if (rx_mask || tx_mask) {
3010 val |= (1 << en_sft);
3011 if (rt5645->codec_type == CODEC_TYPE_RT5645)
3012 snd_soc_component_update_bits(component, RT5645_BASS_BACK,
3013 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
3014 }
3015
3016 switch (slots) {
3017 case 4:
3018 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
3019 break;
3020 case 6:
3021 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
3022 break;
3023 case 8:
3024 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
3025 break;
3026 case 2:
3027 default:
3028 break;
3029 }
3030
3031 switch (slot_width) {
3032 case 20:
3033 val |= (1 << i_width_sht) | (1 << o_width_sht);
3034 break;
3035 case 24:
3036 val |= (2 << i_width_sht) | (2 << o_width_sht);
3037 break;
3038 case 32:
3039 val |= (3 << i_width_sht) | (3 << o_width_sht);
3040 break;
3041 case 16:
3042 default:
3043 break;
3044 }
3045
3046 snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val);
3047
3048 return 0;
3049}
3050
3051static int rt5645_set_bias_level(struct snd_soc_component *component,
3052 enum snd_soc_bias_level level)
3053{
3054 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3055
3056 switch (level) {
3057 case SND_SOC_BIAS_PREPARE:
3058 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
3059 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3060 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3061 RT5645_PWR_BG | RT5645_PWR_VREF2,
3062 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3063 RT5645_PWR_BG | RT5645_PWR_VREF2);
3064 mdelay(10);
3065 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3066 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3067 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3068 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
3069 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3070 }
3071 break;
3072
3073 case SND_SOC_BIAS_STANDBY:
3074 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3075 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3076 RT5645_PWR_BG | RT5645_PWR_VREF2,
3077 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3078 RT5645_PWR_BG | RT5645_PWR_VREF2);
3079 mdelay(10);
3080 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3081 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3082 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3083 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
3084 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
3085 msleep(40);
3086 if (rt5645->en_button_func)
3087 queue_delayed_work(system_power_efficient_wq,
3088 &rt5645->jack_detect_work,
3089 msecs_to_jiffies(0));
3090 }
3091 break;
3092
3093 case SND_SOC_BIAS_OFF:
3094 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100);
3095 if (!rt5645->en_button_func)
3096 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
3097 RT5645_DIG_GATE_CTRL, 0);
3098 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3099 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3100 RT5645_PWR_BG | RT5645_PWR_VREF2 |
3101 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
3102 break;
3103
3104 default:
3105 break;
3106 }
3107
3108 return 0;
3109}
3110
3111static void rt5645_enable_push_button_irq(struct snd_soc_component *component,
3112 bool enable)
3113{
3114 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3115
3116 if (enable) {
3117 snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
3118 snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
3119 snd_soc_dapm_sync(dapm);
3120
3121 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3);
3122 snd_soc_component_update_bits(component,
3123 RT5645_INT_IRQ_ST, 0x8, 0x8);
3124 snd_soc_component_update_bits(component,
3125 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
3126 snd_soc_component_read32(component, RT5650_4BTN_IL_CMD1);
3127 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
3128 snd_soc_component_read32(component, RT5650_4BTN_IL_CMD1));
3129 } else {
3130 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
3131 snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0);
3132
3133 snd_soc_dapm_disable_pin(dapm, "ADC L power");
3134 snd_soc_dapm_disable_pin(dapm, "ADC R power");
3135 snd_soc_dapm_sync(dapm);
3136 }
3137}
3138
3139static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert)
3140{
3141 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3142 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3143 unsigned int val;
3144
3145 if (jack_insert) {
3146 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
3147
3148 /* for jack type detect */
3149 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3150 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
3151 snd_soc_dapm_sync(dapm);
3152 if (!dapm->card->instantiated) {
3153 /* Power up necessary bits for JD if dapm is
3154 not ready yet */
3155 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
3156 RT5645_PWR_MB | RT5645_PWR_VREF2,
3157 RT5645_PWR_MB | RT5645_PWR_VREF2);
3158 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
3159 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
3160 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
3161 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
3162 }
3163
3164 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
3165 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3166 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3167 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3168 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
3169 msleep(100);
3170 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3171 RT5645_CBJ_MN_JD, 0);
3172
3173 if (rt5645->gpiod_cbj_sleeve)
3174 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 1);
3175
3176 msleep(600);
3177 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
3178 val &= 0x7;
3179 dev_dbg(component->dev, "val = %d\n", val);
3180
3181 if (val == 1 || val == 2) {
3182 rt5645->jack_type = SND_JACK_HEADSET;
3183 if (rt5645->en_button_func) {
3184 rt5645_enable_push_button_irq(component, true);
3185 }
3186 } else {
3187 if (rt5645->en_button_func)
3188 rt5645_enable_push_button_irq(component, false);
3189 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3190 snd_soc_dapm_sync(dapm);
3191 rt5645->jack_type = SND_JACK_HEADPHONE;
3192 if (rt5645->gpiod_cbj_sleeve)
3193 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
3194 }
3195 if (rt5645->pdata.level_trigger_irq)
3196 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3197 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
3198 } else { /* jack out */
3199 rt5645->jack_type = 0;
3200
3201 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,
3202 RT5645_L_MUTE | RT5645_R_MUTE,
3203 RT5645_L_MUTE | RT5645_R_MUTE);
3204 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3205 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3206 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3207 RT5645_CBJ_BST1_EN, 0);
3208
3209 if (rt5645->en_button_func)
3210 rt5645_enable_push_button_irq(component, false);
3211
3212 if (rt5645->pdata.jd_mode == 0)
3213 snd_soc_dapm_disable_pin(dapm, "LDO2");
3214 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3215 snd_soc_dapm_sync(dapm);
3216 if (rt5645->pdata.level_trigger_irq)
3217 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3218 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
3219
3220 if (rt5645->gpiod_cbj_sleeve)
3221 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
3222 }
3223
3224 return rt5645->jack_type;
3225}
3226
3227static int rt5645_button_detect(struct snd_soc_component *component)
3228{
3229 int btn_type, val;
3230
3231 val = snd_soc_component_read32(component, RT5650_4BTN_IL_CMD1);
3232 pr_debug("val=0x%x\n", val);
3233 btn_type = val & 0xfff0;
3234 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val);
3235
3236 return btn_type;
3237}
3238
3239static irqreturn_t rt5645_irq(int irq, void *data);
3240
3241int rt5645_set_jack_detect(struct snd_soc_component *component,
3242 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
3243 struct snd_soc_jack *btn_jack)
3244{
3245 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3246
3247 rt5645->hp_jack = hp_jack;
3248 rt5645->mic_jack = mic_jack;
3249 rt5645->btn_jack = btn_jack;
3250 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
3251 rt5645->en_button_func = true;
3252 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3253 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3254 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
3255 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3256 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1,
3257 RT5645_HP_CB_MASK, RT5645_HP_CB_PU);
3258 }
3259 rt5645_irq(0, rt5645);
3260
3261 return 0;
3262}
3263EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
3264
3265static void rt5645_jack_detect_work(struct work_struct *work)
3266{
3267 struct rt5645_priv *rt5645 =
3268 container_of(work, struct rt5645_priv, jack_detect_work.work);
3269 int val, btn_type, gpio_state = 0, report = 0;
3270
3271 if (!rt5645->component)
3272 return;
3273
3274 mutex_lock(&rt5645->jd_mutex);
3275
3276 switch (rt5645->pdata.jd_mode) {
3277 case 0: /* Not using rt5645 JD */
3278 if (rt5645->gpiod_hp_det) {
3279 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
3280 dev_dbg(rt5645->component->dev, "gpio_state = %d\n",
3281 gpio_state);
3282 report = rt5645_jack_detect(rt5645->component, gpio_state);
3283 }
3284 snd_soc_jack_report(rt5645->hp_jack,
3285 report, SND_JACK_HEADPHONE);
3286 snd_soc_jack_report(rt5645->mic_jack,
3287 report, SND_JACK_MICROPHONE);
3288 mutex_unlock(&rt5645->jd_mutex);
3289 return;
3290 case 4:
3291 val = snd_soc_component_read32(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020;
3292 break;
3293 default: /* read rt5645 jd1_1 status */
3294 val = snd_soc_component_read32(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000;
3295 break;
3296
3297 }
3298
3299 if (!val && (rt5645->jack_type == 0)) { /* jack in */
3300 report = rt5645_jack_detect(rt5645->component, 1);
3301 } else if (!val && rt5645->jack_type == SND_JACK_HEADSET) {
3302 /* for push button and jack out */
3303 btn_type = 0;
3304 if (snd_soc_component_read32(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) {
3305 /* button pressed */
3306 report = SND_JACK_HEADSET;
3307 btn_type = rt5645_button_detect(rt5645->component);
3308 /* rt5650 can report three kinds of button behavior,
3309 one click, double click and hold. However,
3310 currently we will report button pressed/released
3311 event. So all the three button behaviors are
3312 treated as button pressed. */
3313 switch (btn_type) {
3314 case 0x8000:
3315 case 0x4000:
3316 case 0x2000:
3317 report |= SND_JACK_BTN_0;
3318 break;
3319 case 0x1000:
3320 case 0x0800:
3321 case 0x0400:
3322 report |= SND_JACK_BTN_1;
3323 break;
3324 case 0x0200:
3325 case 0x0100:
3326 case 0x0080:
3327 report |= SND_JACK_BTN_2;
3328 break;
3329 case 0x0040:
3330 case 0x0020:
3331 case 0x0010:
3332 report |= SND_JACK_BTN_3;
3333 break;
3334 case 0x0000: /* unpressed */
3335 break;
3336 default:
3337 dev_err(rt5645->component->dev,
3338 "Unexpected button code 0x%04x\n",
3339 btn_type);
3340 break;
3341 }
3342 }
3343 if (btn_type == 0)/* button release */
3344 report = rt5645->jack_type;
3345 else {
3346 mod_timer(&rt5645->btn_check_timer,
3347 msecs_to_jiffies(100));
3348 }
3349 } else {
3350 /* jack out */
3351 report = 0;
3352 snd_soc_component_update_bits(rt5645->component,
3353 RT5645_INT_IRQ_ST, 0x1, 0x0);
3354 rt5645_jack_detect(rt5645->component, 0);
3355 }
3356
3357 mutex_unlock(&rt5645->jd_mutex);
3358
3359 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3360 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3361 if (rt5645->en_button_func)
3362 snd_soc_jack_report(rt5645->btn_jack,
3363 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3364 SND_JACK_BTN_2 | SND_JACK_BTN_3);
3365}
3366
3367static void rt5645_rcclock_work(struct work_struct *work)
3368{
3369 struct rt5645_priv *rt5645 =
3370 container_of(work, struct rt5645_priv, rcclock_work.work);
3371
3372 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3373 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);
3374}
3375
3376static irqreturn_t rt5645_irq(int irq, void *data)
3377{
3378 struct rt5645_priv *rt5645 = data;
3379
3380 queue_delayed_work(system_power_efficient_wq,
3381 &rt5645->jack_detect_work, msecs_to_jiffies(250));
3382
3383 return IRQ_HANDLED;
3384}
3385
3386static void rt5645_btn_check_callback(struct timer_list *t)
3387{
3388 struct rt5645_priv *rt5645 = from_timer(rt5645, t, btn_check_timer);
3389
3390 queue_delayed_work(system_power_efficient_wq,
3391 &rt5645->jack_detect_work, msecs_to_jiffies(5));
3392}
3393
3394static int rt5645_probe(struct snd_soc_component *component)
3395{
3396 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3397 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3398
3399 rt5645->component = component;
3400
3401 switch (rt5645->codec_type) {
3402 case CODEC_TYPE_RT5645:
3403 snd_soc_dapm_new_controls(dapm,
3404 rt5645_specific_dapm_widgets,
3405 ARRAY_SIZE(rt5645_specific_dapm_widgets));
3406 snd_soc_dapm_add_routes(dapm,
3407 rt5645_specific_dapm_routes,
3408 ARRAY_SIZE(rt5645_specific_dapm_routes));
3409 if (rt5645->v_id < 3) {
3410 snd_soc_dapm_add_routes(dapm,
3411 rt5645_old_dapm_routes,
3412 ARRAY_SIZE(rt5645_old_dapm_routes));
3413 }
3414 break;
3415 case CODEC_TYPE_RT5650:
3416 snd_soc_dapm_new_controls(dapm,
3417 rt5650_specific_dapm_widgets,
3418 ARRAY_SIZE(rt5650_specific_dapm_widgets));
3419 snd_soc_dapm_add_routes(dapm,
3420 rt5650_specific_dapm_routes,
3421 ARRAY_SIZE(rt5650_specific_dapm_routes));
3422 break;
3423 }
3424
3425 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
3426
3427 /* for JD function */
3428 if (rt5645->pdata.jd_mode) {
3429 snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3430 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3431 snd_soc_dapm_sync(dapm);
3432 }
3433
3434 if (rt5645->pdata.long_name)
3435 component->card->long_name = rt5645->pdata.long_name;
3436
3437 rt5645->eq_param = devm_kcalloc(component->dev,
3438 RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s),
3439 GFP_KERNEL);
3440
3441 if (!rt5645->eq_param)
3442 return -ENOMEM;
3443
3444 return 0;
3445}
3446
3447static void rt5645_remove(struct snd_soc_component *component)
3448{
3449 rt5645_reset(component);
3450}
3451
3452#ifdef CONFIG_PM
3453static int rt5645_suspend(struct snd_soc_component *component)
3454{
3455 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3456
3457 regcache_cache_only(rt5645->regmap, true);
3458 regcache_mark_dirty(rt5645->regmap);
3459
3460 return 0;
3461}
3462
3463static int rt5645_resume(struct snd_soc_component *component)
3464{
3465 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3466
3467 regcache_cache_only(rt5645->regmap, false);
3468 regcache_sync(rt5645->regmap);
3469
3470 return 0;
3471}
3472#else
3473#define rt5645_suspend NULL
3474#define rt5645_resume NULL
3475#endif
3476
3477#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3478#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3479 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3480
3481static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {
3482 .hw_params = rt5645_hw_params,
3483 .set_fmt = rt5645_set_dai_fmt,
3484 .set_sysclk = rt5645_set_dai_sysclk,
3485 .set_tdm_slot = rt5645_set_tdm_slot,
3486 .set_pll = rt5645_set_dai_pll,
3487};
3488
3489static struct snd_soc_dai_driver rt5645_dai[] = {
3490 {
3491 .name = "rt5645-aif1",
3492 .id = RT5645_AIF1,
3493 .playback = {
3494 .stream_name = "AIF1 Playback",
3495 .channels_min = 1,
3496 .channels_max = 2,
3497 .rates = RT5645_STEREO_RATES,
3498 .formats = RT5645_FORMATS,
3499 },
3500 .capture = {
3501 .stream_name = "AIF1 Capture",
3502 .channels_min = 1,
3503 .channels_max = 4,
3504 .rates = RT5645_STEREO_RATES,
3505 .formats = RT5645_FORMATS,
3506 },
3507 .ops = &rt5645_aif_dai_ops,
3508 },
3509 {
3510 .name = "rt5645-aif2",
3511 .id = RT5645_AIF2,
3512 .playback = {
3513 .stream_name = "AIF2 Playback",
3514 .channels_min = 1,
3515 .channels_max = 2,
3516 .rates = RT5645_STEREO_RATES,
3517 .formats = RT5645_FORMATS,
3518 },
3519 .capture = {
3520 .stream_name = "AIF2 Capture",
3521 .channels_min = 1,
3522 .channels_max = 2,
3523 .rates = RT5645_STEREO_RATES,
3524 .formats = RT5645_FORMATS,
3525 },
3526 .ops = &rt5645_aif_dai_ops,
3527 },
3528};
3529
3530static const struct snd_soc_component_driver soc_component_dev_rt5645 = {
3531 .probe = rt5645_probe,
3532 .remove = rt5645_remove,
3533 .suspend = rt5645_suspend,
3534 .resume = rt5645_resume,
3535 .set_bias_level = rt5645_set_bias_level,
3536 .controls = rt5645_snd_controls,
3537 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3538 .dapm_widgets = rt5645_dapm_widgets,
3539 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3540 .dapm_routes = rt5645_dapm_routes,
3541 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3542 .use_pmdown_time = 1,
3543 .endianness = 1,
3544 .non_legacy_dai_naming = 1,
3545};
3546
3547static const struct regmap_config rt5645_regmap = {
3548 .reg_bits = 8,
3549 .val_bits = 16,
3550 .use_single_read = true,
3551 .use_single_write = true,
3552 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3553 RT5645_PR_SPACING),
3554 .volatile_reg = rt5645_volatile_register,
3555 .readable_reg = rt5645_readable_register,
3556
3557 .cache_type = REGCACHE_RBTREE,
3558 .reg_defaults = rt5645_reg,
3559 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3560 .ranges = rt5645_ranges,
3561 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3562};
3563
3564static const struct regmap_config rt5650_regmap = {
3565 .reg_bits = 8,
3566 .val_bits = 16,
3567 .use_single_read = true,
3568 .use_single_write = true,
3569 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3570 RT5645_PR_SPACING),
3571 .volatile_reg = rt5645_volatile_register,
3572 .readable_reg = rt5645_readable_register,
3573
3574 .cache_type = REGCACHE_RBTREE,
3575 .reg_defaults = rt5650_reg,
3576 .num_reg_defaults = ARRAY_SIZE(rt5650_reg),
3577 .ranges = rt5645_ranges,
3578 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3579};
3580
3581static const struct regmap_config temp_regmap = {
3582 .name="nocache",
3583 .reg_bits = 8,
3584 .val_bits = 16,
3585 .use_single_read = true,
3586 .use_single_write = true,
3587 .max_register = RT5645_VENDOR_ID2 + 1,
3588 .cache_type = REGCACHE_NONE,
3589};
3590
3591static const struct i2c_device_id rt5645_i2c_id[] = {
3592 { "rt5645", 0 },
3593 { "rt5650", 0 },
3594 { }
3595};
3596MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3597
3598#ifdef CONFIG_OF
3599static const struct of_device_id rt5645_of_match[] = {
3600 { .compatible = "realtek,rt5645", },
3601 { .compatible = "realtek,rt5650", },
3602 { }
3603};
3604MODULE_DEVICE_TABLE(of, rt5645_of_match);
3605#endif
3606
3607#ifdef CONFIG_ACPI
3608static const struct acpi_device_id rt5645_acpi_match[] = {
3609 { "10EC5645", 0 },
3610 { "10EC5648", 0 },
3611 { "10EC5650", 0 },
3612 { "10EC5640", 0 },
3613 { "10EC3270", 0 },
3614 {},
3615};
3616MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3617#endif
3618
3619static const struct rt5645_platform_data intel_braswell_platform_data = {
3620 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3621 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3622 .jd_mode = 3,
3623};
3624
3625static const struct rt5645_platform_data buddy_platform_data = {
3626 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3627 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3628 .jd_mode = 4,
3629 .level_trigger_irq = true,
3630};
3631
3632static const struct rt5645_platform_data gpd_win_platform_data = {
3633 .jd_mode = 3,
3634 .inv_jd1_1 = true,
3635 .long_name = "gpd-win-pocket-rt5645",
3636 /* The GPD pocket has a diff. mic, for the win this does not matter. */
3637 .in2_diff = true,
3638};
3639
3640static const struct rt5645_platform_data asus_t100ha_platform_data = {
3641 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3642 .dmic2_data_pin = RT5645_DMIC2_DISABLE,
3643 .jd_mode = 3,
3644 .inv_jd1_1 = true,
3645};
3646
3647static const struct rt5645_platform_data asus_t101ha_platform_data = {
3648 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3649 .dmic2_data_pin = RT5645_DMIC2_DISABLE,
3650 .jd_mode = 3,
3651};
3652
3653static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = {
3654 .jd_mode = 3,
3655 .in2_diff = true,
3656};
3657
3658static const struct rt5645_platform_data jd_mode3_platform_data = {
3659 .jd_mode = 3,
3660};
3661
3662static const struct rt5645_platform_data lattepanda_board_platform_data = {
3663 .jd_mode = 2,
3664 .inv_jd1_1 = true
3665};
3666
3667static const struct dmi_system_id dmi_platform_data[] = {
3668 {
3669 .ident = "Chrome Buddy",
3670 .matches = {
3671 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
3672 },
3673 .driver_data = (void *)&buddy_platform_data,
3674 },
3675 {
3676 .ident = "Intel Strago",
3677 .matches = {
3678 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3679 },
3680 .driver_data = (void *)&intel_braswell_platform_data,
3681 },
3682 {
3683 .ident = "Google Chrome",
3684 .matches = {
3685 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
3686 },
3687 .driver_data = (void *)&intel_braswell_platform_data,
3688 },
3689 {
3690 .ident = "Google Setzer",
3691 .matches = {
3692 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
3693 },
3694 .driver_data = (void *)&intel_braswell_platform_data,
3695 },
3696 {
3697 .ident = "Microsoft Surface 3",
3698 .matches = {
3699 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
3700 },
3701 .driver_data = (void *)&intel_braswell_platform_data,
3702 },
3703 {
3704 /*
3705 * Match for the GPDwin which unfortunately uses somewhat
3706 * generic dmi strings, which is why we test for 4 strings.
3707 * Comparing against 23 other byt/cht boards, board_vendor
3708 * and board_name are unique to the GPDwin, where as only one
3709 * other board has the same board_serial and 3 others have
3710 * the same default product_name. Also the GPDwin is the
3711 * only device to have both board_ and product_name not set.
3712 */
3713 .ident = "GPD Win / Pocket",
3714 .matches = {
3715 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3716 DMI_MATCH(DMI_BOARD_NAME, "Default string"),
3717 DMI_MATCH(DMI_BOARD_SERIAL, "Default string"),
3718 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
3719 },
3720 .driver_data = (void *)&gpd_win_platform_data,
3721 },
3722 {
3723 .ident = "ASUS T100HAN",
3724 .matches = {
3725 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3726 DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"),
3727 },
3728 .driver_data = (void *)&asus_t100ha_platform_data,
3729 },
3730 {
3731 .ident = "ASUS T101HA",
3732 .matches = {
3733 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3734 DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"),
3735 },
3736 .driver_data = (void *)&asus_t101ha_platform_data,
3737 },
3738 {
3739 .ident = "MINIX Z83-4",
3740 .matches = {
3741 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"),
3742 DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"),
3743 },
3744 .driver_data = (void *)&jd_mode3_platform_data,
3745 },
3746 {
3747 .ident = "Teclast X80 Pro",
3748 .matches = {
3749 DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"),
3750 DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"),
3751 },
3752 .driver_data = (void *)&jd_mode3_platform_data,
3753 },
3754 {
3755 .ident = "Lenovo Ideapad Miix 310",
3756 .matches = {
3757 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
3758 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"),
3759 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"),
3760 },
3761 .driver_data = (void *)&lenovo_ideapad_miix_310_pdata,
3762 },
3763 {
3764 .ident = "Lenovo Ideapad Miix 320",
3765 .matches = {
3766 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
3767 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"),
3768 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
3769 },
3770 .driver_data = (void *)&intel_braswell_platform_data,
3771 },
3772 {
3773 .ident = "LattePanda board",
3774 .matches = {
3775 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3776 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
3777 DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"),
3778 /*
3779 * Above strings are too generic, LattePanda BIOS versions for
3780 * all 4 hw revisions are:
3781 * DF-BI-7-S70CR100-*
3782 * DF-BI-7-S70CR110-*
3783 * DF-BI-7-S70CR200-*
3784 * LP-BS-7-S70CR700-*
3785 * Do a partial match for S70CR to avoid false positive matches.
3786 */
3787 DMI_MATCH(DMI_BIOS_VERSION, "S70CR"),
3788 },
3789 .driver_data = (void *)&lattepanda_board_platform_data,
3790 },
3791 { }
3792};
3793
3794static bool rt5645_check_dp(struct device *dev)
3795{
3796 if (device_property_present(dev, "realtek,in2-differential") ||
3797 device_property_present(dev, "realtek,dmic1-data-pin") ||
3798 device_property_present(dev, "realtek,dmic2-data-pin") ||
3799 device_property_present(dev, "realtek,jd-mode"))
3800 return true;
3801
3802 return false;
3803}
3804
3805static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
3806{
3807 rt5645->pdata.in2_diff = device_property_read_bool(dev,
3808 "realtek,in2-differential");
3809 device_property_read_u32(dev,
3810 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
3811 device_property_read_u32(dev,
3812 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
3813 device_property_read_u32(dev,
3814 "realtek,jd-mode", &rt5645->pdata.jd_mode);
3815
3816 return 0;
3817}
3818
3819static int rt5645_i2c_probe(struct i2c_client *i2c,
3820 const struct i2c_device_id *id)
3821{
3822 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
3823 const struct dmi_system_id *dmi_data;
3824 struct rt5645_priv *rt5645;
3825 int ret, i;
3826 unsigned int val;
3827 struct regmap *regmap;
3828
3829 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3830 GFP_KERNEL);
3831 if (rt5645 == NULL)
3832 return -ENOMEM;
3833
3834 rt5645->i2c = i2c;
3835 i2c_set_clientdata(i2c, rt5645);
3836
3837 dmi_data = dmi_first_match(dmi_platform_data);
3838 if (dmi_data) {
3839 dev_info(&i2c->dev, "Detected %s platform\n", dmi_data->ident);
3840 pdata = dmi_data->driver_data;
3841 }
3842
3843 if (pdata)
3844 rt5645->pdata = *pdata;
3845 else if (rt5645_check_dp(&i2c->dev))
3846 rt5645_parse_dt(rt5645, &i2c->dev);
3847 else
3848 rt5645->pdata = jd_mode3_platform_data;
3849
3850 if (quirk != -1) {
3851 rt5645->pdata.in2_diff = QUIRK_IN2_DIFF(quirk);
3852 rt5645->pdata.level_trigger_irq = QUIRK_LEVEL_IRQ(quirk);
3853 rt5645->pdata.inv_jd1_1 = QUIRK_INV_JD1_1(quirk);
3854 rt5645->pdata.jd_mode = QUIRK_JD_MODE(quirk);
3855 rt5645->pdata.dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk);
3856 rt5645->pdata.dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk);
3857 }
3858
3859 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
3860 GPIOD_IN);
3861
3862 if (IS_ERR(rt5645->gpiod_hp_det)) {
3863 dev_info(&i2c->dev, "failed to initialize gpiod\n");
3864 ret = PTR_ERR(rt5645->gpiod_hp_det);
3865 /*
3866 * Continue if optional gpiod is missing, bail for all other
3867 * errors, including -EPROBE_DEFER
3868 */
3869 if (ret != -ENOENT)
3870 return ret;
3871 }
3872
3873 rt5645->gpiod_cbj_sleeve = devm_gpiod_get_optional(&i2c->dev, "cbj-sleeve",
3874 GPIOD_OUT_LOW);
3875
3876 if (IS_ERR(rt5645->gpiod_cbj_sleeve)) {
3877 ret = PTR_ERR(rt5645->gpiod_cbj_sleeve);
3878 dev_info(&i2c->dev, "failed to initialize gpiod, ret=%d\n", ret);
3879 if (ret != -ENOENT)
3880 return ret;
3881 }
3882
3883 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
3884 rt5645->supplies[i].supply = rt5645_supply_names[i];
3885
3886 ret = devm_regulator_bulk_get(&i2c->dev,
3887 ARRAY_SIZE(rt5645->supplies),
3888 rt5645->supplies);
3889 if (ret) {
3890 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3891 return ret;
3892 }
3893
3894 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
3895 rt5645->supplies);
3896 if (ret) {
3897 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3898 return ret;
3899 }
3900
3901 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3902 if (IS_ERR(regmap)) {
3903 ret = PTR_ERR(regmap);
3904 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3905 ret);
3906 return ret;
3907 }
3908
3909 /*
3910 * Read after 400msec, as it is the interval required between
3911 * read and power On.
3912 */
3913 msleep(TIME_TO_POWER_MS);
3914 regmap_read(regmap, RT5645_VENDOR_ID2, &val);
3915
3916 switch (val) {
3917 case RT5645_DEVICE_ID:
3918 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
3919 rt5645->codec_type = CODEC_TYPE_RT5645;
3920 break;
3921 case RT5650_DEVICE_ID:
3922 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap);
3923 rt5645->codec_type = CODEC_TYPE_RT5650;
3924 break;
3925 default:
3926 dev_err(&i2c->dev,
3927 "Device with ID register %#x is not rt5645 or rt5650\n",
3928 val);
3929 ret = -ENODEV;
3930 goto err_enable;
3931 }
3932
3933 if (IS_ERR(rt5645->regmap)) {
3934 ret = PTR_ERR(rt5645->regmap);
3935 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3936 ret);
3937 return ret;
3938 }
3939
3940 regmap_write(rt5645->regmap, RT5645_RESET, 0);
3941
3942 regmap_read(regmap, RT5645_VENDOR_ID, &val);
3943 rt5645->v_id = val & 0xff;
3944
3945 regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080);
3946
3947 ret = regmap_register_patch(rt5645->regmap, init_list,
3948 ARRAY_SIZE(init_list));
3949 if (ret != 0)
3950 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3951
3952 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3953 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
3954 ARRAY_SIZE(rt5650_init_list));
3955 if (ret != 0)
3956 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3957 ret);
3958 }
3959
3960 regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0);
3961
3962 if (rt5645->pdata.in2_diff)
3963 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3964 RT5645_IN_DF2, RT5645_IN_DF2);
3965
3966 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
3967 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3968 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
3969 }
3970 switch (rt5645->pdata.dmic1_data_pin) {
3971 case RT5645_DMIC_DATA_IN2N:
3972 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3973 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3974 break;
3975
3976 case RT5645_DMIC_DATA_GPIO5:
3977 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3978 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);
3979 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3980 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3981 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3982 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3983 break;
3984
3985 case RT5645_DMIC_DATA_GPIO11:
3986 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3987 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3988 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3989 RT5645_GP11_PIN_MASK,
3990 RT5645_GP11_PIN_DMIC1_SDA);
3991 break;
3992
3993 default:
3994 break;
3995 }
3996
3997 switch (rt5645->pdata.dmic2_data_pin) {
3998 case RT5645_DMIC_DATA_IN2P:
3999 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4000 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
4001 break;
4002
4003 case RT5645_DMIC_DATA_GPIO6:
4004 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4005 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
4006 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4007 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
4008 break;
4009
4010 case RT5645_DMIC_DATA_GPIO10:
4011 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4012 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
4013 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4014 RT5645_GP10_PIN_MASK,
4015 RT5645_GP10_PIN_DMIC2_SDA);
4016 break;
4017
4018 case RT5645_DMIC_DATA_GPIO12:
4019 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4020 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
4021 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4022 RT5645_GP12_PIN_MASK,
4023 RT5645_GP12_PIN_DMIC2_SDA);
4024 break;
4025
4026 default:
4027 break;
4028 }
4029
4030 if (rt5645->pdata.jd_mode) {
4031 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4032 RT5645_IRQ_CLK_GATE_CTRL,
4033 RT5645_IRQ_CLK_GATE_CTRL);
4034 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
4035 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
4036 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4037 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
4038 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4039 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
4040 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
4041 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
4042 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
4043 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
4044 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4045 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
4046 switch (rt5645->pdata.jd_mode) {
4047 case 1:
4048 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4049 RT5645_JD1_MODE_MASK,
4050 RT5645_JD1_MODE_0);
4051 break;
4052 case 2:
4053 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4054 RT5645_JD1_MODE_MASK,
4055 RT5645_JD1_MODE_1);
4056 break;
4057 case 3:
4058 case 4:
4059 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4060 RT5645_JD1_MODE_MASK,
4061 RT5645_JD1_MODE_2);
4062 break;
4063 default:
4064 break;
4065 }
4066 if (rt5645->pdata.inv_jd1_1) {
4067 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4068 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
4069 }
4070 }
4071
4072 regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1,
4073 RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2);
4074
4075 if (rt5645->pdata.level_trigger_irq) {
4076 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4077 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
4078 }
4079 timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0);
4080
4081 mutex_init(&rt5645->jd_mutex);
4082 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
4083 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);
4084
4085 if (rt5645->i2c->irq) {
4086 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
4087 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4088 | IRQF_ONESHOT, "rt5645", rt5645);
4089 if (ret) {
4090 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4091 goto err_enable;
4092 }
4093 }
4094
4095 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645,
4096 rt5645_dai, ARRAY_SIZE(rt5645_dai));
4097 if (ret)
4098 goto err_irq;
4099
4100 return 0;
4101
4102err_irq:
4103 if (rt5645->i2c->irq)
4104 free_irq(rt5645->i2c->irq, rt5645);
4105err_enable:
4106 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4107 return ret;
4108}
4109
4110static int rt5645_i2c_remove(struct i2c_client *i2c)
4111{
4112 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4113
4114 if (i2c->irq)
4115 free_irq(i2c->irq, rt5645);
4116
4117 /*
4118 * Since the rt5645_btn_check_callback() can queue jack_detect_work,
4119 * the timer need to be delted first
4120 */
4121 del_timer_sync(&rt5645->btn_check_timer);
4122
4123 cancel_delayed_work_sync(&rt5645->jack_detect_work);
4124 cancel_delayed_work_sync(&rt5645->rcclock_work);
4125
4126 if (rt5645->gpiod_cbj_sleeve)
4127 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
4128
4129 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4130
4131 return 0;
4132}
4133
4134static void rt5645_i2c_shutdown(struct i2c_client *i2c)
4135{
4136 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4137
4138 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4139 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);
4140 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,
4141 RT5645_CBJ_MN_JD);
4142 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,
4143 0);
4144 msleep(20);
4145 regmap_write(rt5645->regmap, RT5645_RESET, 0);
4146
4147 if (rt5645->gpiod_cbj_sleeve)
4148 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
4149}
4150
4151static struct i2c_driver rt5645_i2c_driver = {
4152 .driver = {
4153 .name = "rt5645",
4154 .of_match_table = of_match_ptr(rt5645_of_match),
4155 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
4156 },
4157 .probe = rt5645_i2c_probe,
4158 .remove = rt5645_i2c_remove,
4159 .shutdown = rt5645_i2c_shutdown,
4160 .id_table = rt5645_i2c_id,
4161};
4162module_i2c_driver(rt5645_i2c_driver);
4163
4164MODULE_DESCRIPTION("ASoC RT5645 driver");
4165MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4166MODULE_LICENSE("GPL v2");