| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | #ifndef WM9081_H |
| 3 | #define WM9081_H |
| 4 | |
| 5 | /* |
| 6 | * wm9081.c -- WM9081 ALSA SoC Audio driver |
| 7 | * |
| 8 | * Author: Mark Brown |
| 9 | * |
| 10 | * Copyright 2009 Wolfson Microelectronics plc |
| 11 | */ |
| 12 | |
| 13 | #include <sound/soc.h> |
| 14 | |
| 15 | /* |
| 16 | * SYSCLK sources |
| 17 | */ |
| 18 | #define WM9081_SYSCLK_MCLK 1 /* Use MCLK without FLL */ |
| 19 | #define WM9081_SYSCLK_FLL_MCLK 2 /* Use MCLK, enabling FLL if required */ |
| 20 | |
| 21 | /* |
| 22 | * Register values. |
| 23 | */ |
| 24 | #define WM9081_SOFTWARE_RESET 0x00 |
| 25 | #define WM9081_ANALOGUE_LINEOUT 0x02 |
| 26 | #define WM9081_ANALOGUE_SPEAKER_PGA 0x03 |
| 27 | #define WM9081_VMID_CONTROL 0x04 |
| 28 | #define WM9081_BIAS_CONTROL_1 0x05 |
| 29 | #define WM9081_ANALOGUE_MIXER 0x07 |
| 30 | #define WM9081_ANTI_POP_CONTROL 0x08 |
| 31 | #define WM9081_ANALOGUE_SPEAKER_1 0x09 |
| 32 | #define WM9081_ANALOGUE_SPEAKER_2 0x0A |
| 33 | #define WM9081_POWER_MANAGEMENT 0x0B |
| 34 | #define WM9081_CLOCK_CONTROL_1 0x0C |
| 35 | #define WM9081_CLOCK_CONTROL_2 0x0D |
| 36 | #define WM9081_CLOCK_CONTROL_3 0x0E |
| 37 | #define WM9081_FLL_CONTROL_1 0x10 |
| 38 | #define WM9081_FLL_CONTROL_2 0x11 |
| 39 | #define WM9081_FLL_CONTROL_3 0x12 |
| 40 | #define WM9081_FLL_CONTROL_4 0x13 |
| 41 | #define WM9081_FLL_CONTROL_5 0x14 |
| 42 | #define WM9081_AUDIO_INTERFACE_1 0x16 |
| 43 | #define WM9081_AUDIO_INTERFACE_2 0x17 |
| 44 | #define WM9081_AUDIO_INTERFACE_3 0x18 |
| 45 | #define WM9081_AUDIO_INTERFACE_4 0x19 |
| 46 | #define WM9081_INTERRUPT_STATUS 0x1A |
| 47 | #define WM9081_INTERRUPT_STATUS_MASK 0x1B |
| 48 | #define WM9081_INTERRUPT_POLARITY 0x1C |
| 49 | #define WM9081_INTERRUPT_CONTROL 0x1D |
| 50 | #define WM9081_DAC_DIGITAL_1 0x1E |
| 51 | #define WM9081_DAC_DIGITAL_2 0x1F |
| 52 | #define WM9081_DRC_1 0x20 |
| 53 | #define WM9081_DRC_2 0x21 |
| 54 | #define WM9081_DRC_3 0x22 |
| 55 | #define WM9081_DRC_4 0x23 |
| 56 | #define WM9081_WRITE_SEQUENCER_1 0x26 |
| 57 | #define WM9081_WRITE_SEQUENCER_2 0x27 |
| 58 | #define WM9081_MW_SLAVE_1 0x28 |
| 59 | #define WM9081_EQ_1 0x2A |
| 60 | #define WM9081_EQ_2 0x2B |
| 61 | #define WM9081_EQ_3 0x2C |
| 62 | #define WM9081_EQ_4 0x2D |
| 63 | #define WM9081_EQ_5 0x2E |
| 64 | #define WM9081_EQ_6 0x2F |
| 65 | #define WM9081_EQ_7 0x30 |
| 66 | #define WM9081_EQ_8 0x31 |
| 67 | #define WM9081_EQ_9 0x32 |
| 68 | #define WM9081_EQ_10 0x33 |
| 69 | #define WM9081_EQ_11 0x34 |
| 70 | #define WM9081_EQ_12 0x35 |
| 71 | #define WM9081_EQ_13 0x36 |
| 72 | #define WM9081_EQ_14 0x37 |
| 73 | #define WM9081_EQ_15 0x38 |
| 74 | #define WM9081_EQ_16 0x39 |
| 75 | #define WM9081_EQ_17 0x3A |
| 76 | #define WM9081_EQ_18 0x3B |
| 77 | #define WM9081_EQ_19 0x3C |
| 78 | #define WM9081_EQ_20 0x3D |
| 79 | |
| 80 | #define WM9081_REGISTER_COUNT 55 |
| 81 | #define WM9081_MAX_REGISTER 0x3D |
| 82 | |
| 83 | /* |
| 84 | * Field Definitions. |
| 85 | */ |
| 86 | |
| 87 | /* |
| 88 | * R0 (0x00) - Software Reset |
| 89 | */ |
| 90 | #define WM9081_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ |
| 91 | #define WM9081_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ |
| 92 | #define WM9081_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ |
| 93 | |
| 94 | /* |
| 95 | * R2 (0x02) - Analogue Lineout |
| 96 | */ |
| 97 | #define WM9081_LINEOUT_MUTE 0x0080 /* LINEOUT_MUTE */ |
| 98 | #define WM9081_LINEOUT_MUTE_MASK 0x0080 /* LINEOUT_MUTE */ |
| 99 | #define WM9081_LINEOUT_MUTE_SHIFT 7 /* LINEOUT_MUTE */ |
| 100 | #define WM9081_LINEOUT_MUTE_WIDTH 1 /* LINEOUT_MUTE */ |
| 101 | #define WM9081_LINEOUTZC 0x0040 /* LINEOUTZC */ |
| 102 | #define WM9081_LINEOUTZC_MASK 0x0040 /* LINEOUTZC */ |
| 103 | #define WM9081_LINEOUTZC_SHIFT 6 /* LINEOUTZC */ |
| 104 | #define WM9081_LINEOUTZC_WIDTH 1 /* LINEOUTZC */ |
| 105 | #define WM9081_LINEOUT_VOL_MASK 0x003F /* LINEOUT_VOL - [5:0] */ |
| 106 | #define WM9081_LINEOUT_VOL_SHIFT 0 /* LINEOUT_VOL - [5:0] */ |
| 107 | #define WM9081_LINEOUT_VOL_WIDTH 6 /* LINEOUT_VOL - [5:0] */ |
| 108 | |
| 109 | /* |
| 110 | * R3 (0x03) - Analogue Speaker PGA |
| 111 | */ |
| 112 | #define WM9081_SPKPGA_MUTE 0x0080 /* SPKPGA_MUTE */ |
| 113 | #define WM9081_SPKPGA_MUTE_MASK 0x0080 /* SPKPGA_MUTE */ |
| 114 | #define WM9081_SPKPGA_MUTE_SHIFT 7 /* SPKPGA_MUTE */ |
| 115 | #define WM9081_SPKPGA_MUTE_WIDTH 1 /* SPKPGA_MUTE */ |
| 116 | #define WM9081_SPKPGAZC 0x0040 /* SPKPGAZC */ |
| 117 | #define WM9081_SPKPGAZC_MASK 0x0040 /* SPKPGAZC */ |
| 118 | #define WM9081_SPKPGAZC_SHIFT 6 /* SPKPGAZC */ |
| 119 | #define WM9081_SPKPGAZC_WIDTH 1 /* SPKPGAZC */ |
| 120 | #define WM9081_SPKPGA_VOL_MASK 0x003F /* SPKPGA_VOL - [5:0] */ |
| 121 | #define WM9081_SPKPGA_VOL_SHIFT 0 /* SPKPGA_VOL - [5:0] */ |
| 122 | #define WM9081_SPKPGA_VOL_WIDTH 6 /* SPKPGA_VOL - [5:0] */ |
| 123 | |
| 124 | /* |
| 125 | * R4 (0x04) - VMID Control |
| 126 | */ |
| 127 | #define WM9081_VMID_BUF_ENA 0x0020 /* VMID_BUF_ENA */ |
| 128 | #define WM9081_VMID_BUF_ENA_MASK 0x0020 /* VMID_BUF_ENA */ |
| 129 | #define WM9081_VMID_BUF_ENA_SHIFT 5 /* VMID_BUF_ENA */ |
| 130 | #define WM9081_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ |
| 131 | #define WM9081_VMID_RAMP 0x0008 /* VMID_RAMP */ |
| 132 | #define WM9081_VMID_RAMP_MASK 0x0008 /* VMID_RAMP */ |
| 133 | #define WM9081_VMID_RAMP_SHIFT 3 /* VMID_RAMP */ |
| 134 | #define WM9081_VMID_RAMP_WIDTH 1 /* VMID_RAMP */ |
| 135 | #define WM9081_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */ |
| 136 | #define WM9081_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */ |
| 137 | #define WM9081_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */ |
| 138 | #define WM9081_VMID_FAST_ST 0x0001 /* VMID_FAST_ST */ |
| 139 | #define WM9081_VMID_FAST_ST_MASK 0x0001 /* VMID_FAST_ST */ |
| 140 | #define WM9081_VMID_FAST_ST_SHIFT 0 /* VMID_FAST_ST */ |
| 141 | #define WM9081_VMID_FAST_ST_WIDTH 1 /* VMID_FAST_ST */ |
| 142 | |
| 143 | /* |
| 144 | * R5 (0x05) - Bias Control 1 |
| 145 | */ |
| 146 | #define WM9081_BIAS_SRC 0x0040 /* BIAS_SRC */ |
| 147 | #define WM9081_BIAS_SRC_MASK 0x0040 /* BIAS_SRC */ |
| 148 | #define WM9081_BIAS_SRC_SHIFT 6 /* BIAS_SRC */ |
| 149 | #define WM9081_BIAS_SRC_WIDTH 1 /* BIAS_SRC */ |
| 150 | #define WM9081_STBY_BIAS_LVL 0x0020 /* STBY_BIAS_LVL */ |
| 151 | #define WM9081_STBY_BIAS_LVL_MASK 0x0020 /* STBY_BIAS_LVL */ |
| 152 | #define WM9081_STBY_BIAS_LVL_SHIFT 5 /* STBY_BIAS_LVL */ |
| 153 | #define WM9081_STBY_BIAS_LVL_WIDTH 1 /* STBY_BIAS_LVL */ |
| 154 | #define WM9081_STBY_BIAS_ENA 0x0010 /* STBY_BIAS_ENA */ |
| 155 | #define WM9081_STBY_BIAS_ENA_MASK 0x0010 /* STBY_BIAS_ENA */ |
| 156 | #define WM9081_STBY_BIAS_ENA_SHIFT 4 /* STBY_BIAS_ENA */ |
| 157 | #define WM9081_STBY_BIAS_ENA_WIDTH 1 /* STBY_BIAS_ENA */ |
| 158 | #define WM9081_BIAS_LVL_MASK 0x000C /* BIAS_LVL - [3:2] */ |
| 159 | #define WM9081_BIAS_LVL_SHIFT 2 /* BIAS_LVL - [3:2] */ |
| 160 | #define WM9081_BIAS_LVL_WIDTH 2 /* BIAS_LVL - [3:2] */ |
| 161 | #define WM9081_BIAS_ENA 0x0002 /* BIAS_ENA */ |
| 162 | #define WM9081_BIAS_ENA_MASK 0x0002 /* BIAS_ENA */ |
| 163 | #define WM9081_BIAS_ENA_SHIFT 1 /* BIAS_ENA */ |
| 164 | #define WM9081_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ |
| 165 | #define WM9081_STARTUP_BIAS_ENA 0x0001 /* STARTUP_BIAS_ENA */ |
| 166 | #define WM9081_STARTUP_BIAS_ENA_MASK 0x0001 /* STARTUP_BIAS_ENA */ |
| 167 | #define WM9081_STARTUP_BIAS_ENA_SHIFT 0 /* STARTUP_BIAS_ENA */ |
| 168 | #define WM9081_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ |
| 169 | |
| 170 | /* |
| 171 | * R7 (0x07) - Analogue Mixer |
| 172 | */ |
| 173 | #define WM9081_DAC_SEL 0x0010 /* DAC_SEL */ |
| 174 | #define WM9081_DAC_SEL_MASK 0x0010 /* DAC_SEL */ |
| 175 | #define WM9081_DAC_SEL_SHIFT 4 /* DAC_SEL */ |
| 176 | #define WM9081_DAC_SEL_WIDTH 1 /* DAC_SEL */ |
| 177 | #define WM9081_IN2_VOL 0x0008 /* IN2_VOL */ |
| 178 | #define WM9081_IN2_VOL_MASK 0x0008 /* IN2_VOL */ |
| 179 | #define WM9081_IN2_VOL_SHIFT 3 /* IN2_VOL */ |
| 180 | #define WM9081_IN2_VOL_WIDTH 1 /* IN2_VOL */ |
| 181 | #define WM9081_IN2_ENA 0x0004 /* IN2_ENA */ |
| 182 | #define WM9081_IN2_ENA_MASK 0x0004 /* IN2_ENA */ |
| 183 | #define WM9081_IN2_ENA_SHIFT 2 /* IN2_ENA */ |
| 184 | #define WM9081_IN2_ENA_WIDTH 1 /* IN2_ENA */ |
| 185 | #define WM9081_IN1_VOL 0x0002 /* IN1_VOL */ |
| 186 | #define WM9081_IN1_VOL_MASK 0x0002 /* IN1_VOL */ |
| 187 | #define WM9081_IN1_VOL_SHIFT 1 /* IN1_VOL */ |
| 188 | #define WM9081_IN1_VOL_WIDTH 1 /* IN1_VOL */ |
| 189 | #define WM9081_IN1_ENA 0x0001 /* IN1_ENA */ |
| 190 | #define WM9081_IN1_ENA_MASK 0x0001 /* IN1_ENA */ |
| 191 | #define WM9081_IN1_ENA_SHIFT 0 /* IN1_ENA */ |
| 192 | #define WM9081_IN1_ENA_WIDTH 1 /* IN1_ENA */ |
| 193 | |
| 194 | /* |
| 195 | * R8 (0x08) - Anti Pop Control |
| 196 | */ |
| 197 | #define WM9081_LINEOUT_DISCH 0x0004 /* LINEOUT_DISCH */ |
| 198 | #define WM9081_LINEOUT_DISCH_MASK 0x0004 /* LINEOUT_DISCH */ |
| 199 | #define WM9081_LINEOUT_DISCH_SHIFT 2 /* LINEOUT_DISCH */ |
| 200 | #define WM9081_LINEOUT_DISCH_WIDTH 1 /* LINEOUT_DISCH */ |
| 201 | #define WM9081_LINEOUT_VROI 0x0002 /* LINEOUT_VROI */ |
| 202 | #define WM9081_LINEOUT_VROI_MASK 0x0002 /* LINEOUT_VROI */ |
| 203 | #define WM9081_LINEOUT_VROI_SHIFT 1 /* LINEOUT_VROI */ |
| 204 | #define WM9081_LINEOUT_VROI_WIDTH 1 /* LINEOUT_VROI */ |
| 205 | #define WM9081_LINEOUT_CLAMP 0x0001 /* LINEOUT_CLAMP */ |
| 206 | #define WM9081_LINEOUT_CLAMP_MASK 0x0001 /* LINEOUT_CLAMP */ |
| 207 | #define WM9081_LINEOUT_CLAMP_SHIFT 0 /* LINEOUT_CLAMP */ |
| 208 | #define WM9081_LINEOUT_CLAMP_WIDTH 1 /* LINEOUT_CLAMP */ |
| 209 | |
| 210 | /* |
| 211 | * R9 (0x09) - Analogue Speaker 1 |
| 212 | */ |
| 213 | #define WM9081_SPK_DCGAIN_MASK 0x0038 /* SPK_DCGAIN - [5:3] */ |
| 214 | #define WM9081_SPK_DCGAIN_SHIFT 3 /* SPK_DCGAIN - [5:3] */ |
| 215 | #define WM9081_SPK_DCGAIN_WIDTH 3 /* SPK_DCGAIN - [5:3] */ |
| 216 | #define WM9081_SPK_ACGAIN_MASK 0x0007 /* SPK_ACGAIN - [2:0] */ |
| 217 | #define WM9081_SPK_ACGAIN_SHIFT 0 /* SPK_ACGAIN - [2:0] */ |
| 218 | #define WM9081_SPK_ACGAIN_WIDTH 3 /* SPK_ACGAIN - [2:0] */ |
| 219 | |
| 220 | /* |
| 221 | * R10 (0x0A) - Analogue Speaker 2 |
| 222 | */ |
| 223 | #define WM9081_SPK_MODE 0x0040 /* SPK_MODE */ |
| 224 | #define WM9081_SPK_MODE_MASK 0x0040 /* SPK_MODE */ |
| 225 | #define WM9081_SPK_MODE_SHIFT 6 /* SPK_MODE */ |
| 226 | #define WM9081_SPK_MODE_WIDTH 1 /* SPK_MODE */ |
| 227 | #define WM9081_SPK_INV_MUTE 0x0010 /* SPK_INV_MUTE */ |
| 228 | #define WM9081_SPK_INV_MUTE_MASK 0x0010 /* SPK_INV_MUTE */ |
| 229 | #define WM9081_SPK_INV_MUTE_SHIFT 4 /* SPK_INV_MUTE */ |
| 230 | #define WM9081_SPK_INV_MUTE_WIDTH 1 /* SPK_INV_MUTE */ |
| 231 | #define WM9081_OUT_SPK_CTRL 0x0008 /* OUT_SPK_CTRL */ |
| 232 | #define WM9081_OUT_SPK_CTRL_MASK 0x0008 /* OUT_SPK_CTRL */ |
| 233 | #define WM9081_OUT_SPK_CTRL_SHIFT 3 /* OUT_SPK_CTRL */ |
| 234 | #define WM9081_OUT_SPK_CTRL_WIDTH 1 /* OUT_SPK_CTRL */ |
| 235 | |
| 236 | /* |
| 237 | * R11 (0x0B) - Power Management |
| 238 | */ |
| 239 | #define WM9081_TSHUT_ENA 0x0100 /* TSHUT_ENA */ |
| 240 | #define WM9081_TSHUT_ENA_MASK 0x0100 /* TSHUT_ENA */ |
| 241 | #define WM9081_TSHUT_ENA_SHIFT 8 /* TSHUT_ENA */ |
| 242 | #define WM9081_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */ |
| 243 | #define WM9081_TSENSE_ENA 0x0080 /* TSENSE_ENA */ |
| 244 | #define WM9081_TSENSE_ENA_MASK 0x0080 /* TSENSE_ENA */ |
| 245 | #define WM9081_TSENSE_ENA_SHIFT 7 /* TSENSE_ENA */ |
| 246 | #define WM9081_TSENSE_ENA_WIDTH 1 /* TSENSE_ENA */ |
| 247 | #define WM9081_TEMP_SHUT 0x0040 /* TEMP_SHUT */ |
| 248 | #define WM9081_TEMP_SHUT_MASK 0x0040 /* TEMP_SHUT */ |
| 249 | #define WM9081_TEMP_SHUT_SHIFT 6 /* TEMP_SHUT */ |
| 250 | #define WM9081_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */ |
| 251 | #define WM9081_LINEOUT_ENA 0x0010 /* LINEOUT_ENA */ |
| 252 | #define WM9081_LINEOUT_ENA_MASK 0x0010 /* LINEOUT_ENA */ |
| 253 | #define WM9081_LINEOUT_ENA_SHIFT 4 /* LINEOUT_ENA */ |
| 254 | #define WM9081_LINEOUT_ENA_WIDTH 1 /* LINEOUT_ENA */ |
| 255 | #define WM9081_SPKPGA_ENA 0x0004 /* SPKPGA_ENA */ |
| 256 | #define WM9081_SPKPGA_ENA_MASK 0x0004 /* SPKPGA_ENA */ |
| 257 | #define WM9081_SPKPGA_ENA_SHIFT 2 /* SPKPGA_ENA */ |
| 258 | #define WM9081_SPKPGA_ENA_WIDTH 1 /* SPKPGA_ENA */ |
| 259 | #define WM9081_SPK_ENA 0x0002 /* SPK_ENA */ |
| 260 | #define WM9081_SPK_ENA_MASK 0x0002 /* SPK_ENA */ |
| 261 | #define WM9081_SPK_ENA_SHIFT 1 /* SPK_ENA */ |
| 262 | #define WM9081_SPK_ENA_WIDTH 1 /* SPK_ENA */ |
| 263 | #define WM9081_DAC_ENA 0x0001 /* DAC_ENA */ |
| 264 | #define WM9081_DAC_ENA_MASK 0x0001 /* DAC_ENA */ |
| 265 | #define WM9081_DAC_ENA_SHIFT 0 /* DAC_ENA */ |
| 266 | #define WM9081_DAC_ENA_WIDTH 1 /* DAC_ENA */ |
| 267 | |
| 268 | /* |
| 269 | * R12 (0x0C) - Clock Control 1 |
| 270 | */ |
| 271 | #define WM9081_CLK_OP_DIV_MASK 0x1C00 /* CLK_OP_DIV - [12:10] */ |
| 272 | #define WM9081_CLK_OP_DIV_SHIFT 10 /* CLK_OP_DIV - [12:10] */ |
| 273 | #define WM9081_CLK_OP_DIV_WIDTH 3 /* CLK_OP_DIV - [12:10] */ |
| 274 | #define WM9081_CLK_TO_DIV_MASK 0x0300 /* CLK_TO_DIV - [9:8] */ |
| 275 | #define WM9081_CLK_TO_DIV_SHIFT 8 /* CLK_TO_DIV - [9:8] */ |
| 276 | #define WM9081_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [9:8] */ |
| 277 | #define WM9081_MCLKDIV2 0x0080 /* MCLKDIV2 */ |
| 278 | #define WM9081_MCLKDIV2_MASK 0x0080 /* MCLKDIV2 */ |
| 279 | #define WM9081_MCLKDIV2_SHIFT 7 /* MCLKDIV2 */ |
| 280 | #define WM9081_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */ |
| 281 | |
| 282 | /* |
| 283 | * R13 (0x0D) - Clock Control 2 |
| 284 | */ |
| 285 | #define WM9081_CLK_SYS_RATE_MASK 0x00F0 /* CLK_SYS_RATE - [7:4] */ |
| 286 | #define WM9081_CLK_SYS_RATE_SHIFT 4 /* CLK_SYS_RATE - [7:4] */ |
| 287 | #define WM9081_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [7:4] */ |
| 288 | #define WM9081_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */ |
| 289 | #define WM9081_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */ |
| 290 | #define WM9081_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */ |
| 291 | |
| 292 | /* |
| 293 | * R14 (0x0E) - Clock Control 3 |
| 294 | */ |
| 295 | #define WM9081_CLK_SRC_SEL 0x2000 /* CLK_SRC_SEL */ |
| 296 | #define WM9081_CLK_SRC_SEL_MASK 0x2000 /* CLK_SRC_SEL */ |
| 297 | #define WM9081_CLK_SRC_SEL_SHIFT 13 /* CLK_SRC_SEL */ |
| 298 | #define WM9081_CLK_SRC_SEL_WIDTH 1 /* CLK_SRC_SEL */ |
| 299 | #define WM9081_CLK_OP_ENA 0x0020 /* CLK_OP_ENA */ |
| 300 | #define WM9081_CLK_OP_ENA_MASK 0x0020 /* CLK_OP_ENA */ |
| 301 | #define WM9081_CLK_OP_ENA_SHIFT 5 /* CLK_OP_ENA */ |
| 302 | #define WM9081_CLK_OP_ENA_WIDTH 1 /* CLK_OP_ENA */ |
| 303 | #define WM9081_CLK_TO_ENA 0x0004 /* CLK_TO_ENA */ |
| 304 | #define WM9081_CLK_TO_ENA_MASK 0x0004 /* CLK_TO_ENA */ |
| 305 | #define WM9081_CLK_TO_ENA_SHIFT 2 /* CLK_TO_ENA */ |
| 306 | #define WM9081_CLK_TO_ENA_WIDTH 1 /* CLK_TO_ENA */ |
| 307 | #define WM9081_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */ |
| 308 | #define WM9081_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */ |
| 309 | #define WM9081_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */ |
| 310 | #define WM9081_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */ |
| 311 | #define WM9081_CLK_SYS_ENA 0x0001 /* CLK_SYS_ENA */ |
| 312 | #define WM9081_CLK_SYS_ENA_MASK 0x0001 /* CLK_SYS_ENA */ |
| 313 | #define WM9081_CLK_SYS_ENA_SHIFT 0 /* CLK_SYS_ENA */ |
| 314 | #define WM9081_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */ |
| 315 | |
| 316 | /* |
| 317 | * R16 (0x10) - FLL Control 1 |
| 318 | */ |
| 319 | #define WM9081_FLL_HOLD 0x0008 /* FLL_HOLD */ |
| 320 | #define WM9081_FLL_HOLD_MASK 0x0008 /* FLL_HOLD */ |
| 321 | #define WM9081_FLL_HOLD_SHIFT 3 /* FLL_HOLD */ |
| 322 | #define WM9081_FLL_HOLD_WIDTH 1 /* FLL_HOLD */ |
| 323 | #define WM9081_FLL_FRAC 0x0004 /* FLL_FRAC */ |
| 324 | #define WM9081_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */ |
| 325 | #define WM9081_FLL_FRAC_SHIFT 2 /* FLL_FRAC */ |
| 326 | #define WM9081_FLL_FRAC_WIDTH 1 /* FLL_FRAC */ |
| 327 | #define WM9081_FLL_ENA 0x0001 /* FLL_ENA */ |
| 328 | #define WM9081_FLL_ENA_MASK 0x0001 /* FLL_ENA */ |
| 329 | #define WM9081_FLL_ENA_SHIFT 0 /* FLL_ENA */ |
| 330 | #define WM9081_FLL_ENA_WIDTH 1 /* FLL_ENA */ |
| 331 | |
| 332 | /* |
| 333 | * R17 (0x11) - FLL Control 2 |
| 334 | */ |
| 335 | #define WM9081_FLL_OUTDIV_MASK 0x0700 /* FLL_OUTDIV - [10:8] */ |
| 336 | #define WM9081_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [10:8] */ |
| 337 | #define WM9081_FLL_OUTDIV_WIDTH 3 /* FLL_OUTDIV - [10:8] */ |
| 338 | #define WM9081_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */ |
| 339 | #define WM9081_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */ |
| 340 | #define WM9081_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */ |
| 341 | #define WM9081_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ |
| 342 | #define WM9081_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ |
| 343 | #define WM9081_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ |
| 344 | |
| 345 | /* |
| 346 | * R18 (0x12) - FLL Control 3 |
| 347 | */ |
| 348 | #define WM9081_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */ |
| 349 | #define WM9081_FLL_K_SHIFT 0 /* FLL_K - [15:0] */ |
| 350 | #define WM9081_FLL_K_WIDTH 16 /* FLL_K - [15:0] */ |
| 351 | |
| 352 | /* |
| 353 | * R19 (0x13) - FLL Control 4 |
| 354 | */ |
| 355 | #define WM9081_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */ |
| 356 | #define WM9081_FLL_N_SHIFT 5 /* FLL_N - [14:5] */ |
| 357 | #define WM9081_FLL_N_WIDTH 10 /* FLL_N - [14:5] */ |
| 358 | #define WM9081_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */ |
| 359 | #define WM9081_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */ |
| 360 | #define WM9081_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */ |
| 361 | |
| 362 | /* |
| 363 | * R20 (0x14) - FLL Control 5 |
| 364 | */ |
| 365 | #define WM9081_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */ |
| 366 | #define WM9081_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */ |
| 367 | #define WM9081_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */ |
| 368 | #define WM9081_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */ |
| 369 | #define WM9081_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */ |
| 370 | #define WM9081_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */ |
| 371 | |
| 372 | /* |
| 373 | * R22 (0x16) - Audio Interface 1 |
| 374 | */ |
| 375 | #define WM9081_AIFDAC_CHAN 0x0040 /* AIFDAC_CHAN */ |
| 376 | #define WM9081_AIFDAC_CHAN_MASK 0x0040 /* AIFDAC_CHAN */ |
| 377 | #define WM9081_AIFDAC_CHAN_SHIFT 6 /* AIFDAC_CHAN */ |
| 378 | #define WM9081_AIFDAC_CHAN_WIDTH 1 /* AIFDAC_CHAN */ |
| 379 | #define WM9081_AIFDAC_TDM_SLOT_MASK 0x0030 /* AIFDAC_TDM_SLOT - [5:4] */ |
| 380 | #define WM9081_AIFDAC_TDM_SLOT_SHIFT 4 /* AIFDAC_TDM_SLOT - [5:4] */ |
| 381 | #define WM9081_AIFDAC_TDM_SLOT_WIDTH 2 /* AIFDAC_TDM_SLOT - [5:4] */ |
| 382 | #define WM9081_AIFDAC_TDM_MODE_MASK 0x000C /* AIFDAC_TDM_MODE - [3:2] */ |
| 383 | #define WM9081_AIFDAC_TDM_MODE_SHIFT 2 /* AIFDAC_TDM_MODE - [3:2] */ |
| 384 | #define WM9081_AIFDAC_TDM_MODE_WIDTH 2 /* AIFDAC_TDM_MODE - [3:2] */ |
| 385 | #define WM9081_DAC_COMP 0x0002 /* DAC_COMP */ |
| 386 | #define WM9081_DAC_COMP_MASK 0x0002 /* DAC_COMP */ |
| 387 | #define WM9081_DAC_COMP_SHIFT 1 /* DAC_COMP */ |
| 388 | #define WM9081_DAC_COMP_WIDTH 1 /* DAC_COMP */ |
| 389 | #define WM9081_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */ |
| 390 | #define WM9081_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */ |
| 391 | #define WM9081_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */ |
| 392 | #define WM9081_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */ |
| 393 | |
| 394 | /* |
| 395 | * R23 (0x17) - Audio Interface 2 |
| 396 | */ |
| 397 | #define WM9081_AIF_TRIS 0x0200 /* AIF_TRIS */ |
| 398 | #define WM9081_AIF_TRIS_MASK 0x0200 /* AIF_TRIS */ |
| 399 | #define WM9081_AIF_TRIS_SHIFT 9 /* AIF_TRIS */ |
| 400 | #define WM9081_AIF_TRIS_WIDTH 1 /* AIF_TRIS */ |
| 401 | #define WM9081_DAC_DAT_INV 0x0100 /* DAC_DAT_INV */ |
| 402 | #define WM9081_DAC_DAT_INV_MASK 0x0100 /* DAC_DAT_INV */ |
| 403 | #define WM9081_DAC_DAT_INV_SHIFT 8 /* DAC_DAT_INV */ |
| 404 | #define WM9081_DAC_DAT_INV_WIDTH 1 /* DAC_DAT_INV */ |
| 405 | #define WM9081_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */ |
| 406 | #define WM9081_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */ |
| 407 | #define WM9081_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */ |
| 408 | #define WM9081_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */ |
| 409 | #define WM9081_BCLK_DIR 0x0040 /* BCLK_DIR */ |
| 410 | #define WM9081_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */ |
| 411 | #define WM9081_BCLK_DIR_SHIFT 6 /* BCLK_DIR */ |
| 412 | #define WM9081_BCLK_DIR_WIDTH 1 /* BCLK_DIR */ |
| 413 | #define WM9081_LRCLK_DIR 0x0020 /* LRCLK_DIR */ |
| 414 | #define WM9081_LRCLK_DIR_MASK 0x0020 /* LRCLK_DIR */ |
| 415 | #define WM9081_LRCLK_DIR_SHIFT 5 /* LRCLK_DIR */ |
| 416 | #define WM9081_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */ |
| 417 | #define WM9081_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */ |
| 418 | #define WM9081_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */ |
| 419 | #define WM9081_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */ |
| 420 | #define WM9081_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */ |
| 421 | #define WM9081_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */ |
| 422 | #define WM9081_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */ |
| 423 | #define WM9081_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */ |
| 424 | #define WM9081_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */ |
| 425 | #define WM9081_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */ |
| 426 | #define WM9081_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */ |
| 427 | |
| 428 | /* |
| 429 | * R24 (0x18) - Audio Interface 3 |
| 430 | */ |
| 431 | #define WM9081_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */ |
| 432 | #define WM9081_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */ |
| 433 | #define WM9081_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */ |
| 434 | |
| 435 | /* |
| 436 | * R25 (0x19) - Audio Interface 4 |
| 437 | */ |
| 438 | #define WM9081_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */ |
| 439 | #define WM9081_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */ |
| 440 | #define WM9081_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */ |
| 441 | |
| 442 | /* |
| 443 | * R26 (0x1A) - Interrupt Status |
| 444 | */ |
| 445 | #define WM9081_WSEQ_BUSY_EINT 0x0004 /* WSEQ_BUSY_EINT */ |
| 446 | #define WM9081_WSEQ_BUSY_EINT_MASK 0x0004 /* WSEQ_BUSY_EINT */ |
| 447 | #define WM9081_WSEQ_BUSY_EINT_SHIFT 2 /* WSEQ_BUSY_EINT */ |
| 448 | #define WM9081_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */ |
| 449 | #define WM9081_TSHUT_EINT 0x0001 /* TSHUT_EINT */ |
| 450 | #define WM9081_TSHUT_EINT_MASK 0x0001 /* TSHUT_EINT */ |
| 451 | #define WM9081_TSHUT_EINT_SHIFT 0 /* TSHUT_EINT */ |
| 452 | #define WM9081_TSHUT_EINT_WIDTH 1 /* TSHUT_EINT */ |
| 453 | |
| 454 | /* |
| 455 | * R27 (0x1B) - Interrupt Status Mask |
| 456 | */ |
| 457 | #define WM9081_IM_WSEQ_BUSY_EINT 0x0004 /* IM_WSEQ_BUSY_EINT */ |
| 458 | #define WM9081_IM_WSEQ_BUSY_EINT_MASK 0x0004 /* IM_WSEQ_BUSY_EINT */ |
| 459 | #define WM9081_IM_WSEQ_BUSY_EINT_SHIFT 2 /* IM_WSEQ_BUSY_EINT */ |
| 460 | #define WM9081_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */ |
| 461 | #define WM9081_IM_TSHUT_EINT 0x0001 /* IM_TSHUT_EINT */ |
| 462 | #define WM9081_IM_TSHUT_EINT_MASK 0x0001 /* IM_TSHUT_EINT */ |
| 463 | #define WM9081_IM_TSHUT_EINT_SHIFT 0 /* IM_TSHUT_EINT */ |
| 464 | #define WM9081_IM_TSHUT_EINT_WIDTH 1 /* IM_TSHUT_EINT */ |
| 465 | |
| 466 | /* |
| 467 | * R28 (0x1C) - Interrupt Polarity |
| 468 | */ |
| 469 | #define WM9081_TSHUT_INV 0x0001 /* TSHUT_INV */ |
| 470 | #define WM9081_TSHUT_INV_MASK 0x0001 /* TSHUT_INV */ |
| 471 | #define WM9081_TSHUT_INV_SHIFT 0 /* TSHUT_INV */ |
| 472 | #define WM9081_TSHUT_INV_WIDTH 1 /* TSHUT_INV */ |
| 473 | |
| 474 | /* |
| 475 | * R29 (0x1D) - Interrupt Control |
| 476 | */ |
| 477 | #define WM9081_IRQ_POL 0x8000 /* IRQ_POL */ |
| 478 | #define WM9081_IRQ_POL_MASK 0x8000 /* IRQ_POL */ |
| 479 | #define WM9081_IRQ_POL_SHIFT 15 /* IRQ_POL */ |
| 480 | #define WM9081_IRQ_POL_WIDTH 1 /* IRQ_POL */ |
| 481 | #define WM9081_IRQ_OP_CTRL 0x0001 /* IRQ_OP_CTRL */ |
| 482 | #define WM9081_IRQ_OP_CTRL_MASK 0x0001 /* IRQ_OP_CTRL */ |
| 483 | #define WM9081_IRQ_OP_CTRL_SHIFT 0 /* IRQ_OP_CTRL */ |
| 484 | #define WM9081_IRQ_OP_CTRL_WIDTH 1 /* IRQ_OP_CTRL */ |
| 485 | |
| 486 | /* |
| 487 | * R30 (0x1E) - DAC Digital 1 |
| 488 | */ |
| 489 | #define WM9081_DAC_VOL_MASK 0x00FF /* DAC_VOL - [7:0] */ |
| 490 | #define WM9081_DAC_VOL_SHIFT 0 /* DAC_VOL - [7:0] */ |
| 491 | #define WM9081_DAC_VOL_WIDTH 8 /* DAC_VOL - [7:0] */ |
| 492 | |
| 493 | /* |
| 494 | * R31 (0x1F) - DAC Digital 2 |
| 495 | */ |
| 496 | #define WM9081_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */ |
| 497 | #define WM9081_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */ |
| 498 | #define WM9081_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */ |
| 499 | #define WM9081_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ |
| 500 | #define WM9081_DAC_MUTEMODE 0x0200 /* DAC_MUTEMODE */ |
| 501 | #define WM9081_DAC_MUTEMODE_MASK 0x0200 /* DAC_MUTEMODE */ |
| 502 | #define WM9081_DAC_MUTEMODE_SHIFT 9 /* DAC_MUTEMODE */ |
| 503 | #define WM9081_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */ |
| 504 | #define WM9081_DAC_MUTE 0x0008 /* DAC_MUTE */ |
| 505 | #define WM9081_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */ |
| 506 | #define WM9081_DAC_MUTE_SHIFT 3 /* DAC_MUTE */ |
| 507 | #define WM9081_DAC_MUTE_WIDTH 1 /* DAC_MUTE */ |
| 508 | #define WM9081_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ |
| 509 | #define WM9081_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ |
| 510 | #define WM9081_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ |
| 511 | |
| 512 | /* |
| 513 | * R32 (0x20) - DRC 1 |
| 514 | */ |
| 515 | #define WM9081_DRC_ENA 0x8000 /* DRC_ENA */ |
| 516 | #define WM9081_DRC_ENA_MASK 0x8000 /* DRC_ENA */ |
| 517 | #define WM9081_DRC_ENA_SHIFT 15 /* DRC_ENA */ |
| 518 | #define WM9081_DRC_ENA_WIDTH 1 /* DRC_ENA */ |
| 519 | #define WM9081_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */ |
| 520 | #define WM9081_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */ |
| 521 | #define WM9081_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */ |
| 522 | #define WM9081_DRC_FF_DLY 0x0020 /* DRC_FF_DLY */ |
| 523 | #define WM9081_DRC_FF_DLY_MASK 0x0020 /* DRC_FF_DLY */ |
| 524 | #define WM9081_DRC_FF_DLY_SHIFT 5 /* DRC_FF_DLY */ |
| 525 | #define WM9081_DRC_FF_DLY_WIDTH 1 /* DRC_FF_DLY */ |
| 526 | #define WM9081_DRC_QR 0x0004 /* DRC_QR */ |
| 527 | #define WM9081_DRC_QR_MASK 0x0004 /* DRC_QR */ |
| 528 | #define WM9081_DRC_QR_SHIFT 2 /* DRC_QR */ |
| 529 | #define WM9081_DRC_QR_WIDTH 1 /* DRC_QR */ |
| 530 | #define WM9081_DRC_ANTICLIP 0x0002 /* DRC_ANTICLIP */ |
| 531 | #define WM9081_DRC_ANTICLIP_MASK 0x0002 /* DRC_ANTICLIP */ |
| 532 | #define WM9081_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */ |
| 533 | #define WM9081_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */ |
| 534 | |
| 535 | /* |
| 536 | * R33 (0x21) - DRC 2 |
| 537 | */ |
| 538 | #define WM9081_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */ |
| 539 | #define WM9081_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */ |
| 540 | #define WM9081_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */ |
| 541 | #define WM9081_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */ |
| 542 | #define WM9081_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */ |
| 543 | #define WM9081_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */ |
| 544 | #define WM9081_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */ |
| 545 | #define WM9081_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */ |
| 546 | #define WM9081_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */ |
| 547 | #define WM9081_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */ |
| 548 | #define WM9081_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */ |
| 549 | #define WM9081_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */ |
| 550 | #define WM9081_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */ |
| 551 | #define WM9081_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */ |
| 552 | #define WM9081_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */ |
| 553 | #define WM9081_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ |
| 554 | #define WM9081_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ |
| 555 | #define WM9081_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ |
| 556 | |
| 557 | /* |
| 558 | * R34 (0x22) - DRC 3 |
| 559 | */ |
| 560 | #define WM9081_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */ |
| 561 | #define WM9081_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */ |
| 562 | #define WM9081_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */ |
| 563 | #define WM9081_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */ |
| 564 | #define WM9081_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */ |
| 565 | #define WM9081_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */ |
| 566 | |
| 567 | /* |
| 568 | * R35 (0x23) - DRC 4 |
| 569 | */ |
| 570 | #define WM9081_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */ |
| 571 | #define WM9081_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */ |
| 572 | #define WM9081_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */ |
| 573 | #define WM9081_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */ |
| 574 | #define WM9081_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */ |
| 575 | #define WM9081_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */ |
| 576 | |
| 577 | /* |
| 578 | * R38 (0x26) - Write Sequencer 1 |
| 579 | */ |
| 580 | #define WM9081_WSEQ_ENA 0x8000 /* WSEQ_ENA */ |
| 581 | #define WM9081_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ |
| 582 | #define WM9081_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ |
| 583 | #define WM9081_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ |
| 584 | #define WM9081_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ |
| 585 | #define WM9081_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ |
| 586 | #define WM9081_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ |
| 587 | #define WM9081_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ |
| 588 | #define WM9081_WSEQ_START 0x0100 /* WSEQ_START */ |
| 589 | #define WM9081_WSEQ_START_MASK 0x0100 /* WSEQ_START */ |
| 590 | #define WM9081_WSEQ_START_SHIFT 8 /* WSEQ_START */ |
| 591 | #define WM9081_WSEQ_START_WIDTH 1 /* WSEQ_START */ |
| 592 | #define WM9081_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ |
| 593 | #define WM9081_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ |
| 594 | #define WM9081_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ |
| 595 | |
| 596 | /* |
| 597 | * R39 (0x27) - Write Sequencer 2 |
| 598 | */ |
| 599 | #define WM9081_WSEQ_CURRENT_INDEX_MASK 0x07F0 /* WSEQ_CURRENT_INDEX - [10:4] */ |
| 600 | #define WM9081_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [10:4] */ |
| 601 | #define WM9081_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [10:4] */ |
| 602 | #define WM9081_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ |
| 603 | #define WM9081_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ |
| 604 | #define WM9081_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ |
| 605 | #define WM9081_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ |
| 606 | |
| 607 | /* |
| 608 | * R40 (0x28) - MW Slave 1 |
| 609 | */ |
| 610 | #define WM9081_SPI_CFG 0x0020 /* SPI_CFG */ |
| 611 | #define WM9081_SPI_CFG_MASK 0x0020 /* SPI_CFG */ |
| 612 | #define WM9081_SPI_CFG_SHIFT 5 /* SPI_CFG */ |
| 613 | #define WM9081_SPI_CFG_WIDTH 1 /* SPI_CFG */ |
| 614 | #define WM9081_SPI_4WIRE 0x0010 /* SPI_4WIRE */ |
| 615 | #define WM9081_SPI_4WIRE_MASK 0x0010 /* SPI_4WIRE */ |
| 616 | #define WM9081_SPI_4WIRE_SHIFT 4 /* SPI_4WIRE */ |
| 617 | #define WM9081_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ |
| 618 | #define WM9081_ARA_ENA 0x0008 /* ARA_ENA */ |
| 619 | #define WM9081_ARA_ENA_MASK 0x0008 /* ARA_ENA */ |
| 620 | #define WM9081_ARA_ENA_SHIFT 3 /* ARA_ENA */ |
| 621 | #define WM9081_ARA_ENA_WIDTH 1 /* ARA_ENA */ |
| 622 | #define WM9081_AUTO_INC 0x0002 /* AUTO_INC */ |
| 623 | #define WM9081_AUTO_INC_MASK 0x0002 /* AUTO_INC */ |
| 624 | #define WM9081_AUTO_INC_SHIFT 1 /* AUTO_INC */ |
| 625 | #define WM9081_AUTO_INC_WIDTH 1 /* AUTO_INC */ |
| 626 | |
| 627 | /* |
| 628 | * R42 (0x2A) - EQ 1 |
| 629 | */ |
| 630 | #define WM9081_EQ_B1_GAIN_MASK 0xF800 /* EQ_B1_GAIN - [15:11] */ |
| 631 | #define WM9081_EQ_B1_GAIN_SHIFT 11 /* EQ_B1_GAIN - [15:11] */ |
| 632 | #define WM9081_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [15:11] */ |
| 633 | #define WM9081_EQ_B2_GAIN_MASK 0x07C0 /* EQ_B2_GAIN - [10:6] */ |
| 634 | #define WM9081_EQ_B2_GAIN_SHIFT 6 /* EQ_B2_GAIN - [10:6] */ |
| 635 | #define WM9081_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [10:6] */ |
| 636 | #define WM9081_EQ_B4_GAIN_MASK 0x003E /* EQ_B4_GAIN - [5:1] */ |
| 637 | #define WM9081_EQ_B4_GAIN_SHIFT 1 /* EQ_B4_GAIN - [5:1] */ |
| 638 | #define WM9081_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [5:1] */ |
| 639 | #define WM9081_EQ_ENA 0x0001 /* EQ_ENA */ |
| 640 | #define WM9081_EQ_ENA_MASK 0x0001 /* EQ_ENA */ |
| 641 | #define WM9081_EQ_ENA_SHIFT 0 /* EQ_ENA */ |
| 642 | #define WM9081_EQ_ENA_WIDTH 1 /* EQ_ENA */ |
| 643 | |
| 644 | /* |
| 645 | * R43 (0x2B) - EQ 2 |
| 646 | */ |
| 647 | #define WM9081_EQ_B3_GAIN_MASK 0xF800 /* EQ_B3_GAIN - [15:11] */ |
| 648 | #define WM9081_EQ_B3_GAIN_SHIFT 11 /* EQ_B3_GAIN - [15:11] */ |
| 649 | #define WM9081_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [15:11] */ |
| 650 | #define WM9081_EQ_B5_GAIN_MASK 0x07C0 /* EQ_B5_GAIN - [10:6] */ |
| 651 | #define WM9081_EQ_B5_GAIN_SHIFT 6 /* EQ_B5_GAIN - [10:6] */ |
| 652 | #define WM9081_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [10:6] */ |
| 653 | |
| 654 | /* |
| 655 | * R44 (0x2C) - EQ 3 |
| 656 | */ |
| 657 | #define WM9081_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */ |
| 658 | #define WM9081_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */ |
| 659 | #define WM9081_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */ |
| 660 | |
| 661 | /* |
| 662 | * R45 (0x2D) - EQ 4 |
| 663 | */ |
| 664 | #define WM9081_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */ |
| 665 | #define WM9081_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */ |
| 666 | #define WM9081_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */ |
| 667 | |
| 668 | /* |
| 669 | * R46 (0x2E) - EQ 5 |
| 670 | */ |
| 671 | #define WM9081_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */ |
| 672 | #define WM9081_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */ |
| 673 | #define WM9081_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */ |
| 674 | |
| 675 | /* |
| 676 | * R47 (0x2F) - EQ 6 |
| 677 | */ |
| 678 | #define WM9081_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */ |
| 679 | #define WM9081_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */ |
| 680 | #define WM9081_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */ |
| 681 | |
| 682 | /* |
| 683 | * R48 (0x30) - EQ 7 |
| 684 | */ |
| 685 | #define WM9081_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */ |
| 686 | #define WM9081_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */ |
| 687 | #define WM9081_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */ |
| 688 | |
| 689 | /* |
| 690 | * R49 (0x31) - EQ 8 |
| 691 | */ |
| 692 | #define WM9081_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */ |
| 693 | #define WM9081_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */ |
| 694 | #define WM9081_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */ |
| 695 | |
| 696 | /* |
| 697 | * R50 (0x32) - EQ 9 |
| 698 | */ |
| 699 | #define WM9081_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */ |
| 700 | #define WM9081_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */ |
| 701 | #define WM9081_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */ |
| 702 | |
| 703 | /* |
| 704 | * R51 (0x33) - EQ 10 |
| 705 | */ |
| 706 | #define WM9081_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */ |
| 707 | #define WM9081_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */ |
| 708 | #define WM9081_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */ |
| 709 | |
| 710 | /* |
| 711 | * R52 (0x34) - EQ 11 |
| 712 | */ |
| 713 | #define WM9081_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */ |
| 714 | #define WM9081_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */ |
| 715 | #define WM9081_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */ |
| 716 | |
| 717 | /* |
| 718 | * R53 (0x35) - EQ 12 |
| 719 | */ |
| 720 | #define WM9081_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */ |
| 721 | #define WM9081_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */ |
| 722 | #define WM9081_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */ |
| 723 | |
| 724 | /* |
| 725 | * R54 (0x36) - EQ 13 |
| 726 | */ |
| 727 | #define WM9081_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */ |
| 728 | #define WM9081_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */ |
| 729 | #define WM9081_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */ |
| 730 | |
| 731 | /* |
| 732 | * R55 (0x37) - EQ 14 |
| 733 | */ |
| 734 | #define WM9081_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */ |
| 735 | #define WM9081_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */ |
| 736 | #define WM9081_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */ |
| 737 | |
| 738 | /* |
| 739 | * R56 (0x38) - EQ 15 |
| 740 | */ |
| 741 | #define WM9081_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */ |
| 742 | #define WM9081_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */ |
| 743 | #define WM9081_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */ |
| 744 | |
| 745 | /* |
| 746 | * R57 (0x39) - EQ 16 |
| 747 | */ |
| 748 | #define WM9081_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */ |
| 749 | #define WM9081_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */ |
| 750 | #define WM9081_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */ |
| 751 | |
| 752 | /* |
| 753 | * R58 (0x3A) - EQ 17 |
| 754 | */ |
| 755 | #define WM9081_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */ |
| 756 | #define WM9081_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */ |
| 757 | #define WM9081_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */ |
| 758 | |
| 759 | /* |
| 760 | * R59 (0x3B) - EQ 18 |
| 761 | */ |
| 762 | #define WM9081_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */ |
| 763 | #define WM9081_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */ |
| 764 | #define WM9081_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */ |
| 765 | |
| 766 | /* |
| 767 | * R60 (0x3C) - EQ 19 |
| 768 | */ |
| 769 | #define WM9081_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */ |
| 770 | #define WM9081_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */ |
| 771 | #define WM9081_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */ |
| 772 | |
| 773 | /* |
| 774 | * R61 (0x3D) - EQ 20 |
| 775 | */ |
| 776 | #define WM9081_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */ |
| 777 | #define WM9081_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */ |
| 778 | #define WM9081_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */ |
| 779 | |
| 780 | |
| 781 | #endif |