| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copied from the kernel sources: |
| 4 | * |
| 5 | * Copyright IBM Corp. 1999, 2009 |
| 6 | * |
| 7 | * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> |
| 8 | */ |
| 9 | |
| 10 | #ifndef __TOOLS_LINUX_ASM_BARRIER_H |
| 11 | #define __TOOLS_LINUX_ASM_BARRIER_H |
| 12 | |
| 13 | /* |
| 14 | * Force strict CPU ordering. |
| 15 | * And yes, this is required on UP too when we're talking |
| 16 | * to devices. |
| 17 | */ |
| 18 | |
| 19 | #ifdef CONFIG_HAVE_MARCH_Z196_FEATURES |
| 20 | /* Fast-BCR without checkpoint synchronization */ |
| 21 | #define __ASM_BARRIER "bcr 14,0\n" |
| 22 | #else |
| 23 | #define __ASM_BARRIER "bcr 15,0\n" |
| 24 | #endif |
| 25 | |
| 26 | #define mb() do { asm volatile(__ASM_BARRIER : : : "memory"); } while (0) |
| 27 | |
| 28 | #define rmb() mb() |
| 29 | #define wmb() mb() |
| 30 | |
| 31 | #define smp_store_release(p, v) \ |
| 32 | do { \ |
| 33 | barrier(); \ |
| 34 | WRITE_ONCE(*p, v); \ |
| 35 | } while (0) |
| 36 | |
| 37 | #define smp_load_acquire(p) \ |
| 38 | ({ \ |
| 39 | typeof(*p) ___p1 = READ_ONCE(*p); \ |
| 40 | barrier(); \ |
| 41 | ___p1; \ |
| 42 | }) |
| 43 | |
| 44 | #endif /* __TOOLS_LIB_ASM_BARRIER_H */ |