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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / tools / power / x86 / intel-speed-select / isst.h
blob: d280b27d600d538658445158e8fb0132a96c3c56 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Intel Speed Select -- Enumerate and control features
4 * Copyright (c) 2019 Intel Corporation.
5 */
6
7#ifndef _ISST_H_
8#define _ISST_H_
9
10#include <stdio.h>
11#include <unistd.h>
12#include <sys/types.h>
13#include <sched.h>
14#include <sys/stat.h>
15#include <sys/resource.h>
16#include <getopt.h>
17#include <err.h>
18#include <fcntl.h>
19#include <signal.h>
20#include <sys/time.h>
21#include <limits.h>
22#include <stdlib.h>
23#include <string.h>
24#include <cpuid.h>
25#include <dirent.h>
26#include <errno.h>
27
28#include <stdarg.h>
29#include <sys/ioctl.h>
30
31#define BIT(x) (1 << (x))
32#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (sizeof(long) * 8 - 1 - (h))))
33#define GENMASK_ULL(h, l) \
34 (((~0ULL) << (l)) & (~0ULL >> (sizeof(long long) * 8 - 1 - (h))))
35
36#define CONFIG_TDP 0x7f
37#define CONFIG_TDP_GET_LEVELS_INFO 0x00
38#define CONFIG_TDP_GET_TDP_CONTROL 0x01
39#define CONFIG_TDP_SET_TDP_CONTROL 0x02
40#define CONFIG_TDP_GET_TDP_INFO 0x03
41#define CONFIG_TDP_GET_PWR_INFO 0x04
42#define CONFIG_TDP_GET_TJMAX_INFO 0x05
43#define CONFIG_TDP_GET_CORE_MASK 0x06
44#define CONFIG_TDP_GET_TURBO_LIMIT_RATIOS 0x07
45#define CONFIG_TDP_SET_LEVEL 0x08
46#define CONFIG_TDP_GET_UNCORE_P0_P1_INFO 0X09
47#define CONFIG_TDP_GET_P1_INFO 0x0a
48#define CONFIG_TDP_GET_MEM_FREQ 0x0b
49
50#define CONFIG_TDP_GET_FACT_HP_TURBO_LIMIT_NUMCORES 0x10
51#define CONFIG_TDP_GET_FACT_HP_TURBO_LIMIT_RATIOS 0x11
52#define CONFIG_TDP_GET_FACT_LP_CLIPPING_RATIO 0x12
53
54#define CONFIG_TDP_PBF_GET_CORE_MASK_INFO 0x20
55#define CONFIG_TDP_PBF_GET_P1HI_P1LO_INFO 0x21
56#define CONFIG_TDP_PBF_GET_TJ_MAX_INFO 0x22
57#define CONFIG_TDP_PBF_GET_TDP_INFO 0X23
58
59#define CONFIG_CLOS 0xd0
60#define CLOS_PQR_ASSOC 0x00
61#define CLOS_PM_CLOS 0x01
62#define CLOS_PM_QOS_CONFIG 0x02
63#define CLOS_STATUS 0x03
64
65#define MBOX_CMD_WRITE_BIT 0x08
66
67#define PM_QOS_INFO_OFFSET 0x00
68#define PM_QOS_CONFIG_OFFSET 0x04
69#define PM_CLOS_OFFSET 0x08
70#define PQR_ASSOC_OFFSET 0x20
71
72struct isst_clos_config {
73 int pkg_id;
74 int die_id;
75 unsigned char epp;
76 unsigned char clos_prop_prio;
77 unsigned char clos_min;
78 unsigned char clos_max;
79 unsigned char clos_desired;
80};
81
82struct isst_fact_bucket_info {
83 int high_priority_cores_count;
84 int sse_trl;
85 int avx_trl;
86 int avx512_trl;
87};
88
89struct isst_pbf_info {
90 int pbf_acticated;
91 int pbf_available;
92 size_t core_cpumask_size;
93 cpu_set_t *core_cpumask;
94 int p1_high;
95 int p1_low;
96 int t_control;
97 int t_prochot;
98 int tdp;
99};
100
101#define ISST_TRL_MAX_ACTIVE_CORES 8
102#define ISST_FACT_MAX_BUCKETS 8
103struct isst_fact_info {
104 int lp_clipping_ratio_license_sse;
105 int lp_clipping_ratio_license_avx2;
106 int lp_clipping_ratio_license_avx512;
107 struct isst_fact_bucket_info bucket_info[ISST_FACT_MAX_BUCKETS];
108};
109
110struct isst_pkg_ctdp_level_info {
111 int processed;
112 int control_cpu;
113 int pkg_id;
114 int die_id;
115 int level;
116 int fact_support;
117 int pbf_support;
118 int fact_enabled;
119 int pbf_enabled;
120 int tdp_ratio;
121 int active;
122 int tdp_control;
123 int pkg_tdp;
124 int pkg_min_power;
125 int pkg_max_power;
126 int fact;
127 int t_proc_hot;
128 int uncore_p0;
129 int uncore_p1;
130 int sse_p1;
131 int avx2_p1;
132 int avx512_p1;
133 int mem_freq;
134 size_t core_cpumask_size;
135 cpu_set_t *core_cpumask;
136 int cpu_count;
137 unsigned long long buckets_info;
138 int trl_sse_active_cores[ISST_TRL_MAX_ACTIVE_CORES];
139 int trl_avx_active_cores[ISST_TRL_MAX_ACTIVE_CORES];
140 int trl_avx_512_active_cores[ISST_TRL_MAX_ACTIVE_CORES];
141 int kobj_bucket_index;
142 int active_bucket;
143 int fact_max_index;
144 int fact_max_config;
145 int pbf_found;
146 int pbf_active;
147 struct isst_pbf_info pbf_info;
148 struct isst_fact_info fact_info;
149};
150
151#define ISST_MAX_TDP_LEVELS (4 + 1) /* +1 for base config */
152struct isst_pkg_ctdp {
153 int locked;
154 int version;
155 int processed;
156 int levels;
157 int current_level;
158 int enabled;
159 struct isst_pkg_ctdp_level_info ctdp_level[ISST_MAX_TDP_LEVELS];
160};
161
162extern int get_topo_max_cpus(void);
163extern int get_cpu_count(int pkg_id, int die_id);
164
165/* Common interfaces */
166extern void debug_printf(const char *format, ...);
167extern int out_format_is_json(void);
168extern int get_physical_package_id(int cpu);
169extern int get_physical_die_id(int cpu);
170extern size_t alloc_cpu_set(cpu_set_t **cpu_set);
171extern void free_cpu_set(cpu_set_t *cpu_set);
172extern int find_logical_cpu(int pkg_id, int die_id, int phy_cpu);
173extern int find_phy_cpu_num(int logical_cpu);
174extern int find_phy_core_num(int logical_cpu);
175extern void set_cpu_mask_from_punit_coremask(int cpu,
176 unsigned long long core_mask,
177 size_t core_cpumask_size,
178 cpu_set_t *core_cpumask,
179 int *cpu_cnt);
180
181extern int isst_send_mbox_command(unsigned int cpu, unsigned char command,
182 unsigned char sub_command,
183 unsigned int write,
184 unsigned int req_data, unsigned int *resp);
185
186extern int isst_send_msr_command(unsigned int cpu, unsigned int command,
187 int write, unsigned long long *req_resp);
188
189extern int isst_get_ctdp_levels(int cpu, struct isst_pkg_ctdp *pkg_dev);
190extern int isst_get_coremask_info(int cpu, int config_index,
191 struct isst_pkg_ctdp_level_info *ctdp_level);
192extern int isst_get_process_ctdp(int cpu, int tdp_level,
193 struct isst_pkg_ctdp *pkg_dev);
194extern void isst_get_process_ctdp_complete(int cpu,
195 struct isst_pkg_ctdp *pkg_dev);
196extern void isst_ctdp_display_information(int cpu, FILE *outf, int tdp_level,
197 struct isst_pkg_ctdp *pkg_dev);
198extern void isst_ctdp_display_core_info(int cpu, FILE *outf, char *prefix,
199 unsigned int val);
200extern void isst_ctdp_display_information_start(FILE *outf);
201extern void isst_ctdp_display_information_end(FILE *outf);
202extern void isst_pbf_display_information(int cpu, FILE *outf, int level,
203 struct isst_pbf_info *info);
204extern int isst_set_tdp_level(int cpu, int tdp_level);
205extern int isst_set_tdp_level_msr(int cpu, int tdp_level);
206extern int isst_set_pbf_fact_status(int cpu, int pbf, int enable);
207extern int isst_get_pbf_info(int cpu, int level,
208 struct isst_pbf_info *pbf_info);
209extern void isst_get_pbf_info_complete(struct isst_pbf_info *pbf_info);
210extern int isst_get_fact_info(int cpu, int level,
211 struct isst_fact_info *fact_info);
212extern int isst_get_fact_bucket_info(int cpu, int level,
213 struct isst_fact_bucket_info *bucket_info);
214extern void isst_fact_display_information(int cpu, FILE *outf, int level,
215 int fact_bucket, int fact_avx,
216 struct isst_fact_info *fact_info);
217extern int isst_set_trl(int cpu, unsigned long long trl);
218extern int isst_set_trl_from_current_tdp(int cpu, unsigned long long trl);
219extern int isst_get_config_tdp_lock_status(int cpu);
220
221extern int isst_pm_qos_config(int cpu, int enable_clos, int priority_type);
222extern int isst_pm_get_clos(int cpu, int clos,
223 struct isst_clos_config *clos_config);
224extern int isst_set_clos(int cpu, int clos,
225 struct isst_clos_config *clos_config);
226extern int isst_clos_associate(int cpu, int clos);
227extern int isst_clos_get_assoc_status(int cpu, int *clos_id);
228extern void isst_clos_display_information(int cpu, FILE *outf, int clos,
229 struct isst_clos_config *clos_config);
230extern void isst_clos_display_assoc_information(int cpu, FILE *outf, int clos);
231extern int isst_read_reg(unsigned short reg, unsigned int *val);
232extern int isst_write_reg(int reg, unsigned int val);
233
234extern void isst_display_result(int cpu, FILE *outf, char *feature, char *cmd,
235 int result);
236
237extern int isst_clos_get_clos_information(int cpu, int *enable, int *type);
238extern void isst_clos_display_clos_information(int cpu, FILE *outf,
239 int clos_enable, int type);
240#endif