| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2006 |
| 3 | * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | |
| 10 | #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) |
| 11 | # if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) |
| 12 | |
| 13 | #include <asm/arch/pxa-regs.h> |
| 14 | #include <asm/io.h> |
| 15 | #include <usb.h> |
| 16 | |
| 17 | int usb_cpu_init(void) |
| 18 | { |
| 19 | #if defined(CONFIG_CPU_MONAHANS) |
| 20 | /* Enable USB host clock. */ |
| 21 | writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA); |
| 22 | udelay(100); |
| 23 | #endif |
| 24 | #if defined(CONFIG_CPU_PXA27X) |
| 25 | /* Enable USB host clock. */ |
| 26 | writel(readl(CKEN) | CKEN10_USBHOST, CKEN); |
| 27 | #endif |
| 28 | |
| 29 | #if defined(CONFIG_CPU_MONAHANS) |
| 30 | /* Configure Port 2 for Host (USB Client Registers) */ |
| 31 | writel(0x3000c, UP2OCR); |
| 32 | #endif |
| 33 | |
| 34 | writel(readl(UHCHR) | UHCHR_FHR, UHCHR); |
| 35 | mdelay(11); |
| 36 | writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); |
| 37 | |
| 38 | writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); |
| 39 | while (readl(UHCHR) & UHCHR_FSBIR) |
| 40 | udelay(1); |
| 41 | |
| 42 | #if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) |
| 43 | writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); |
| 44 | #endif |
| 45 | #if defined(CONFIG_CPU_PXA27X) |
| 46 | writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR); |
| 47 | #endif |
| 48 | writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR); |
| 49 | |
| 50 | return 0; |
| 51 | } |
| 52 | |
| 53 | int usb_cpu_stop(void) |
| 54 | { |
| 55 | writel(readl(UHCHR) | UHCHR_FHR, UHCHR); |
| 56 | udelay(11); |
| 57 | writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); |
| 58 | |
| 59 | writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS); |
| 60 | udelay(10); |
| 61 | |
| 62 | #if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) |
| 63 | writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR); |
| 64 | #endif |
| 65 | #if defined(CONFIG_CPU_PXA27X) |
| 66 | writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR); |
| 67 | #endif |
| 68 | writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR); |
| 69 | |
| 70 | #if defined(CONFIG_CPU_MONAHANS) |
| 71 | /* Disable USB host clock. */ |
| 72 | writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA); |
| 73 | udelay(100); |
| 74 | #endif |
| 75 | #if defined(CONFIG_CPU_PXA27X) |
| 76 | /* Disable USB host clock. */ |
| 77 | writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); |
| 78 | #endif |
| 79 | |
| 80 | return 0; |
| 81 | } |
| 82 | |
| 83 | int usb_cpu_init_fail(void) |
| 84 | { |
| 85 | return usb_cpu_stop(); |
| 86 | } |
| 87 | |
| 88 | # endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */ |
| 89 | #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ |