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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / uboot / arch / arm / cpu / tegra-common / ap.c
blob: 60d71a6c30ad01a50d2a533cd734a71b216e7f8e [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1/*
2* (C) Copyright 2010-2011
3* NVIDIA Corporation <www.nvidia.com>
4*
5 * SPDX-License-Identifier: GPL-2.0+
6*/
7
8/* Tegra AP (Application Processor) code */
9
10#include <common.h>
11#include <asm/io.h>
12#include <asm/arch/gp_padctrl.h>
13#include <asm/arch-tegra/ap.h>
14#include <asm/arch-tegra/clock.h>
15#include <asm/arch-tegra/fuse.h>
16#include <asm/arch-tegra/pmc.h>
17#include <asm/arch-tegra/scu.h>
18#include <asm/arch-tegra/tegra.h>
19#include <asm/arch-tegra/warmboot.h>
20
21int tegra_get_chip(void)
22{
23 int rev;
24 struct apb_misc_gp_ctlr *gp =
25 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
26
27 /*
28 * This is undocumented, Chip ID is bits 15:8 of the register
29 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
30 * Tegra30, and 0x35 for T114.
31 */
32 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
33 debug("%s: CHIPID is 0x%02X\n", __func__, rev);
34
35 return rev;
36}
37
38int tegra_get_sku_info(void)
39{
40 int sku_id;
41 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
42
43 sku_id = readl(&fuse->sku_info) & 0xff;
44 debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
45
46 return sku_id;
47}
48
49int tegra_get_chip_sku(void)
50{
51 uint sku_id, chip_id;
52
53 chip_id = tegra_get_chip();
54 sku_id = tegra_get_sku_info();
55
56 switch (chip_id) {
57 case CHIPID_TEGRA20:
58 switch (sku_id) {
59 case SKU_ID_T20_7:
60 case SKU_ID_T20:
61 return TEGRA_SOC_T20;
62 case SKU_ID_T25SE:
63 case SKU_ID_AP25:
64 case SKU_ID_T25:
65 case SKU_ID_AP25E:
66 case SKU_ID_T25E:
67 return TEGRA_SOC_T25;
68 }
69 break;
70 case CHIPID_TEGRA30:
71 switch (sku_id) {
72 case SKU_ID_T33:
73 case SKU_ID_T30:
74 case SKU_ID_TM30MQS_P_A3:
75 return TEGRA_SOC_T30;
76 }
77 break;
78 case CHIPID_TEGRA114:
79 switch (sku_id) {
80 case SKU_ID_T114_ENG:
81 case SKU_ID_T114_1:
82 return TEGRA_SOC_T114;
83 }
84 break;
85 }
86 /* unknown chip/sku id */
87 printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
88 __func__, chip_id, sku_id);
89 return TEGRA_SOC_UNKNOWN;
90}
91
92static void enable_scu(void)
93{
94 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
95 u32 reg;
96
97 /* Only enable the SCU on T20/T25 */
98 if (tegra_get_chip() != CHIPID_TEGRA20)
99 return;
100
101 /* If SCU already setup/enabled, return */
102 if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
103 return;
104
105 /* Invalidate all ways for all processors */
106 writel(0xFFFF, &scu->scu_inv_all);
107
108 /* Enable SCU - bit 0 */
109 reg = readl(&scu->scu_ctrl);
110 reg |= SCU_CTRL_ENABLE;
111 writel(reg, &scu->scu_ctrl);
112}
113
114static u32 get_odmdata(void)
115{
116 /*
117 * ODMDATA is stored in the BCT in IRAM by the BootROM.
118 * The BCT start and size are stored in the BIT in IRAM.
119 * Read the data @ bct_start + (bct_size - 12). This works
120 * on T20 and T30 BCTs, which are locked down. If this changes
121 * in new chips (T114, etc.), we can revisit this algorithm.
122 */
123
124 u32 bct_start, odmdata;
125
126 bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
127 odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
128
129 return odmdata;
130}
131
132static void init_pmc_scratch(void)
133{
134 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
135 u32 odmdata;
136 int i;
137
138 /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
139 for (i = 0; i < 23; i++)
140 writel(0, &pmc->pmc_scratch1+i);
141
142 /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
143 odmdata = get_odmdata();
144 writel(odmdata, &pmc->pmc_scratch20);
145}
146
147void s_init(void)
148{
149 /* Init PMC scratch memory */
150 init_pmc_scratch();
151
152 enable_scu();
153
154 /* init the cache */
155 config_cache();
156}