| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2000-2003 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <asm/arch/imx-regs.h> |
| 13 | #include <asm/arch/clock.h> |
| 14 | |
| 15 | #ifdef CONFIG_FSL_ESDHC |
| 16 | DECLARE_GLOBAL_DATA_PTR; |
| 17 | #endif |
| 18 | |
| 19 | int get_clocks(void) |
| 20 | { |
| 21 | #ifdef CONFIG_FSL_ESDHC |
| 22 | #ifdef CONFIG_FSL_USDHC |
| 23 | #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR |
| 24 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 25 | #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR |
| 26 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| 27 | #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR |
| 28 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| 29 | #else |
| 30 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
| 31 | #endif |
| 32 | #else |
| 33 | #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR |
| 34 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 35 | #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR |
| 36 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| 37 | #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR |
| 38 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| 39 | #else |
| 40 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
| 41 | #endif |
| 42 | #endif |
| 43 | #endif |
| 44 | return 0; |
| 45 | } |