| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Sascha Hauer, Pengutronix |
| 4 | * |
| 5 | * (C) Copyright 2009 Freescale Semiconductor, Inc. |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #include <common.h> |
| 11 | #include <asm/io.h> |
| 12 | #include <div64.h> |
| 13 | #include <asm/arch/imx-regs.h> |
| 14 | #include <asm/arch/clock.h> |
| 15 | |
| 16 | /* General purpose timers registers */ |
| 17 | struct mxc_gpt { |
| 18 | unsigned int control; |
| 19 | unsigned int prescaler; |
| 20 | unsigned int status; |
| 21 | unsigned int nouse[6]; |
| 22 | unsigned int counter; |
| 23 | }; |
| 24 | |
| 25 | static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; |
| 26 | |
| 27 | /* General purpose timers bitfields */ |
| 28 | #define GPTCR_SWR (1 << 15) /* Software reset */ |
| 29 | #define GPTCR_FRR (1 << 9) /* Freerun / restart */ |
| 30 | #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ |
| 31 | #define GPTCR_TEN 1 /* Timer enable */ |
| 32 | |
| 33 | DECLARE_GLOBAL_DATA_PTR; |
| 34 | |
| 35 | static inline unsigned long long tick_to_time(unsigned long long tick) |
| 36 | { |
| 37 | tick *= CONFIG_SYS_HZ; |
| 38 | do_div(tick, MXC_CLK32); |
| 39 | |
| 40 | return tick; |
| 41 | } |
| 42 | |
| 43 | static inline unsigned long long us_to_tick(unsigned long long usec) |
| 44 | { |
| 45 | usec = usec * MXC_CLK32 + 999999; |
| 46 | do_div(usec, 1000000); |
| 47 | |
| 48 | return usec; |
| 49 | } |
| 50 | |
| 51 | int timer_init(void) |
| 52 | { |
| 53 | int i; |
| 54 | |
| 55 | /* setup GP Timer 1 */ |
| 56 | __raw_writel(GPTCR_SWR, &cur_gpt->control); |
| 57 | |
| 58 | /* We have no udelay by now */ |
| 59 | for (i = 0; i < 100; i++) |
| 60 | __raw_writel(0, &cur_gpt->control); |
| 61 | |
| 62 | __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ |
| 63 | |
| 64 | /* Freerun Mode, PERCLK1 input */ |
| 65 | i = __raw_readl(&cur_gpt->control); |
| 66 | __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); |
| 67 | |
| 68 | gd->arch.tbl = __raw_readl(&cur_gpt->counter); |
| 69 | gd->arch.tbu = 0; |
| 70 | |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | unsigned long long get_ticks(void) |
| 75 | { |
| 76 | ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */ |
| 77 | |
| 78 | /* increment tbu if tbl has rolled over */ |
| 79 | if (now < gd->arch.tbl) |
| 80 | gd->arch.tbu++; |
| 81 | gd->arch.tbl = now; |
| 82 | return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; |
| 83 | } |
| 84 | |
| 85 | ulong get_timer_masked(void) |
| 86 | { |
| 87 | /* |
| 88 | * get_ticks() returns a long long (64 bit), it wraps in |
| 89 | * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ |
| 90 | * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in |
| 91 | * 5 * 10^6 days - long enough. |
| 92 | */ |
| 93 | return tick_to_time(get_ticks()); |
| 94 | } |
| 95 | |
| 96 | ulong get_timer(ulong base) |
| 97 | { |
| 98 | return get_timer_masked() - base; |
| 99 | } |
| 100 | |
| 101 | /* delay x useconds AND preserve advance timstamp value */ |
| 102 | void __udelay(unsigned long usec) |
| 103 | { |
| 104 | unsigned long long tmp; |
| 105 | ulong tmo; |
| 106 | |
| 107 | tmo = us_to_tick(usec); |
| 108 | tmp = get_ticks() + tmo; /* get current timestamp */ |
| 109 | |
| 110 | while (get_ticks() < tmp) /* loop till event */ |
| 111 | /*NOP*/; |
| 112 | } |
| 113 | |
| 114 | /* |
| 115 | * This function is derived from PowerPC code (timebase clock frequency). |
| 116 | * On ARM it returns the number of timer ticks per second. |
| 117 | */ |
| 118 | ulong get_tbclk(void) |
| 119 | { |
| 120 | return MXC_CLK32; |
| 121 | } |