| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Freescale i.MXS Register Accessors |
| 3 | * |
| 4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
| 5 | * on behalf of DENX Software Engineering GmbH |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #ifndef __MXS_REGS_COMMON_H__ |
| 11 | #define __MXS_REGS_COMMON_H__ |
| 12 | |
| 13 | /* |
| 14 | * The i.MXS has interesting feature when it comes to register access. There |
| 15 | * are four kinds of access to one particular register. Those are: |
| 16 | * |
| 17 | * 1) Common read/write access. To use this mode, just write to the address of |
| 18 | * the register. |
| 19 | * 2) Set bits only access. To set bits, write which bits you want to set to the |
| 20 | * address of the register + 0x4. |
| 21 | * 3) Clear bits only access. To clear bits, write which bits you want to clear |
| 22 | * to the address of the register + 0x8. |
| 23 | * 4) Toggle bits only access. To toggle bits, write which bits you want to |
| 24 | * toggle to the address of the register + 0xc. |
| 25 | * |
| 26 | * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits |
| 27 | * can be set/cleared by pure write as in access type 1, some need to be |
| 28 | * explicitly set/cleared by using access type 2-3. |
| 29 | * |
| 30 | * The following macros and structures allow the user to either access the |
| 31 | * register in all aforementioned modes (by accessing reg_name, reg_name_set, |
| 32 | * reg_name_clr, reg_name_tog) or pass the register structure further into |
| 33 | * various functions with correct type information (by accessing reg_name_reg). |
| 34 | * |
| 35 | */ |
| 36 | |
| 37 | #define __mxs_reg_8(name) \ |
| 38 | uint8_t name[4]; \ |
| 39 | uint8_t name##_set[4]; \ |
| 40 | uint8_t name##_clr[4]; \ |
| 41 | uint8_t name##_tog[4]; \ |
| 42 | |
| 43 | #define __mxs_reg_32(name) \ |
| 44 | uint32_t name; \ |
| 45 | uint32_t name##_set; \ |
| 46 | uint32_t name##_clr; \ |
| 47 | uint32_t name##_tog; |
| 48 | |
| 49 | struct mxs_register_8 { |
| 50 | __mxs_reg_8(reg) |
| 51 | }; |
| 52 | |
| 53 | struct mxs_register_32 { |
| 54 | __mxs_reg_32(reg) |
| 55 | }; |
| 56 | |
| 57 | #define mxs_reg_8(name) \ |
| 58 | union { \ |
| 59 | struct { __mxs_reg_8(name) }; \ |
| 60 | struct mxs_register_8 name##_reg; \ |
| 61 | }; |
| 62 | |
| 63 | #define mxs_reg_32(name) \ |
| 64 | union { \ |
| 65 | struct { __mxs_reg_32(name) }; \ |
| 66 | struct mxs_register_32 name##_reg; \ |
| 67 | }; |
| 68 | |
| 69 | #endif /* __MXS_REGS_COMMON_H__ */ |