| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Marius Groeger <mgroeger@sysgo.de> |
| 5 | * |
| 6 | * (C) Copyright 2002 |
| 7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 8 | * Alex Zuepke <azu@sysgo.de> |
| 9 | * |
| 10 | * SPDX-License-Identifier: GPL-2.0+ |
| 11 | */ |
| 12 | |
| 13 | #ifndef _U_BOOT_ARM_H_ |
| 14 | #define _U_BOOT_ARM_H_ 1 |
| 15 | |
| 16 | /* for the following variables, see start.S */ |
| 17 | extern ulong IRQ_STACK_START; /* top of IRQ stack */ |
| 18 | extern ulong FIQ_STACK_START; /* top of FIQ stack */ |
| 19 | extern ulong _datarel_start_ofs; |
| 20 | extern ulong _datarelrolocal_start_ofs; |
| 21 | extern ulong _datarellocal_start_ofs; |
| 22 | extern ulong _datarelro_start_ofs; |
| 23 | extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */ |
| 24 | |
| 25 | /* cpu/.../cpu.c */ |
| 26 | int cpu_init(void); |
| 27 | int cleanup_before_linux(void); |
| 28 | |
| 29 | /* Set up ARMv7 MMU, caches and TLBs */ |
| 30 | void cpu_init_cp15(void); |
| 31 | |
| 32 | /* cpu/.../arch/cpu.c */ |
| 33 | int arch_cpu_init(void); |
| 34 | int arch_misc_init(void); |
| 35 | int arch_early_init_r(void); |
| 36 | |
| 37 | /* board/.../... */ |
| 38 | int board_init(void); |
| 39 | int dram_init (void); |
| 40 | void dram_init_banksize (void); |
| 41 | |
| 42 | /* cpu/.../interrupt.c */ |
| 43 | int arch_interrupt_init (void); |
| 44 | void reset_timer_masked (void); |
| 45 | ulong get_timer_masked (void); |
| 46 | void udelay_masked (unsigned long usec); |
| 47 | |
| 48 | #endif /* _U_BOOT_ARM_H_ */ |