| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * |
| 3 | * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. |
| 4 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | /* CPU specific interrupt routine */ |
| 10 | #include <common.h> |
| 11 | #include <asm/immap.h> |
| 12 | #include <asm/io.h> |
| 13 | |
| 14 | int interrupt_init(void) |
| 15 | { |
| 16 | int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); |
| 17 | |
| 18 | /* Make sure all interrupts are disabled */ |
| 19 | setbits_be32(&intp->imrh0, 0xffffffff); |
| 20 | setbits_be32(&intp->imrl0, 0xffffffff); |
| 21 | |
| 22 | enable_interrupts(); |
| 23 | |
| 24 | return 0; |
| 25 | } |
| 26 | |
| 27 | #if defined(CONFIG_SLTTMR) |
| 28 | void dtimer_intr_setup(void) |
| 29 | { |
| 30 | int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); |
| 31 | |
| 32 | out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); |
| 33 | clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); |
| 34 | } |
| 35 | #endif |