| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2011 The Chromium OS Authors. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef __MIPS_CACHE_H__ |
| 8 | #define __MIPS_CACHE_H__ |
| 9 | |
| 10 | /* |
| 11 | * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use |
| 12 | * that as a default for aligning DMA buffers unless the board config has |
| 13 | * specified another cache line size. |
| 14 | */ |
| 15 | #ifdef CONFIG_SYS_CACHELINE_SIZE |
| 16 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE |
| 17 | #else |
| 18 | #define ARCH_DMA_MINALIGN 128 |
| 19 | #endif |
| 20 | |
| 21 | #endif /* __MIPS_CACHE_H__ */ |