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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / uboot / arch / powerpc / cpu / mpc86xx / speed.c
blob: 5abe6f0bf2cf102a0ce8a4e75ba593e373687089 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1/*
2 * Copyright 2004 Freescale Semiconductor.
3 * Jeff Brown
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 *
6 * (C) Copyright 2000-2002
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12#include <common.h>
13#include <mpc86xx.h>
14#include <asm/processor.h>
15#include <asm/io.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19/* used in some defintiions of CONFIG_SYS_CLK_FREQ */
20extern unsigned long get_board_sys_clk(unsigned long dummy);
21
22void get_sys_info(sys_info_t *sys_info)
23{
24 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
25 volatile ccsr_gur_t *gur = &immap->im_gur;
26 uint plat_ratio, e600_ratio;
27 uint lcrr_div;
28
29 plat_ratio = (gur->porpllsr) & 0x0000003e;
30 plat_ratio >>= 1;
31
32 switch (plat_ratio) {
33 case 0x0:
34 sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ;
35 break;
36 case 0x02:
37 case 0x03:
38 case 0x04:
39 case 0x05:
40 case 0x06:
41 case 0x08:
42 case 0x09:
43 case 0x0a:
44 case 0x0c:
45 case 0x10:
46 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
47 break;
48 default:
49 sys_info->freq_systembus = 0;
50 break;
51 }
52
53 e600_ratio = (gur->porpllsr) & 0x003f0000;
54 e600_ratio >>= 16;
55
56 switch (e600_ratio) {
57 case 0x10:
58 sys_info->freq_processor = 2 * sys_info->freq_systembus;
59 break;
60 case 0x19:
61 sys_info->freq_processor = 5 * sys_info->freq_systembus / 2;
62 break;
63 case 0x20:
64 sys_info->freq_processor = 3 * sys_info->freq_systembus;
65 break;
66 case 0x39:
67 sys_info->freq_processor = 7 * sys_info->freq_systembus / 2;
68 break;
69 case 0x28:
70 sys_info->freq_processor = 4 * sys_info->freq_systembus;
71 break;
72 case 0x1d:
73 sys_info->freq_processor = 9 * sys_info->freq_systembus / 2;
74 break;
75 default:
76 sys_info->freq_processor = e600_ratio +
77 sys_info->freq_systembus;
78 break;
79 }
80
81#if defined(CONFIG_SYS_LBC_LCRR)
82 /* We will program LCRR to this value later */
83 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
84#else
85 lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
86#endif
87 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
88 sys_info->freq_localbus = sys_info->freq_systembus
89 / (lcrr_div * 2);
90 } else {
91 /* In case anyone cares what the unknown value is */
92 sys_info->freq_localbus = lcrr_div;
93 }
94}
95
96
97/*
98 * Measure CPU clock speed (core clock GCLK1, GCLK2)
99 * (Approx. GCLK frequency in Hz)
100 */
101
102int get_clocks(void)
103{
104 sys_info_t sys_info;
105
106 get_sys_info(&sys_info);
107 gd->cpu_clk = sys_info.freq_processor;
108 gd->bus_clk = sys_info.freq_systembus;
109 gd->arch.lbc_clk = sys_info.freq_localbus;
110
111 /*
112 * The base clock for I2C depends on the actual SOC. Unfortunately,
113 * there is no pattern that can be used to determine the frequency, so
114 * the only choice is to look up the actual SOC number and use the value
115 * for that SOC. This information is taken from application note
116 * AN2919.
117 */
118#ifdef CONFIG_MPC8610
119 gd->arch.i2c1_clk = sys_info.freq_systembus;
120#else
121 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
122#endif
123 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
124
125 if (gd->cpu_clk != 0)
126 return 0;
127 else
128 return 1;
129}
130
131
132/*
133 * get_bus_freq
134 * Return system bus freq in Hz
135 */
136
137ulong get_bus_freq(ulong dummy)
138{
139 ulong val;
140 sys_info_t sys_info;
141
142 get_sys_info(&sys_info);
143 val = sys_info.freq_systembus;
144
145 return val;
146}