| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2006 DENX Software Engineering |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
| 9 | |
| 10 | #if defined(CONFIG_CMD_NAND) |
| 11 | |
| 12 | #include <nand.h> |
| 13 | |
| 14 | /* |
| 15 | * hardware specific access to control-lines |
| 16 | * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) |
| 17 | */ |
| 18 | static void ppchameleonevb_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
| 19 | { |
| 20 | struct nand_chip *this = mtd->priv; |
| 21 | ulong base = (ulong) this->IO_ADDR_W; |
| 22 | |
| 23 | if (ctrl & NAND_CTRL_CHANGE) { |
| 24 | if ( ctrl & NAND_CLE ) |
| 25 | MACRO_NAND_CTL_SETCLE((unsigned long)base); |
| 26 | else |
| 27 | MACRO_NAND_CTL_CLRCLE((unsigned long)base); |
| 28 | if ( ctrl & NAND_ALE ) |
| 29 | MACRO_NAND_CTL_CLRCLE((unsigned long)base); |
| 30 | else |
| 31 | MACRO_NAND_CTL_CLRALE((unsigned long)base); |
| 32 | if ( ctrl & NAND_NCE ) |
| 33 | MACRO_NAND_ENABLE_CE((unsigned long)base); |
| 34 | else |
| 35 | MACRO_NAND_DISABLE_CE((unsigned long)base); |
| 36 | } |
| 37 | |
| 38 | if (cmd != NAND_CMD_NONE) |
| 39 | writeb(cmd, this->IO_ADDR_W); |
| 40 | } |
| 41 | |
| 42 | |
| 43 | /* |
| 44 | * read device ready pin |
| 45 | * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) |
| 46 | */ |
| 47 | static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo) |
| 48 | { |
| 49 | struct nand_chip *this = mtdinfo->priv; |
| 50 | ulong rb_gpio_pin; |
| 51 | |
| 52 | /* use the base addr to find out which chip are we dealing with */ |
| 53 | switch((ulong) this->IO_ADDR_W) { |
| 54 | case CONFIG_SYS_NAND0_BASE: |
| 55 | rb_gpio_pin = CONFIG_SYS_NAND0_RDY; |
| 56 | break; |
| 57 | case CONFIG_SYS_NAND1_BASE: |
| 58 | rb_gpio_pin = CONFIG_SYS_NAND1_RDY; |
| 59 | break; |
| 60 | default: /* this should never happen */ |
| 61 | return 0; |
| 62 | break; |
| 63 | } |
| 64 | |
| 65 | if (in32(GPIO0_IR) & rb_gpio_pin) |
| 66 | return 1; |
| 67 | return 0; |
| 68 | } |
| 69 | |
| 70 | |
| 71 | /* |
| 72 | * Board-specific NAND initialization. The following members of the |
| 73 | * argument are board-specific (per include/linux/mtd/nand.h): |
| 74 | * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device |
| 75 | * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device |
| 76 | * - cmd_ctrl: hardwarespecific function for accesing control-lines |
| 77 | * - dev_ready: hardwarespecific function for accesing device ready/busy line |
| 78 | * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must |
| 79 | * only be provided if a hardware ECC is available |
| 80 | * - ecc.mode: mode of ecc, see defines |
| 81 | * - chip_delay: chip dependent delay for transfering data from array to |
| 82 | * read regs (tR) |
| 83 | * - options: various chip options. They can partly be set to inform |
| 84 | * nand_scan about special functionality. See the defines for further |
| 85 | * explanation |
| 86 | * Members with a "?" were not set in the merged testing-NAND branch, |
| 87 | * so they are not set here either. |
| 88 | */ |
| 89 | int board_nand_init(struct nand_chip *nand) |
| 90 | { |
| 91 | |
| 92 | nand->cmd_ctrl = ppchameleonevb_hwcontrol; |
| 93 | nand->dev_ready = ppchameleonevb_device_ready; |
| 94 | nand->ecc.mode = NAND_ECC_SOFT; |
| 95 | nand->chip_delay = NAND_BIG_DELAY_US; |
| 96 | nand->options = NAND_SAMSUNG_LP_OPTIONS; |
| 97 | return 0; |
| 98 | } |
| 99 | #endif |