blob: b642e1255ca3141def00e73569b14caf5fffdf33 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001/*
2 * Copyright 2009, 2011 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#include <common.h>
7
8#include <fsl_ddr_sdram.h>
9#include <fsl_ddr_dimm_params.h>
10
11void fsl_ddr_board_options(memctl_options_t *popts,
12 dimm_params_t *pdimm,
13 unsigned int ctrl_num)
14{
15 if (ctrl_num) {
16 printf("Wrong parameter for controller number %d", ctrl_num);
17 return;
18 }
19
20 if (!pdimm->n_ranks)
21 return;
22
23 /*
24 * Set DDR_SDRAM_CLK_CNTL = 0x02800000
25 *
26 * Clock is launched 5/8 applied cycle after address/command
27 */
28 popts->clk_adjust = 5;
29}