| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2006 |
| 3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de |
| 4 | * |
| 5 | * (C) Copyright 2006 |
| 6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | |
| 13 | #if defined(CONFIG_CMD_NAND) |
| 14 | |
| 15 | #include <asm/processor.h> |
| 16 | #include <nand.h> |
| 17 | |
| 18 | struct alpr_ndfc_regs { |
| 19 | u8 cmd[4]; |
| 20 | u8 addr_wait; |
| 21 | u8 term; |
| 22 | u8 dummy; |
| 23 | u8 dummy2; |
| 24 | u8 data; |
| 25 | }; |
| 26 | |
| 27 | static u8 hwctl; |
| 28 | static struct alpr_ndfc_regs *alpr_ndfc = NULL; |
| 29 | |
| 30 | #define readb(addr) (u8)(*(volatile u8 *)(addr)) |
| 31 | #define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d)) |
| 32 | |
| 33 | /* |
| 34 | * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to |
| 35 | * the NAND devices. The NDFC has command, address and data registers that |
| 36 | * when accessed will set up the NAND flash pins appropriately. We'll use the |
| 37 | * hwcontrol function to save the configuration in a global variable. |
| 38 | * We can then use this information in the read and write functions to |
| 39 | * determine which NDFC register to access. |
| 40 | * |
| 41 | * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte). |
| 42 | */ |
| 43 | static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
| 44 | { |
| 45 | struct nand_chip *this = mtd->priv; |
| 46 | |
| 47 | if (ctrl & NAND_CTRL_CHANGE) { |
| 48 | if ( ctrl & NAND_CLE ) |
| 49 | hwctl |= 0x1; |
| 50 | else |
| 51 | hwctl &= ~0x1; |
| 52 | if ( ctrl & NAND_ALE ) |
| 53 | hwctl |= 0x2; |
| 54 | else |
| 55 | hwctl &= ~0x2; |
| 56 | if ( (ctrl & NAND_NCE) != NAND_NCE) |
| 57 | writeb(0x00, &(alpr_ndfc->term)); |
| 58 | } |
| 59 | if (cmd != NAND_CMD_NONE) |
| 60 | writeb(cmd, this->IO_ADDR_W); |
| 61 | } |
| 62 | |
| 63 | static u_char alpr_nand_read_byte(struct mtd_info *mtd) |
| 64 | { |
| 65 | return readb(&(alpr_ndfc->data)); |
| 66 | } |
| 67 | |
| 68 | static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
| 69 | { |
| 70 | struct nand_chip *nand = mtd->priv; |
| 71 | int i; |
| 72 | |
| 73 | for (i = 0; i < len; i++) { |
| 74 | if (hwctl & 0x1) |
| 75 | /* |
| 76 | * IO_ADDR_W used as CMD[i] reg to support multiple NAND |
| 77 | * chips. |
| 78 | */ |
| 79 | writeb(buf[i], nand->IO_ADDR_W); |
| 80 | else if (hwctl & 0x2) |
| 81 | writeb(buf[i], &(alpr_ndfc->addr_wait)); |
| 82 | else |
| 83 | writeb(buf[i], &(alpr_ndfc->data)); |
| 84 | } |
| 85 | } |
| 86 | |
| 87 | static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
| 88 | { |
| 89 | int i; |
| 90 | |
| 91 | for (i = 0; i < len; i++) { |
| 92 | buf[i] = readb(&(alpr_ndfc->data)); |
| 93 | } |
| 94 | } |
| 95 | |
| 96 | static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) |
| 97 | { |
| 98 | int i; |
| 99 | |
| 100 | for (i = 0; i < len; i++) |
| 101 | if (buf[i] != readb(&(alpr_ndfc->data))) |
| 102 | return i; |
| 103 | |
| 104 | return 0; |
| 105 | } |
| 106 | |
| 107 | static int alpr_nand_dev_ready(struct mtd_info *mtd) |
| 108 | { |
| 109 | /* |
| 110 | * Blocking read to wait for NAND to be ready |
| 111 | */ |
| 112 | (void)readb(&(alpr_ndfc->addr_wait)); |
| 113 | |
| 114 | /* |
| 115 | * Return always true |
| 116 | */ |
| 117 | return 1; |
| 118 | } |
| 119 | |
| 120 | int board_nand_init(struct nand_chip *nand) |
| 121 | { |
| 122 | alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE; |
| 123 | |
| 124 | nand->ecc.mode = NAND_ECC_SOFT; |
| 125 | |
| 126 | /* Reference hardware control function */ |
| 127 | nand->cmd_ctrl = alpr_nand_hwcontrol; |
| 128 | nand->read_byte = alpr_nand_read_byte; |
| 129 | nand->write_buf = alpr_nand_write_buf; |
| 130 | nand->read_buf = alpr_nand_read_buf; |
| 131 | nand->verify_buf = alpr_nand_verify_buf; |
| 132 | nand->dev_ready = alpr_nand_dev_ready; |
| 133 | |
| 134 | return 0; |
| 135 | } |
| 136 | #endif |