| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <netdev.h> |
| 9 | #include <zynqpl.h> |
| 10 | #include <asm/arch/hardware.h> |
| 11 | #include <asm/arch/sys_proto.h> |
| 12 | |
| 13 | DECLARE_GLOBAL_DATA_PTR; |
| 14 | |
| 15 | /* Bootmode setting values */ |
| 16 | #define ZYNQ_BM_MASK 0x0F |
| 17 | #define ZYNQ_BM_NOR 0x02 |
| 18 | #define ZYNQ_BM_SD 0x05 |
| 19 | #define ZYNQ_BM_JTAG 0x0 |
| 20 | |
| 21 | #ifdef CONFIG_FPGA |
| 22 | Xilinx_desc fpga; |
| 23 | |
| 24 | /* It can be done differently */ |
| 25 | Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); |
| 26 | Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); |
| 27 | Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); |
| 28 | Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); |
| 29 | Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); |
| 30 | #endif |
| 31 | |
| 32 | int board_init(void) |
| 33 | { |
| 34 | #ifdef CONFIG_FPGA |
| 35 | u32 idcode; |
| 36 | |
| 37 | idcode = zynq_slcr_get_idcode(); |
| 38 | |
| 39 | switch (idcode) { |
| 40 | case XILINX_ZYNQ_7010: |
| 41 | fpga = fpga010; |
| 42 | break; |
| 43 | case XILINX_ZYNQ_7020: |
| 44 | fpga = fpga020; |
| 45 | break; |
| 46 | case XILINX_ZYNQ_7030: |
| 47 | fpga = fpga030; |
| 48 | break; |
| 49 | case XILINX_ZYNQ_7045: |
| 50 | fpga = fpga045; |
| 51 | break; |
| 52 | case XILINX_ZYNQ_7100: |
| 53 | fpga = fpga100; |
| 54 | break; |
| 55 | } |
| 56 | #endif |
| 57 | |
| 58 | icache_enable(); |
| 59 | |
| 60 | #ifdef CONFIG_FPGA |
| 61 | fpga_init(); |
| 62 | fpga_add(fpga_xilinx, &fpga); |
| 63 | #endif |
| 64 | |
| 65 | return 0; |
| 66 | } |
| 67 | |
| 68 | int board_late_init(void) |
| 69 | { |
| 70 | switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { |
| 71 | case ZYNQ_BM_NOR: |
| 72 | setenv("modeboot", "norboot"); |
| 73 | break; |
| 74 | case ZYNQ_BM_SD: |
| 75 | setenv("modeboot", "sdboot"); |
| 76 | break; |
| 77 | case ZYNQ_BM_JTAG: |
| 78 | setenv("modeboot", "jtagboot"); |
| 79 | break; |
| 80 | default: |
| 81 | setenv("modeboot", ""); |
| 82 | break; |
| 83 | } |
| 84 | |
| 85 | return 0; |
| 86 | } |
| 87 | |
| 88 | #ifdef CONFIG_CMD_NET |
| 89 | int board_eth_init(bd_t *bis) |
| 90 | { |
| 91 | u32 ret = 0; |
| 92 | |
| 93 | #ifdef CONFIG_XILINX_AXIEMAC |
| 94 | ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, |
| 95 | XILINX_AXIDMA_BASEADDR); |
| 96 | #endif |
| 97 | #ifdef CONFIG_XILINX_EMACLITE |
| 98 | u32 txpp = 0; |
| 99 | u32 rxpp = 0; |
| 100 | # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG |
| 101 | txpp = 1; |
| 102 | # endif |
| 103 | # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG |
| 104 | rxpp = 1; |
| 105 | # endif |
| 106 | ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, |
| 107 | txpp, rxpp); |
| 108 | #endif |
| 109 | |
| 110 | #if defined(CONFIG_ZYNQ_GEM) |
| 111 | # if defined(CONFIG_ZYNQ_GEM0) |
| 112 | ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, |
| 113 | CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); |
| 114 | # endif |
| 115 | # if defined(CONFIG_ZYNQ_GEM1) |
| 116 | ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, |
| 117 | CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); |
| 118 | # endif |
| 119 | #endif |
| 120 | return ret; |
| 121 | } |
| 122 | #endif |
| 123 | |
| 124 | #ifdef CONFIG_CMD_MMC |
| 125 | int board_mmc_init(bd_t *bd) |
| 126 | { |
| 127 | int ret = 0; |
| 128 | |
| 129 | #if defined(CONFIG_ZYNQ_SDHCI) |
| 130 | # if defined(CONFIG_ZYNQ_SDHCI0) |
| 131 | ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); |
| 132 | # endif |
| 133 | # if defined(CONFIG_ZYNQ_SDHCI1) |
| 134 | ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); |
| 135 | # endif |
| 136 | #endif |
| 137 | return ret; |
| 138 | } |
| 139 | #endif |
| 140 | |
| 141 | int dram_init(void) |
| 142 | { |
| 143 | gd->ram_size = CONFIG_SYS_SDRAM_SIZE; |
| 144 | |
| 145 | zynq_ddrc_init(); |
| 146 | |
| 147 | return 0; |
| 148 | } |