marvell/uboot/drivers/crypto/bcm/asr_bcm.c

#include <asm/arch/cpu.h>
#include <asm/io.h>
#include "asr_bcm.h"
#include "asr_hash.h"

void bcm_enable(int enable)
{
    uint32_t val;
    /* it will no longer enable clk if the clk has been enabled */
    static int enabled = 0; 

    if (enable) {
        /* enable clock */
        val = bcm_read32((AES_CLK_RES_CTRL));
        if ((val & (1 << 4 | 1 << 5)) == (1 << 4 | 1 << 5)) {
			enabled = 1;
            return;
		}
        val |= (1 << 4 | 1 << 5);
        bcm_write32(AES_CLK_RES_CTRL, val);

        /* init */
        bcm_write32(BIU_SP_CONTROL, 0x6);
        bcm_write32(BIU_SP_INTERRUPT_MASK, 0xFFFFFFFF);
        bcm_write32(BIU_HST_INTERRUPT_MASK, 0xFFFFFFFF);
        bcm_write32(ADEC_INT_MSK, 0xFFFFFFFF);
    } else {
        /* disable clock */
        if (enabled) {
            return;
        }
        val = bcm_read32(AES_CLK_RES_CTRL);
        val &= ~(1 << 4);
        bcm_write32(AES_CLK_RES_CTRL, val);
    }
}

int dma_input_config(int rid_ext, int rid)
{
    uint32_t val;

    val = bcm_read32(DMA_IN_CTRL);
    val &= 0x0f0f0000;
    val |= (0x7 << 28) |    /* dis error check */
        ((rid_ext & 0xF) << 20) |   /* rid ext */
        (0x1 << 18) |   /* dis out-of-order */
        (0x1 << 17) |   /* data 64 byte aligned */
        (0x1 << 15) |   /* FIFO bus size 64bit */
        (0x1 << 13) |   /* brust type: Inc */
        (0x8 << 8)  |   /* brust len */
        ((rid & 0xF) << 4);

    bcm_write32(DMA_IN_CTRL, val);

    return 0;
}

int dma_input_address(uint32_t src_addr, uint32_t src_size, int chained)
{
    if (chained) {
        bcm_write32(DMA_IN_NX_LL_ADR, src_addr);
        bcm_write32(DMA_IN_SRC_ADR, 0x0);
        bcm_write32(DMA_IN_XFER_CNTR, 0x0);
    } else {
        bcm_write32(DMA_IN_NX_LL_ADR, 0x0);
        bcm_write32(DMA_IN_SRC_ADR, src_addr);
        bcm_write32(DMA_IN_XFER_CNTR, src_size);
    }

    return 0;
}

void dma_input_start(void)
{
    uint32_t val;

    val = bcm_read32(DMA_IN_INT);
    bcm_write32(DMA_IN_INT, val);

    val = bcm_read32(DMA_IN_CTRL);
    val |= 0x1;
    bcm_write32(DMA_IN_CTRL, val);

    return;
}

void dma_input_stop(void)
{
    uint32_t val;

    val = bcm_read32(DMA_IN_CTRL);
    val &= ~0x1;
    bcm_write32(DMA_IN_CTRL, val);

    return;
}

int dma_wait_input_finish(void)
{
    uint32_t val, val_ori;
    int loop;
    int ret = 0;

    loop = 10000;
    while (loop > 0) {
        val_ori = bcm_read32(DMA_IN_INT);
        val = (val_ori & 0x1);
        if (val !=0)
            break;
        loop--;
        udelay(1);
    }

    if (loop == 0) {
        ret = -1;
    } else {
        ret = 0;
    }

    dma_input_stop();

    val = bcm_read32(DMA_IN_INT);
    bcm_write32(DMA_IN_INT, val);

    return ret;
}

int adec_engine_hw_reset(ADEC_ACC_ENG_T engine)
{
    uint32_t val;
    int tmp;

    if (engine == ACC_ENG_ALL)
        tmp = 0xffff;
    else
        tmp = 1 << engine;

    val = bcm_read32(ADEC_CTRL);
    val |= tmp;
    bcm_write32(ADEC_CTRL, val);
    val &= ~tmp;
    bcm_write32(ADEC_CTRL, val);

    return 0;
}

int abus_set_mode(ABUS_GRP_A_T grp_a_mode,
                  ABUS_GRP_B_T grp_b_mode,
                  ABUS_CROSS_BAR_T input_bar,
                  ABUS_CROSS_BAR_T output_bar)
{
    uint32_t val;

    val = bcm_read32(ABUS_BUS_CTRL);

    val &= ~(0x77 << 0x4);
    val |= (grp_a_mode << 0x4) | (grp_b_mode << 0x8);

    if (input_bar == ABUS_STRAIGHT) {
        val &= ~(0x1 << 0x0);
    } else if (input_bar == ABUS_CROSS) {
        val |= (0x1 << 0x0);
    } else {
        return -1;
    }

    if (output_bar == ABUS_STRAIGHT) {
        val &= ~(0x1 << 0x2);
    } else if (input_bar == ABUS_CROSS) {
        val |= (0x1 << 0x2);
    } else {
        return -1;
    }

    bcm_write32(ABUS_BUS_CTRL, val);

    return 0;
}

int dma_output_config(int wid_ext, int wid)
{
	uint32_t val;

	val = bcm_read32(DMA_OUT_CTRL);
	val &= 0x0f0f0000;
	val |= (0x7 << 28) |    /* dis error check */
		((wid_ext & 0xF) << 20) |   /* rid ext */
		(0x1 << 18) |   /* dis out-of-order */
		(0x1 << 17) |   /* data 64 byte aligned */
		(0x1 << 15) |   /* FIFO bus size 64bit */
		(0x1 << 13) |   /* brust type: Inc */
		(0x8 << 8)  |   /* brust len */
		((wid & 0xF) << 4);

	bcm_write32(DMA_OUT_CTRL, val);

	return 0;
}

void dma_output_start(void)
{
	uint32_t val;

	val = bcm_read32(DMA_OUT_INT);
	bcm_write32(DMA_OUT_INT, val);

	val = bcm_read32(DMA_OUT_CTRL);
	val |= 0x1;
	bcm_write32(DMA_OUT_CTRL, val);

	return;
}

void dma_output_stop(void)
{
	uint32_t val;

	val = bcm_read32(DMA_OUT_CTRL);
	val &= ~0x1;
	bcm_write32(DMA_OUT_CTRL, val);

	return;
}

int dma_output_address(uint32_t dst_addr, uint32_t dst_size, int chained)
{
	if (chained) {
		bcm_write32(DMA_OUT_NX_LL_ADR, dst_addr);
		bcm_write32(DMA_OUT_DEST_ADR, 0x0);
		bcm_write32(DMA_OUT_XFER_CNTR, 0x0);
	} else {
		bcm_write32(DMA_OUT_NX_LL_ADR, 0x0);
		bcm_write32(DMA_OUT_DEST_ADR, dst_addr);
		bcm_write32(DMA_OUT_XFER_CNTR, dst_size);
	}

	return 0;
}

int dma_wait_output_finish(void)
{
	uint32_t val, val_ori;
	int loop;
	int ret = 0;

	loop = 10000;
	while (loop > 0) {
		val_ori = bcm_read32(DMA_OUT_INT);
		val = (val_ori & 0x1);
		if (val !=0)
			break;
		loop--;
		udelay(1);
	}

	if (loop == 0) {
		ret = -1;
	} else {
		ret = 0;
	}

	dma_output_stop();

	val = bcm_read32(DMA_OUT_INT);
	bcm_write32(DMA_OUT_INT, val);

	return ret;
}