blob: d51f1101499cc16dee64258a88ea8b0eda71e5e1 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001/*
2 * (C) Copyright 2000
3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
4 *
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
7 *
8 * (C) Copyright 2003 Pengutronix e.K.
9 * Robert Schwebel <r.schwebel@pengutronix.de>
10 *
11 * (C) Copyright 2011 Marvell Inc.
12 * Lei Wen <leiwen@marvell.com>
13 *
14 * SPDX-License-Identifier: GPL-2.0+
15 *
16 * Back ported to the 8xx platform (from the 8260 platform) by
17 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
18 */
19
20#include <common.h>
21#include <asm/io.h>
22#include <asm/arch/cpu.h>
23#ifdef CONFIG_HARD_I2C
24#include <i2c.h>
25#include "mv_i2c.h"
26
27#ifdef DEBUG_I2C
28#define PRINTD(x) printf x
29#else
30#define PRINTD(x)
31#endif
32
33/* All transfers are described by this data structure */
34struct i2c_msg {
35 u8 condition;
36 u8 acknack;
37 u8 direction;
38 u8 data;
39};
40
41#ifdef CONFIG_ASR1901
42struct mv_i2c {
43 u32 icr;
44 u32 isr;
45 u32 isar;
46 u32 idbr;
47 u32 ilcr;
48 u32 iwcr;
49 u32 pad0;
50 u32 ibmr;
51 u32 pad1;
52 u32 pad2;
53 u32 pad3;
54 u32 pad4;
55 u32 pad5;
56 u32 pad6;
57};
58#else
59struct mv_i2c {
60 u32 ibmr;
61 u32 pad0;
62 u32 idbr;
63 u32 pad1;
64 u32 icr;
65 u32 pad2;
66 u32 isr;
67 u32 pad3;
68 u32 isar;
69 u32 pad4;
70 u32 ilcr;
71 u32 pad5;
72 u32 iwcr;
73};
74#endif
75static struct mv_i2c *base;
76static void i2c_board_init(struct mv_i2c *base)
77{
78#ifdef CONFIG_SYS_I2C_INIT_BOARD
79 u32 icr;
80 /*
81 * call board specific i2c bus reset routine before accessing the
82 * environment, which might be in a chip on that bus. For details
83 * about this problem see doc/I2C_Edge_Conditions.
84 *
85 * disable I2C controller first, otherwhise it thinks we want to
86 * talk to the slave port...
87 */
88 icr = readl(&base->icr);
89 writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr);
90
91 i2c_init_board();
92
93 writel(icr, &base->icr);
94#endif
95 /* set for 100khz timing */
96 writel(0x82c469f, &base->ilcr);
97 writel(0x142A, &base->iwcr);
98}
99
100#ifdef CONFIG_I2C_MULTI_BUS
101static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
102static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
103static unsigned int current_bus;
104
105int i2c_set_bus_num(unsigned int bus)
106{
107 if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) {
108 printf("Bad bus: %d\n", bus);
109 return -1;
110 }
111
112 base = (struct mv_i2c *)(uintptr_t)i2c_regs[bus];
113 current_bus = bus;
114
115 if (!bus_initialized[current_bus]) {
116 i2c_board_init(base);
117 bus_initialized[current_bus] = 1;
118 }
119
120 return 0;
121}
122
123unsigned int i2c_get_bus_num(void)
124{
125 return current_bus;
126}
127#endif
128
129/*
130 * i2c_reset: - reset the host controller
131 *
132 */
133static void i2c_reset(void)
134{
135#if defined(CONFIG_PXA182X) || defined(CONFIG_ASR1802S) || defined(CONFIG_ASR1901)
136 if (readl(&base->ibmr) != 0x3) {
137 writel(readl(&base->icr) | ICR_BUS_RESET, &base->icr);
138 udelay((10 * 1000 * 1000 / CONFIG_SYS_I2C_SPEED));
139 printf("i2c bus rst done\n");
140 }
141#endif
142
143 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
144 writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
145 udelay(100);
146 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
147
148 i2c_clk_enable();
149
150#ifdef CONFIG_MV_I2C_SLAVE
151 writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
152#endif
153 writel(I2C_ICR_INIT, &base->icr); /* set control reg values */
154 writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
155 writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
156 udelay(100);
157}
158
159/*
160 * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
161 * are set and cleared
162 *
163 * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
164 */
165static int i2c_isr_set_cleared(unsigned long set_mask,
166 unsigned long cleared_mask)
167{
168 int timeout = 1000, isr;
169
170 do {
171 isr = readl(&base->isr);
172 udelay(10);
173 if (timeout-- < 0)
174 return 0;
175 } while (((isr & set_mask) != set_mask)
176 || ((isr & cleared_mask) != 0));
177
178 return 1;
179}
180
181/*
182 * i2c_transfer: - Transfer one byte over the i2c bus
183 *
184 * This function can tranfer a byte over the i2c bus in both directions.
185 * It is used by the public API functions.
186 *
187 * @return: 0: transfer successful
188 * -1: message is empty
189 * -2: transmit timeout
190 * -3: ACK missing
191 * -4: receive timeout
192 * -5: illegal parameters
193 * -6: bus is busy and couldn't be aquired
194 */
195int i2c_transfer(struct i2c_msg *msg)
196{
197 int ret;
198
199 if (!msg)
200 goto transfer_error_msg_empty;
201
202 switch (msg->direction) {
203 case I2C_WRITE:
204 /* check if bus is not busy */
205 if (!i2c_isr_set_cleared(0, ISR_IBB))
206 goto transfer_error_bus_busy;
207
208 /* start transmission */
209 writel(readl(&base->icr) & ~ICR_START, &base->icr);
210 writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
211 writel(msg->data, &base->idbr);
212 if (msg->condition == I2C_COND_START)
213 writel(readl(&base->icr) | ICR_START, &base->icr);
214 if (msg->condition == I2C_COND_STOP)
215 writel(readl(&base->icr) | ICR_STOP, &base->icr);
216 if (msg->acknack == I2C_ACKNAK_SENDNAK)
217 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
218 if (msg->acknack == I2C_ACKNAK_SENDACK)
219 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
220 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
221 writel(readl(&base->icr) | ICR_TB, &base->icr);
222
223 /* transmit register empty? */
224 if (!i2c_isr_set_cleared(ISR_ITE, 0))
225 goto transfer_error_transmit_timeout;
226
227 /* clear 'transmit empty' state */
228 writel(readl(&base->isr) | ISR_ITE, &base->isr);
229
230 /* wait for ACK from slave */
231 if (msg->acknack == I2C_ACKNAK_WAITACK)
232 if (!i2c_isr_set_cleared(0, ISR_ACKNAK))
233 goto transfer_error_ack_missing;
234 break;
235
236 case I2C_READ:
237
238 /* check if bus is not busy */
239 if (!i2c_isr_set_cleared(0, ISR_IBB))
240 goto transfer_error_bus_busy;
241
242 /* start receive */
243 writel(readl(&base->icr) & ~ICR_START, &base->icr);
244 writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
245 if (msg->condition == I2C_COND_START)
246 writel(readl(&base->icr) | ICR_START, &base->icr);
247 if (msg->condition == I2C_COND_STOP)
248 writel(readl(&base->icr) | ICR_STOP, &base->icr);
249 if (msg->acknack == I2C_ACKNAK_SENDNAK)
250 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
251 if (msg->acknack == I2C_ACKNAK_SENDACK)
252 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
253 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
254 writel(readl(&base->icr) | ICR_TB, &base->icr);
255
256 /* receive register full? */
257 if (!i2c_isr_set_cleared(ISR_IRF, 0))
258 goto transfer_error_receive_timeout;
259
260 msg->data = readl(&base->idbr);
261
262 /* clear 'receive empty' state */
263 writel(readl(&base->isr) | ISR_IRF, &base->isr);
264 break;
265 default:
266 goto transfer_error_illegal_param;
267 }
268
269 return 0;
270
271transfer_error_msg_empty:
272 PRINTD(("i2c_transfer: error: 'msg' is empty\n"));
273 ret = -1; goto i2c_transfer_finish;
274
275transfer_error_transmit_timeout:
276 PRINTD(("i2c_transfer: error: transmit timeout\n"));
277 ret = -2; goto i2c_transfer_finish;
278
279transfer_error_ack_missing:
280 PRINTD(("i2c_transfer: error: ACK missing\n"));
281 ret = -3; goto i2c_transfer_finish;
282
283transfer_error_receive_timeout:
284 PRINTD(("i2c_transfer: error: receive timeout\n"));
285 ret = -4; goto i2c_transfer_finish;
286
287transfer_error_illegal_param:
288 PRINTD(("i2c_transfer: error: illegal parameters\n"));
289 ret = -5; goto i2c_transfer_finish;
290
291transfer_error_bus_busy:
292 PRINTD(("i2c_transfer: error: bus is busy\n"));
293 ret = -6; goto i2c_transfer_finish;
294
295i2c_transfer_finish:
296 PRINTD(("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr)));
297 i2c_reset();
298 return ret;
299}
300
301/* ------------------------------------------------------------------------ */
302/* API Functions */
303/* ------------------------------------------------------------------------ */
304void i2c_init(int speed, int slaveaddr)
305{
306 static u32 init_flag = 1;
307 u32 reg_val;
308
309 if (!init_flag)
310 return;
311 else
312 init_flag = 0;
313#ifdef CONFIG_PXA182X
314 /* switch i2c0/1 address for pxa1826 z3 and later steppings */
315 if (!(cpu_is_pxa1826_z1() || cpu_is_pxa1826_z2())) {
316 reg_val = i2c_regs[0];
317 i2c_regs[0] = i2c_regs[1];
318 i2c_regs[1] = reg_val;
319 }
320#endif
321}
322
323/*
324 * i2c_probe: - Test if a chip answers for a given i2c address
325 *
326 * @chip: address of the chip which is searched for
327 * @return: 0 if a chip was found, -1 otherwhise
328 */
329int i2c_probe(uchar chip)
330{
331 struct i2c_msg msg;
332
333 i2c_reset();
334
335 msg.condition = I2C_COND_START;
336 msg.acknack = I2C_ACKNAK_WAITACK;
337 msg.direction = I2C_WRITE;
338 msg.data = (chip << 1) + 1;
339 if (i2c_transfer(&msg))
340 return -1;
341
342 msg.condition = I2C_COND_STOP;
343 msg.acknack = I2C_ACKNAK_SENDNAK;
344 msg.direction = I2C_READ;
345 msg.data = 0x00;
346 if (i2c_transfer(&msg))
347 return -1;
348
349 return 0;
350}
351
352/*
353 * i2c_read: - Read multiple bytes from an i2c device
354 *
355 * The higher level routines take into account that this function is only
356 * called with len < page length of the device (see configuration file)
357 *
358 * @chip: address of the chip which is to be read
359 * @addr: i2c data address within the chip
360 * @alen: length of the i2c data address (1..2 bytes)
361 * @buffer: where to write the data
362 * @len: how much byte do we want to read
363 * @return: 0 in case of success
364 */
365int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
366{
367 struct i2c_msg msg;
368 u8 addr_bytes[3]; /* lowest...highest byte of data address */
369
370 PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
371 "len=0x%02x)\n", chip, addr, alen, len));
372
373 i2c_reset();
374
375 /* dummy chip address write */
376 PRINTD(("i2c_read: dummy chip address write\n"));
377 msg.condition = I2C_COND_START;
378 msg.acknack = I2C_ACKNAK_WAITACK;
379 msg.direction = I2C_WRITE;
380 msg.data = (chip << 1);
381 msg.data &= 0xFE;
382 if (i2c_transfer(&msg))
383 return -1;
384
385 /*
386 * send memory address bytes;
387 * alen defines how much bytes we have to send.
388 */
389 /*addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); */
390 addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
391 addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
392 addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
393
394 while (--alen >= 0) {
395 PRINTD(("i2c_read: send memory word address byte %1d\n", alen));
396 msg.condition = I2C_COND_NORMAL;
397 msg.acknack = I2C_ACKNAK_WAITACK;
398 msg.direction = I2C_WRITE;
399 msg.data = addr_bytes[alen];
400 if (i2c_transfer(&msg))
401 return -1;
402 }
403
404 /* start read sequence */
405 PRINTD(("i2c_read: start read sequence\n"));
406 msg.condition = I2C_COND_START;
407 msg.acknack = I2C_ACKNAK_WAITACK;
408 msg.direction = I2C_WRITE;
409 msg.data = (chip << 1);
410 msg.data |= 0x01;
411 if (i2c_transfer(&msg))
412 return -1;
413
414 /* read bytes; send NACK at last byte */
415 while (len--) {
416 if (len == 0) {
417 msg.condition = I2C_COND_STOP;
418 msg.acknack = I2C_ACKNAK_SENDNAK;
419 } else {
420 msg.condition = I2C_COND_NORMAL;
421 msg.acknack = I2C_ACKNAK_SENDACK;
422 }
423
424 msg.direction = I2C_READ;
425 msg.data = 0x00;
426 if (i2c_transfer(&msg))
427 return -1;
428
429 *buffer = msg.data;
430 PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",
431 (unsigned int)buffer, *buffer));
432 buffer++;
433 }
434
435 i2c_reset();
436
437 return 0;
438}
439
440/*
441 * i2c_write: - Write multiple bytes to an i2c device
442 *
443 * The higher level routines take into account that this function is only
444 * called with len < page length of the device (see configuration file)
445 *
446 * @chip: address of the chip which is to be written
447 * @addr: i2c data address within the chip
448 * @alen: length of the i2c data address (1..2 bytes)
449 * @buffer: where to find the data to be written
450 * @len: how much byte do we want to read
451 * @return: 0 in case of success
452 */
453int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
454{
455 struct i2c_msg msg;
456 u8 addr_bytes[3]; /* lowest...highest byte of data address */
457
458 PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
459 "len=0x%02x)\n", chip, addr, alen, len));
460
461 i2c_reset();
462
463 /* chip address write */
464 PRINTD(("i2c_write: chip address write\n"));
465 msg.condition = I2C_COND_START;
466 msg.acknack = I2C_ACKNAK_WAITACK;
467 msg.direction = I2C_WRITE;
468 msg.data = (chip << 1);
469 msg.data &= 0xFE;
470 if (i2c_transfer(&msg))
471 return -1;
472
473 /*
474 * send memory address bytes;
475 * alen defines how much bytes we have to send.
476 */
477 addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
478 addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
479 addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
480
481 while (--alen >= 0) {
482 PRINTD(("i2c_write: send memory word address\n"));
483 msg.condition = I2C_COND_NORMAL;
484 msg.acknack = I2C_ACKNAK_WAITACK;
485 msg.direction = I2C_WRITE;
486 msg.data = addr_bytes[alen];
487 if (i2c_transfer(&msg))
488 return -1;
489 }
490
491 /* write bytes; send NACK at last byte */
492 while (len--) {
493 PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",
494 (unsigned int)buffer, *buffer));
495
496 if (len == 0)
497 msg.condition = I2C_COND_STOP;
498 else
499 msg.condition = I2C_COND_NORMAL;
500
501 msg.acknack = I2C_ACKNAK_WAITACK;
502 msg.direction = I2C_WRITE;
503 msg.data = *(buffer++);
504
505 if (i2c_transfer(&msg))
506 return -1;
507 }
508
509 i2c_reset();
510
511 return 0;
512}
513#endif /* CONFIG_HARD_I2C */