b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Basic I2C functions |
| 3 | * |
| 4 | * Copyright (c) 2004 Texas Instruments |
| 5 | * |
| 6 | * This package is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the license found in the file |
| 8 | * named COPYING that should have accompanied this file. |
| 9 | * |
| 10 | * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR |
| 11 | * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED |
| 12 | * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. |
| 13 | * |
| 14 | * Author: Jian Zhang jzhang@ti.com, Texas Instruments |
| 15 | * |
| 16 | * Copyright (c) 2003 Wolfgang Denk, wd@denx.de |
| 17 | * Rewritten to fit into the current U-Boot framework |
| 18 | * |
| 19 | * Adapted for OMAP2420 I2C, r-woodruff2@ti.com |
| 20 | * |
| 21 | * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions |
| 22 | * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4 |
| 23 | * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older |
| 24 | * OMAPs and derivatives as well. The only anticipated exception would |
| 25 | * be the OMAP2420, which shall require driver modification. |
| 26 | * - Rewritten i2c_read to operate correctly with all types of chips |
| 27 | * (old function could not read consistent data from some I2C slaves). |
| 28 | * - Optimized i2c_write. |
| 29 | * - New i2c_probe, performs write access vs read. The old probe could |
| 30 | * hang the system under certain conditions (e.g. unconfigured pads). |
| 31 | * - The read/write/probe functions try to identify unconfigured bus. |
| 32 | * - Status functions now read irqstatus_raw as per TRM guidelines |
| 33 | * (except for OMAP243X and OMAP34XX). |
| 34 | * - Driver now supports up to I2C5 (OMAP5). |
| 35 | */ |
| 36 | |
| 37 | #include <common.h> |
| 38 | #include <i2c.h> |
| 39 | |
| 40 | #include <asm/arch/i2c.h> |
| 41 | #include <asm/io.h> |
| 42 | |
| 43 | #include "omap24xx_i2c.h" |
| 44 | |
| 45 | DECLARE_GLOBAL_DATA_PTR; |
| 46 | |
| 47 | #define I2C_TIMEOUT 1000 |
| 48 | |
| 49 | /* Absolutely safe for status update at 100 kHz I2C: */ |
| 50 | #define I2C_WAIT 200 |
| 51 | |
| 52 | static int wait_for_bb(struct i2c_adapter *adap); |
| 53 | static struct i2c *omap24_get_base(struct i2c_adapter *adap); |
| 54 | static u16 wait_for_event(struct i2c_adapter *adap); |
| 55 | static void flush_fifo(struct i2c_adapter *adap); |
| 56 | |
| 57 | static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) |
| 58 | { |
| 59 | struct i2c *i2c_base = omap24_get_base(adap); |
| 60 | int psc, fsscll, fssclh; |
| 61 | int hsscll = 0, hssclh = 0; |
| 62 | u32 scll, sclh; |
| 63 | int timeout = I2C_TIMEOUT; |
| 64 | |
| 65 | /* Only handle standard, fast and high speeds */ |
| 66 | if ((speed != OMAP_I2C_STANDARD) && |
| 67 | (speed != OMAP_I2C_FAST_MODE) && |
| 68 | (speed != OMAP_I2C_HIGH_SPEED)) { |
| 69 | printf("Error : I2C unsupported speed %d\n", speed); |
| 70 | return; |
| 71 | } |
| 72 | |
| 73 | psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; |
| 74 | psc -= 1; |
| 75 | if (psc < I2C_PSC_MIN) { |
| 76 | printf("Error : I2C unsupported prescalar %d\n", psc); |
| 77 | return; |
| 78 | } |
| 79 | |
| 80 | if (speed == OMAP_I2C_HIGH_SPEED) { |
| 81 | /* High speed */ |
| 82 | |
| 83 | /* For first phase of HS mode */ |
| 84 | fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / |
| 85 | (2 * OMAP_I2C_FAST_MODE); |
| 86 | |
| 87 | fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; |
| 88 | fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; |
| 89 | if (((fsscll < 0) || (fssclh < 0)) || |
| 90 | ((fsscll > 255) || (fssclh > 255))) { |
| 91 | puts("Error : I2C initializing first phase clock\n"); |
| 92 | return; |
| 93 | } |
| 94 | |
| 95 | /* For second phase of HS mode */ |
| 96 | hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); |
| 97 | |
| 98 | hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; |
| 99 | hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; |
| 100 | if (((fsscll < 0) || (fssclh < 0)) || |
| 101 | ((fsscll > 255) || (fssclh > 255))) { |
| 102 | puts("Error : I2C initializing second phase clock\n"); |
| 103 | return; |
| 104 | } |
| 105 | |
| 106 | scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; |
| 107 | sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; |
| 108 | |
| 109 | } else { |
| 110 | /* Standard and fast speed */ |
| 111 | fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); |
| 112 | |
| 113 | fsscll -= I2C_FASTSPEED_SCLL_TRIM; |
| 114 | fssclh -= I2C_FASTSPEED_SCLH_TRIM; |
| 115 | if (((fsscll < 0) || (fssclh < 0)) || |
| 116 | ((fsscll > 255) || (fssclh > 255))) { |
| 117 | puts("Error : I2C initializing clock\n"); |
| 118 | return; |
| 119 | } |
| 120 | |
| 121 | scll = (unsigned int)fsscll; |
| 122 | sclh = (unsigned int)fssclh; |
| 123 | } |
| 124 | |
| 125 | if (readw(&i2c_base->con) & I2C_CON_EN) { |
| 126 | writew(0, &i2c_base->con); |
| 127 | udelay(50000); |
| 128 | } |
| 129 | |
| 130 | writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ |
| 131 | udelay(1000); |
| 132 | |
| 133 | writew(I2C_CON_EN, &i2c_base->con); |
| 134 | while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { |
| 135 | if (timeout <= 0) { |
| 136 | puts("ERROR: Timeout in soft-reset\n"); |
| 137 | return; |
| 138 | } |
| 139 | udelay(1000); |
| 140 | } |
| 141 | |
| 142 | writew(0, &i2c_base->con); |
| 143 | writew(psc, &i2c_base->psc); |
| 144 | writew(scll, &i2c_base->scll); |
| 145 | writew(sclh, &i2c_base->sclh); |
| 146 | |
| 147 | /* own address */ |
| 148 | writew(slaveadd, &i2c_base->oa); |
| 149 | writew(I2C_CON_EN, &i2c_base->con); |
| 150 | #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) |
| 151 | /* |
| 152 | * Have to enable interrupts for OMAP2/3, these IPs don't have |
| 153 | * an 'irqstatus_raw' register and we shall have to poll 'stat' |
| 154 | */ |
| 155 | writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | |
| 156 | I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); |
| 157 | #endif |
| 158 | udelay(1000); |
| 159 | flush_fifo(adap); |
| 160 | writew(0xFFFF, &i2c_base->stat); |
| 161 | } |
| 162 | |
| 163 | static void flush_fifo(struct i2c_adapter *adap) |
| 164 | { |
| 165 | struct i2c *i2c_base = omap24_get_base(adap); |
| 166 | u16 stat; |
| 167 | |
| 168 | /* note: if you try and read data when its not there or ready |
| 169 | * you get a bus error |
| 170 | */ |
| 171 | while (1) { |
| 172 | stat = readw(&i2c_base->stat); |
| 173 | if (stat == I2C_STAT_RRDY) { |
| 174 | readb(&i2c_base->data); |
| 175 | writew(I2C_STAT_RRDY, &i2c_base->stat); |
| 176 | udelay(1000); |
| 177 | } else |
| 178 | break; |
| 179 | } |
| 180 | } |
| 181 | |
| 182 | /* |
| 183 | * i2c_probe: Use write access. Allows to identify addresses that are |
| 184 | * write-only (like the config register of dual-port EEPROMs) |
| 185 | */ |
| 186 | static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) |
| 187 | { |
| 188 | struct i2c *i2c_base = omap24_get_base(adap); |
| 189 | u16 status; |
| 190 | int res = 1; /* default = fail */ |
| 191 | |
| 192 | if (chip == readw(&i2c_base->oa)) |
| 193 | return res; |
| 194 | |
| 195 | /* Wait until bus is free */ |
| 196 | if (wait_for_bb(adap)) |
| 197 | return res; |
| 198 | |
| 199 | /* No data transfer, slave addr only */ |
| 200 | writew(chip, &i2c_base->sa); |
| 201 | /* Stop bit needed here */ |
| 202 | writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | |
| 203 | I2C_CON_STP, &i2c_base->con); |
| 204 | |
| 205 | status = wait_for_event(adap); |
| 206 | |
| 207 | if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { |
| 208 | /* |
| 209 | * With current high-level command implementation, notifying |
| 210 | * the user shall flood the console with 127 messages. If |
| 211 | * silent exit is desired upon unconfigured bus, remove the |
| 212 | * following 'if' section: |
| 213 | */ |
| 214 | if (status == I2C_STAT_XRDY) |
| 215 | printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n", |
| 216 | adap->hwadapnr, status); |
| 217 | |
| 218 | goto pr_exit; |
| 219 | } |
| 220 | |
| 221 | /* Check for ACK (!NAK) */ |
| 222 | if (!(status & I2C_STAT_NACK)) { |
| 223 | res = 0; /* Device found */ |
| 224 | udelay(I2C_WAIT); /* Required by AM335X in SPL */ |
| 225 | /* Abort transfer (force idle state) */ |
| 226 | writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ |
| 227 | udelay(1000); |
| 228 | writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | |
| 229 | I2C_CON_STP, &i2c_base->con); /* STP */ |
| 230 | } |
| 231 | pr_exit: |
| 232 | flush_fifo(adap); |
| 233 | writew(0xFFFF, &i2c_base->stat); |
| 234 | return res; |
| 235 | } |
| 236 | |
| 237 | /* |
| 238 | * i2c_read: Function now uses a single I2C read transaction with bulk transfer |
| 239 | * of the requested number of bytes (note that the 'i2c md' command |
| 240 | * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is |
| 241 | * defined in the board config header, this transaction shall be with |
| 242 | * Repeated Start (Sr) between the address and data phases; otherwise |
| 243 | * Stop-Start (P-S) shall be used (some I2C chips do require a P-S). |
| 244 | * The address (reg offset) may be 0, 1 or 2 bytes long. |
| 245 | * Function now reads correctly from chips that return more than one |
| 246 | * byte of data per addressed register (like TI temperature sensors), |
| 247 | * or that do not need a register address at all (such as some clock |
| 248 | * distributors). |
| 249 | */ |
| 250 | static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, |
| 251 | int alen, uchar *buffer, int len) |
| 252 | { |
| 253 | struct i2c *i2c_base = omap24_get_base(adap); |
| 254 | int i2c_error = 0; |
| 255 | u16 status; |
| 256 | |
| 257 | if (alen < 0) { |
| 258 | puts("I2C read: addr len < 0\n"); |
| 259 | return 1; |
| 260 | } |
| 261 | if (len < 0) { |
| 262 | puts("I2C read: data len < 0\n"); |
| 263 | return 1; |
| 264 | } |
| 265 | if (buffer == NULL) { |
| 266 | puts("I2C read: NULL pointer passed\n"); |
| 267 | return 1; |
| 268 | } |
| 269 | |
| 270 | if (alen > 2) { |
| 271 | printf("I2C read: addr len %d not supported\n", alen); |
| 272 | return 1; |
| 273 | } |
| 274 | |
| 275 | if (addr + len > (1 << 16)) { |
| 276 | puts("I2C read: address out of range\n"); |
| 277 | return 1; |
| 278 | } |
| 279 | |
| 280 | /* Wait until bus not busy */ |
| 281 | if (wait_for_bb(adap)) |
| 282 | return 1; |
| 283 | |
| 284 | /* Zero, one or two bytes reg address (offset) */ |
| 285 | writew(alen, &i2c_base->cnt); |
| 286 | /* Set slave address */ |
| 287 | writew(chip, &i2c_base->sa); |
| 288 | |
| 289 | if (alen) { |
| 290 | /* Must write reg offset first */ |
| 291 | #ifdef CONFIG_I2C_REPEATED_START |
| 292 | /* No stop bit, use Repeated Start (Sr) */ |
| 293 | writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | |
| 294 | I2C_CON_TRX, &i2c_base->con); |
| 295 | #else |
| 296 | /* Stop - Start (P-S) */ |
| 297 | writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | |
| 298 | I2C_CON_TRX, &i2c_base->con); |
| 299 | #endif |
| 300 | /* Send register offset */ |
| 301 | while (1) { |
| 302 | status = wait_for_event(adap); |
| 303 | /* Try to identify bus that is not padconf'd for I2C */ |
| 304 | if (status == I2C_STAT_XRDY) { |
| 305 | i2c_error = 2; |
| 306 | printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n", |
| 307 | adap->hwadapnr, status); |
| 308 | goto rd_exit; |
| 309 | } |
| 310 | if (status == 0 || status & I2C_STAT_NACK) { |
| 311 | i2c_error = 1; |
| 312 | printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", |
| 313 | status); |
| 314 | goto rd_exit; |
| 315 | } |
| 316 | if (alen) { |
| 317 | if (status & I2C_STAT_XRDY) { |
| 318 | alen--; |
| 319 | /* Do we have to use byte access? */ |
| 320 | writeb((addr >> (8 * alen)) & 0xff, |
| 321 | &i2c_base->data); |
| 322 | writew(I2C_STAT_XRDY, &i2c_base->stat); |
| 323 | } |
| 324 | } |
| 325 | if (status & I2C_STAT_ARDY) { |
| 326 | writew(I2C_STAT_ARDY, &i2c_base->stat); |
| 327 | break; |
| 328 | } |
| 329 | } |
| 330 | } |
| 331 | /* Set slave address */ |
| 332 | writew(chip, &i2c_base->sa); |
| 333 | /* Read len bytes from slave */ |
| 334 | writew(len, &i2c_base->cnt); |
| 335 | /* Need stop bit here */ |
| 336 | writew(I2C_CON_EN | I2C_CON_MST | |
| 337 | I2C_CON_STT | I2C_CON_STP, |
| 338 | &i2c_base->con); |
| 339 | |
| 340 | /* Receive data */ |
| 341 | while (1) { |
| 342 | status = wait_for_event(adap); |
| 343 | /* |
| 344 | * Try to identify bus that is not padconf'd for I2C. This |
| 345 | * state could be left over from previous transactions if |
| 346 | * the address phase is skipped due to alen=0. |
| 347 | */ |
| 348 | if (status == I2C_STAT_XRDY) { |
| 349 | i2c_error = 2; |
| 350 | printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n", |
| 351 | adap->hwadapnr, status); |
| 352 | goto rd_exit; |
| 353 | } |
| 354 | if (status == 0 || status & I2C_STAT_NACK) { |
| 355 | i2c_error = 1; |
| 356 | goto rd_exit; |
| 357 | } |
| 358 | if (status & I2C_STAT_RRDY) { |
| 359 | *buffer++ = readb(&i2c_base->data); |
| 360 | writew(I2C_STAT_RRDY, &i2c_base->stat); |
| 361 | } |
| 362 | if (status & I2C_STAT_ARDY) { |
| 363 | writew(I2C_STAT_ARDY, &i2c_base->stat); |
| 364 | break; |
| 365 | } |
| 366 | } |
| 367 | |
| 368 | rd_exit: |
| 369 | flush_fifo(adap); |
| 370 | writew(0xFFFF, &i2c_base->stat); |
| 371 | return i2c_error; |
| 372 | } |
| 373 | |
| 374 | /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ |
| 375 | static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, |
| 376 | int alen, uchar *buffer, int len) |
| 377 | { |
| 378 | struct i2c *i2c_base = omap24_get_base(adap); |
| 379 | int i; |
| 380 | u16 status; |
| 381 | int i2c_error = 0; |
| 382 | |
| 383 | if (alen < 0) { |
| 384 | puts("I2C write: addr len < 0\n"); |
| 385 | return 1; |
| 386 | } |
| 387 | |
| 388 | if (len < 0) { |
| 389 | puts("I2C write: data len < 0\n"); |
| 390 | return 1; |
| 391 | } |
| 392 | |
| 393 | if (buffer == NULL) { |
| 394 | puts("I2C write: NULL pointer passed\n"); |
| 395 | return 1; |
| 396 | } |
| 397 | |
| 398 | if (alen > 2) { |
| 399 | printf("I2C write: addr len %d not supported\n", alen); |
| 400 | return 1; |
| 401 | } |
| 402 | |
| 403 | if (addr + len > (1 << 16)) { |
| 404 | printf("I2C write: address 0x%x + 0x%x out of range\n", |
| 405 | addr, len); |
| 406 | return 1; |
| 407 | } |
| 408 | |
| 409 | /* Wait until bus not busy */ |
| 410 | if (wait_for_bb(adap)) |
| 411 | return 1; |
| 412 | |
| 413 | /* Start address phase - will write regoffset + len bytes data */ |
| 414 | writew(alen + len, &i2c_base->cnt); |
| 415 | /* Set slave address */ |
| 416 | writew(chip, &i2c_base->sa); |
| 417 | /* Stop bit needed here */ |
| 418 | writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | |
| 419 | I2C_CON_STP, &i2c_base->con); |
| 420 | |
| 421 | while (alen) { |
| 422 | /* Must write reg offset (one or two bytes) */ |
| 423 | status = wait_for_event(adap); |
| 424 | /* Try to identify bus that is not padconf'd for I2C */ |
| 425 | if (status == I2C_STAT_XRDY) { |
| 426 | i2c_error = 2; |
| 427 | printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n", |
| 428 | adap->hwadapnr, status); |
| 429 | goto wr_exit; |
| 430 | } |
| 431 | if (status == 0 || status & I2C_STAT_NACK) { |
| 432 | i2c_error = 1; |
| 433 | printf("i2c_write: error waiting for addr ACK (status=0x%x)\n", |
| 434 | status); |
| 435 | goto wr_exit; |
| 436 | } |
| 437 | if (status & I2C_STAT_XRDY) { |
| 438 | alen--; |
| 439 | writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data); |
| 440 | writew(I2C_STAT_XRDY, &i2c_base->stat); |
| 441 | } else { |
| 442 | i2c_error = 1; |
| 443 | printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n", |
| 444 | status); |
| 445 | goto wr_exit; |
| 446 | } |
| 447 | } |
| 448 | /* Address phase is over, now write data */ |
| 449 | for (i = 0; i < len; i++) { |
| 450 | status = wait_for_event(adap); |
| 451 | if (status == 0 || status & I2C_STAT_NACK) { |
| 452 | i2c_error = 1; |
| 453 | printf("i2c_write: error waiting for data ACK (status=0x%x)\n", |
| 454 | status); |
| 455 | goto wr_exit; |
| 456 | } |
| 457 | if (status & I2C_STAT_XRDY) { |
| 458 | writeb(buffer[i], &i2c_base->data); |
| 459 | writew(I2C_STAT_XRDY, &i2c_base->stat); |
| 460 | } else { |
| 461 | i2c_error = 1; |
| 462 | printf("i2c_write: bus not ready for data Tx (i=%d)\n", |
| 463 | i); |
| 464 | goto wr_exit; |
| 465 | } |
| 466 | } |
| 467 | |
| 468 | wr_exit: |
| 469 | flush_fifo(adap); |
| 470 | writew(0xFFFF, &i2c_base->stat); |
| 471 | return i2c_error; |
| 472 | } |
| 473 | |
| 474 | /* |
| 475 | * Wait for the bus to be free by checking the Bus Busy (BB) |
| 476 | * bit to become clear |
| 477 | */ |
| 478 | static int wait_for_bb(struct i2c_adapter *adap) |
| 479 | { |
| 480 | struct i2c *i2c_base = omap24_get_base(adap); |
| 481 | int timeout = I2C_TIMEOUT; |
| 482 | u16 stat; |
| 483 | |
| 484 | writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ |
| 485 | #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) |
| 486 | while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { |
| 487 | #else |
| 488 | /* Read RAW status */ |
| 489 | while ((stat = readw(&i2c_base->irqstatus_raw) & |
| 490 | I2C_STAT_BB) && timeout--) { |
| 491 | #endif |
| 492 | writew(stat, &i2c_base->stat); |
| 493 | udelay(I2C_WAIT); |
| 494 | } |
| 495 | |
| 496 | if (timeout <= 0) { |
| 497 | printf("Timed out in wait_for_bb: status=%04x\n", |
| 498 | stat); |
| 499 | return 1; |
| 500 | } |
| 501 | writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ |
| 502 | return 0; |
| 503 | } |
| 504 | |
| 505 | /* |
| 506 | * Wait for the I2C controller to complete current action |
| 507 | * and update status |
| 508 | */ |
| 509 | static u16 wait_for_event(struct i2c_adapter *adap) |
| 510 | { |
| 511 | struct i2c *i2c_base = omap24_get_base(adap); |
| 512 | u16 status; |
| 513 | int timeout = I2C_TIMEOUT; |
| 514 | |
| 515 | do { |
| 516 | udelay(I2C_WAIT); |
| 517 | #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) |
| 518 | status = readw(&i2c_base->stat); |
| 519 | #else |
| 520 | /* Read RAW status */ |
| 521 | status = readw(&i2c_base->irqstatus_raw); |
| 522 | #endif |
| 523 | } while (!(status & |
| 524 | (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | |
| 525 | I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | |
| 526 | I2C_STAT_AL)) && timeout--); |
| 527 | |
| 528 | if (timeout <= 0) { |
| 529 | printf("Timed out in wait_for_event: status=%04x\n", |
| 530 | status); |
| 531 | /* |
| 532 | * If status is still 0 here, probably the bus pads have |
| 533 | * not been configured for I2C, and/or pull-ups are missing. |
| 534 | */ |
| 535 | printf("Check if pads/pull-ups of bus %d are properly configured\n", |
| 536 | adap->hwadapnr); |
| 537 | writew(0xFFFF, &i2c_base->stat); |
| 538 | status = 0; |
| 539 | } |
| 540 | |
| 541 | return status; |
| 542 | } |
| 543 | |
| 544 | static struct i2c *omap24_get_base(struct i2c_adapter *adap) |
| 545 | { |
| 546 | switch (adap->hwadapnr) { |
| 547 | case 0: |
| 548 | return (struct i2c *)I2C_BASE1; |
| 549 | break; |
| 550 | case 1: |
| 551 | return (struct i2c *)I2C_BASE2; |
| 552 | break; |
| 553 | #if (I2C_BUS_MAX > 2) |
| 554 | case 2: |
| 555 | return (struct i2c *)I2C_BASE3; |
| 556 | break; |
| 557 | #if (I2C_BUS_MAX > 3) |
| 558 | case 3: |
| 559 | return (struct i2c *)I2C_BASE4; |
| 560 | break; |
| 561 | #if (I2C_BUS_MAX > 4) |
| 562 | case 4: |
| 563 | return (struct i2c *)I2C_BASE5; |
| 564 | break; |
| 565 | #endif |
| 566 | #endif |
| 567 | #endif |
| 568 | default: |
| 569 | printf("wrong hwadapnr: %d\n", adap->hwadapnr); |
| 570 | break; |
| 571 | } |
| 572 | return NULL; |
| 573 | } |
| 574 | |
| 575 | #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) |
| 576 | #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED |
| 577 | #endif |
| 578 | #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1) |
| 579 | #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE |
| 580 | #endif |
| 581 | |
| 582 | U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, |
| 583 | omap24_i2c_read, omap24_i2c_write, NULL, |
| 584 | CONFIG_SYS_OMAP24_I2C_SPEED, |
| 585 | CONFIG_SYS_OMAP24_I2C_SLAVE, |
| 586 | 0) |
| 587 | U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, |
| 588 | omap24_i2c_read, omap24_i2c_write, NULL, |
| 589 | CONFIG_SYS_OMAP24_I2C_SPEED1, |
| 590 | CONFIG_SYS_OMAP24_I2C_SLAVE1, |
| 591 | 1) |
| 592 | #if (I2C_BUS_MAX > 2) |
| 593 | #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2) |
| 594 | #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED |
| 595 | #endif |
| 596 | #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2) |
| 597 | #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE |
| 598 | #endif |
| 599 | |
| 600 | U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe, |
| 601 | omap24_i2c_read, omap24_i2c_write, NULL, |
| 602 | CONFIG_SYS_OMAP24_I2C_SPEED2, |
| 603 | CONFIG_SYS_OMAP24_I2C_SLAVE2, |
| 604 | 2) |
| 605 | #if (I2C_BUS_MAX > 3) |
| 606 | #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3) |
| 607 | #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED |
| 608 | #endif |
| 609 | #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3) |
| 610 | #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE |
| 611 | #endif |
| 612 | |
| 613 | U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe, |
| 614 | omap24_i2c_read, omap24_i2c_write, NULL, |
| 615 | CONFIG_SYS_OMAP24_I2C_SPEED3, |
| 616 | CONFIG_SYS_OMAP24_I2C_SLAVE3, |
| 617 | 3) |
| 618 | #if (I2C_BUS_MAX > 4) |
| 619 | #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4) |
| 620 | #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED |
| 621 | #endif |
| 622 | #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4) |
| 623 | #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE |
| 624 | #endif |
| 625 | |
| 626 | U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, |
| 627 | omap24_i2c_read, omap24_i2c_write, NULL, |
| 628 | CONFIG_SYS_OMAP24_I2C_SPEED4, |
| 629 | CONFIG_SYS_OMAP24_I2C_SLAVE4, |
| 630 | 4) |
| 631 | #endif |
| 632 | #endif |
| 633 | #endif |