| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * linux/include/linux/mtd/spinand.h |
| 3 | * |
| 4 | Copyright (c) 2009-2010 Micron Technology, Inc. |
| 5 | |
| 6 | This software is licensed under the terms of the GNU General Public |
| 7 | License version 2, as published by the Free Software Foundation, and |
| 8 | may be copied, distributed, and modified under those terms. |
| 9 | |
| 10 | This program is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | GNU General Public License for more details. |
| 14 | |
| 15 | * Henry Pan <hspan at micron.com> |
| 16 | * |
| 17 | * based on nand.h |
| 18 | */ |
| 19 | #ifndef __LINUX_MTD_SPI_NAND_H |
| 20 | #define __LINUX_MTD_SPI_NAND_H |
| 21 | |
| 22 | /* cmd */ |
| 23 | #define CMD_READ 0x13 |
| 24 | #define CMD_READ_RDM 0x03 |
| 25 | #define CMD_PROG_PAGE_CLRCACHE 0x02 |
| 26 | //#define CMD_PROG_PAGE 0x84 |
| 27 | #define CMD_PROG_PAGE_EXC 0x10 |
| 28 | #define CMD_ERASE_BLK 0xd8 |
| 29 | #define CMD_WR_ENABLE 0x06 |
| 30 | #define CMD_WR_DISABLE 0x04 |
| 31 | #define CMD_READ_ID 0x9f |
| 32 | #define CMD_RESET 0xff |
| 33 | #define CMD_READ_REG 0x0f |
| 34 | #define CMD_WRITE_REG 0x1f |
| 35 | |
| 36 | /* feature/ status reg */ |
| 37 | #define REG_BLOCK_LOCK 0xa0 |
| 38 | #define REG_OTP 0xb0 |
| 39 | #define REG_STATUS 0xc0/* timing */ |
| 40 | |
| 41 | /* status */ |
| 42 | #define STATUS_OIP_MASK 0x01 |
| 43 | #define STATUS_READY 0 << 0 |
| 44 | #define STATUS_BUSY 1 << 0 |
| 45 | |
| 46 | #define STATUS_E_FAIL_MASK 0x04 |
| 47 | #define STATUS_E_FAIL 1 << 2 |
| 48 | |
| 49 | #define STATUS_P_FAIL_MASK 0x08 |
| 50 | #define STATUS_P_FAIL 1 << 3 |
| 51 | |
| 52 | #define STATUS_ECC_MASK 0x30 |
| 53 | #define STATUS_ECC_1BIT_CORRECTED 1 << 4 |
| 54 | #define STATUS_ECC_ERROR 2 << 4 |
| 55 | #define STATUS_ECC_RESERVED 3 << 4 |
| 56 | |
| 57 | |
| 58 | /*ECC enable defines*/ |
| 59 | #define OTP_ECC_MASK 0x10 |
| 60 | #define OTP_ECC_OFF 0 |
| 61 | #define OTP_ECC_ON 1 |
| 62 | |
| 63 | #define ECC_DISABLED |
| 64 | #define ECC_IN_NAND |
| 65 | #define ECC_SOFT |
| 66 | |
| 67 | /* block lock */ |
| 68 | #define BL_ALL_LOCKED 0x38 |
| 69 | #define BL_1_2_LOCKED 0x30 |
| 70 | #define BL_1_4_LOCKED 0x28 |
| 71 | #define BL_1_8_LOCKED 0x20 |
| 72 | #define BL_1_16_LOCKED 0x18 |
| 73 | #define BL_1_32_LOCKED 0x10 |
| 74 | #define BL_1_64_LOCKED 0x08 |
| 75 | #define BL_ALL_UNLOCKED 0 |
| 76 | |
| 77 | struct spinand_info { |
| 78 | struct nand_ecclayout *ecclayout; |
| 79 | struct spi_flash *spi; |
| 80 | void *priv; |
| 81 | }; |
| 82 | |
| 83 | struct nand_state { |
| 84 | uint32_t col; |
| 85 | uint32_t row; |
| 86 | int buf_ptr; |
| 87 | u8 *buf; |
| 88 | }; |
| 89 | |
| 90 | struct spinand_cmd { |
| 91 | u8 cmd; |
| 92 | unsigned n_addr; |
| 93 | u8 addr[3]; |
| 94 | unsigned n_dummy; |
| 95 | unsigned n_tx; |
| 96 | u8 *tx_buf; |
| 97 | unsigned n_rx; |
| 98 | u8 *rx_buf; |
| 99 | }; |
| 100 | |
| 101 | #endif |