b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /*- |
| 2 | * Copyright (c) 2007-2008, Juniper Networks, Inc. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation version 2 of |
| 8 | * the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 18 | * MA 02111-1307 USA |
| 19 | */ |
| 20 | |
| 21 | #include <common.h> |
| 22 | #include <errno.h> |
| 23 | #include <pci.h> |
| 24 | #include <usb.h> |
| 25 | |
| 26 | #include "ehci.h" |
| 27 | |
| 28 | #ifdef CONFIG_PCI_EHCI_DEVICE |
| 29 | static struct pci_device_id ehci_pci_ids[] = { |
| 30 | /* Please add supported PCI EHCI controller ids here */ |
| 31 | {0x1033, 0x00E0}, /* NEC */ |
| 32 | {0x10B9, 0x5239}, /* ULI1575 PCI EHCI module ids */ |
| 33 | {0x12D8, 0x400F}, /* Pericom */ |
| 34 | {0, 0} |
| 35 | }; |
| 36 | #else |
| 37 | static pci_dev_t ehci_find_class(int index) |
| 38 | { |
| 39 | int bus; |
| 40 | int devnum; |
| 41 | pci_dev_t bdf; |
| 42 | uint32_t class; |
| 43 | |
| 44 | for (bus = 0; bus <= pci_last_busno(); bus++) { |
| 45 | for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES-1; devnum++) { |
| 46 | pci_read_config_dword(PCI_BDF(bus, devnum, 0), |
| 47 | PCI_CLASS_REVISION, &class); |
| 48 | if (class >> 16 == 0xffff) |
| 49 | continue; |
| 50 | |
| 51 | for (bdf = PCI_BDF(bus, devnum, 0); |
| 52 | bdf <= PCI_BDF(bus, devnum, |
| 53 | PCI_MAX_PCI_FUNCTIONS - 1); |
| 54 | bdf += PCI_BDF(0, 0, 1)) { |
| 55 | pci_read_config_dword(bdf, PCI_CLASS_REVISION, |
| 56 | &class); |
| 57 | class >>= 8; |
| 58 | /* |
| 59 | * Here be dragons! In case we have multiple |
| 60 | * PCI EHCI controllers, this function will |
| 61 | * be called multiple times as well. This |
| 62 | * function will scan the PCI busses, always |
| 63 | * starting from bus 0, device 0, function 0, |
| 64 | * until it finds an USB controller. The USB |
| 65 | * stack gives us an 'index' of a controller |
| 66 | * that is currently being registered, which |
| 67 | * is a number, starting from 0 and growing |
| 68 | * in ascending order as controllers are added. |
| 69 | * To avoid probing the same controller in tne |
| 70 | * subsequent runs of this function, we will |
| 71 | * skip 'index - 1' detected controllers and |
| 72 | * report the index'th controller. |
| 73 | */ |
| 74 | if (class != PCI_CLASS_SERIAL_USB_EHCI) |
| 75 | continue; |
| 76 | if (index) { |
| 77 | index--; |
| 78 | continue; |
| 79 | } |
| 80 | /* Return index'th controller. */ |
| 81 | return bdf; |
| 82 | } |
| 83 | } |
| 84 | } |
| 85 | |
| 86 | return -ENODEV; |
| 87 | } |
| 88 | #endif |
| 89 | |
| 90 | /* |
| 91 | * Create the appropriate control structures to manage |
| 92 | * a new EHCI host controller. |
| 93 | */ |
| 94 | int ehci_hcd_init(int index, enum usb_init_type init, |
| 95 | struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor) |
| 96 | { |
| 97 | pci_dev_t pdev; |
| 98 | uint32_t cmd; |
| 99 | struct ehci_hccr *hccr; |
| 100 | struct ehci_hcor *hcor; |
| 101 | |
| 102 | #ifdef CONFIG_PCI_EHCI_DEVICE |
| 103 | pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE); |
| 104 | #else |
| 105 | pdev = ehci_find_class(index); |
| 106 | #endif |
| 107 | if (pdev < 0) { |
| 108 | printf("EHCI host controller not found\n"); |
| 109 | return -1; |
| 110 | } |
| 111 | |
| 112 | hccr = (struct ehci_hccr *)pci_map_bar(pdev, |
| 113 | PCI_BASE_ADDRESS_0, PCI_REGION_MEM); |
| 114 | hcor = (struct ehci_hcor *)((uint32_t) hccr + |
| 115 | HC_LENGTH(ehci_readl(&hccr->cr_capbase))); |
| 116 | |
| 117 | debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", |
| 118 | (uint32_t)hccr, (uint32_t)hcor, |
| 119 | (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); |
| 120 | |
| 121 | *ret_hccr = hccr; |
| 122 | *ret_hcor = hcor; |
| 123 | |
| 124 | /* enable busmaster */ |
| 125 | pci_read_config_dword(pdev, PCI_COMMAND, &cmd); |
| 126 | cmd |= PCI_COMMAND_MASTER; |
| 127 | pci_write_config_dword(pdev, PCI_COMMAND, cmd); |
| 128 | return 0; |
| 129 | } |
| 130 | |
| 131 | /* |
| 132 | * Destroy the appropriate control structures corresponding |
| 133 | * the the EHCI host controller. |
| 134 | */ |
| 135 | int ehci_hcd_stop(int index) |
| 136 | { |
| 137 | return 0; |
| 138 | } |