marvell/uboot/include/spi_nand.h

#ifndef _SPI_NAND_H
#define _SPI_NAND_H

#include "spi_flash.h"

#define ENOTSUPP  524

/* feature registers */
#define REG_BLOCK_LOCK		0xa0
#define REG_CFG			0xb0
#define REG_STATUS		0xc0
#define REG_DIE_SELECT		0xd0

/*Configuration register defines*/
#define CFG_QE_MASK		0x01
#define CFG_QE_ENABLE		0x01
#define CFG_ECC_MASK		0X10
#define CFG_ECC_ENABLE		0x10
#define CFG_LOT_MASK		0x20
#define CFG_LOT_ENABLE		0x20
#define CFG_OTP_MASK		0xc2
#define CFG_OTP_ENTER		0x40
#define CFG_OTP_EXIT		0x00
#define CFG_OTP_PROTECT	0xc0
#define CFG_SNOR_ENABLE	0x82

/* block lock */
#define BL_ALL_LOCKED		0x7c
#define BL_U_1_1024_LOCKED		0x08
#define BL_U_1_512_LOCKED		0x10
#define BL_U_1_256_LOCKED		0x18
#define BL_U_1_128_LOCKED		0x20
#define BL_U_1_64_LOCKED		0x28
#define BL_U_1_32_LOCKED		0x30
#define BL_U_1_16_LOCKED		0x38
#define BL_U_1_8_LOCKED		0x40
#define BL_U_1_4_LOCKED		0x48
#define BL_U_1_2_LOCKED		0x50
#define BL_L_1_1024_LOCKED		0x0c
#define BL_L_1_512_LOCKED		0x14
#define BL_L_1_256_LOCKED		0x1c
#define BL_L_1_128_LOCKED		0x24
#define BL_L_1_64_LOCKED		0x2c
#define BL_L_1_32_LOCKED		0x34
#define BL_L_1_16_LOCKED		0x3c
#define BL_L_1_8_LOCKED		0x44
#define BL_L_1_4_LOCKED		0x4c
#define BL_L_1_2_LOCKED		0x54
#define BL_ALL_UNLOCKED		0X00

/* die select */
#define DIE_SELECT_MASK		0x40
#define DIE_SELECT_DS0		0x00
#define DIE_SELECT_DS1		0x40

#define SPI_NAND_ECC_SHIFT	4
#define SPI_NAND_ECC_MASK	0x30
#define SPI_NAND_ECC_0_BIT	0x0
#define SPI_NAND_ECC_1_3_BIT	0x1
#define SPI_NAND_ECC_4_6_BIT	0x3
#define SPI_NAND_ECC_UNCORR	0x2

/*
 * SPI NAND chip options
 * !!! Do not use BIT9, reserved for NAND_SKIP_BBTSCAN !!!
 */
#define SPINAND_NEED_PLANE_SELECT	(1 << 0)
#define SPINAND_NEED_DIE_SELECT	(1 << 1)
#define SPINAND_READ_PAGE_CACHE_RDM	(1 << 2)
#define SPINAND_ECC_TYPE_HRADWARE	(1 << 3)
#define SPINAND_SKIP_BBTSCAN		(1 << 4)
/*
 * If PROGRAM LOAD RANDOM DATA cmd only valid during Internal Data Move,
 * need to send Page Read command to cache first.
 */
#define SPINAND_RDM_CMD_NEED_PAGE_READ	(1 << 5)
#define SPINAND_ECC_EN_ADDR_90H		(1 << 6)
#define SPINAND_SUPPORT_DTR		(1 << 7)
#define SPINAND_NEED_SET_BFT		(1 << 8)

#define SPINAND_MAX_ID_LEN		4

struct spi_nand_info {
	char		*name;
	u8		mfr_id;
	u16		dev_id;
	u32		page_size;
	u32		oob_size;
	u32		pages_per_blk;
	u32		blks_per_lun;
	u32		luns_per_chip;
	u32		ecc_strength;
	u32		options;
	u32		bitflip_threshold;
	u32		tclqv; /* in nanosecond*/
	u32		tset; /* in nanosecond*/
	u32		thold; /* in nanosecond*/
	u32		max_mhz;
	u8		quad_cmd_index;
	u8		quad_cmd_dtr_index;
	struct nand_ecclayout *ecclayout;
	void (*get_ecc_status)(struct spi_flash_chip *chip, u8 status,
				u32 *corrected, u32 *ecc_error);
};

#define SPI_NAND_INFO_DTR(nm, mid, did, pagesz, oobsz, pg_per_blk,\
	blk_per_lun, lun_per_chip, ecc_stren, opts, _bitflip_threshold, \
	_tclqv, _tset, _thold, _max_mhz, _cmd_index, _dtr_index, _ecclayout, _get_ecc_status) \
	{ .name = (nm), .mfr_id = (mid), .dev_id = (did),\
	.page_size = (pagesz), .oob_size = (oobsz),\
	.pages_per_blk = (pg_per_blk), .blks_per_lun = (blk_per_lun),\
	.luns_per_chip = (lun_per_chip),			\
	.ecc_strength = (ecc_stren), .options = (opts),\
	.bitflip_threshold = (_bitflip_threshold), \
	.tclqv = (_tclqv), \
	.tset = (_tset), \
	.thold = (_thold), \
	.max_mhz = (_max_mhz), \
	.quad_cmd_index = (_cmd_index), \
	.quad_cmd_dtr_index = _dtr_index, \
	.ecclayout = (_ecclayout), .get_ecc_status = (_get_ecc_status), }

#define SPI_NAND_INFO(nm, mid, did, pagesz, oobsz, pg_per_blk,\
	blk_per_lun, lun_per_chip, ecc_stren, opts, _bitflip_threshold, \
	_max_mhz, _cmd_index, _ecclayout, _get_ecc_status) \
	SPI_NAND_INFO_DTR(nm, mid, did, pagesz, oobsz, pg_per_blk,\
	blk_per_lun, lun_per_chip, ecc_stren, opts, _bitflip_threshold, \
	0, 0, 0, _max_mhz, _cmd_index, 0, _ecclayout, _get_ecc_status)

#define SPI_NAND_INFO_TIMING(nm, mid, did, pagesz, oobsz, pg_per_blk,\
	blk_per_lun, lun_per_chip, ecc_stren, opts, _bitflip_threshold, \
	_tclqv, _tset, _thold, _max_mhz, _cmd_index, _ecclayout, _get_ecc_status) \
	SPI_NAND_INFO_DTR(nm, mid, did, pagesz, oobsz, pg_per_blk,\
	blk_per_lun, lun_per_chip, ecc_stren, opts, _bitflip_threshold, \
	_tclqv, _tset, _thold, _max_mhz, _cmd_index, 0, _ecclayout, _get_ecc_status)

/**
 * struct mtd_oob_ops - oob operation operands
 * @mode:	operation mode
 * @len:	number of data bytes to write/read
 * @retlen:	number of data bytes written/read
 * @ooblen:	number of oob bytes to write/read
 * @oobretlen:	number of oob bytes written/read
 * @ooboffs:	offset of oob data in the oob area (only relevant when
 *		mode = MTD_OPS_PLACE_OOB or MTD_OPS_RAW)
 * @datbuf:	data buffer - if NULL only oob data are read/written
 * @oobbuf:	oob data buffer
 *
 * Note, it is allowed to read more than one OOB area at one go, but not write.
 * The interface assumes that the OOB write requests program only one page's
 * OOB area.
 */
//struct mtd_oob_ops {
//	unsigned int	mode;
//	u32	len;
//	u32	retlen;
//	u32	ooblen;
//	u32	oobretlen;
//	u32	ooboffs;
//	u8		*datbuf;
//	u8		*oobbuf;
//};

//enum {
//	NORMAL_MODE,
//	OTP_MODE,
//	OTP_PROTECT_MODE,
//	SNOR_READ_ENABLE_MODE,
//};

struct spi_flash_chip *spi_nand_scan_ident(struct mtd_info *mtd);

#endif