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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / package / kernel / mac80211 / patches / rt2x00 / 991-rt2x00-mt7620-differentiate-based-on-SoC-CHIP_VER.patch
blob: a724232c44be7e7c561d7eb2904527b353e59490 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1--- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
2+++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
3@@ -1042,6 +1042,11 @@
4 #define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010)
5 #define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020)
6
7+#define BB_PA_MODE_CFG0 0x1214
8+#define BB_PA_MODE_CFG1 0x1218
9+#define RF_PA_MODE_CFG0 0x121C
10+#define RF_PA_MODE_CFG1 0x1220
11+
12 /*
13 * EDCA_AC0_CFG:
14 */
15--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
16+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
17@@ -3685,14 +3685,16 @@ static void rt2800_config_channel_rf7620
18 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
19 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
20
21- /* Default: XO=20MHz , SDM mode */
22- rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
23- rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
24- rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
25-
26- rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
27- rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
28- rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
29+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
30+ /* Default: XO=20MHz , SDM mode */
31+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
32+ rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
33+ rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
34+
35+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
36+ rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
37+ rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
38+ }
39
40 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
41 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
42@@ -3726,18 +3728,23 @@ static void rt2800_config_channel_rf7620
43 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
44 }
45
46- if (conf_is_ht40(conf)) {
47- rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
48- rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
49- } else {
50- rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
51- rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
52+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
53+ if (conf_is_ht40(conf)) {
54+ rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
55+ rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
56+ } else {
57+ rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
58+ rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
59+ }
60 }
61
62- rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
63- rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
64- conf_is_ht40(conf) && (rf->channel == 11));
65- rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
66+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
67+ rt2800_hw_get_chipeco(rt2x00dev) == 2) {
68+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
69+ rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
70+ conf_is_ht40(conf) && (rf->channel == 11));
71+ rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
72+ }
73
74 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
75 if (conf_is_ht40(conf)) {
76@@ -3837,25 +3844,29 @@ static void rt2800_config_alc(struct rt2
77 if (i == 10000)
78 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
79
80- if (chan->center_freq > 2457) {
81- bbp = rt2800_bbp_read(rt2x00dev, 30);
82- bbp = 0x40;
83- rt2800_bbp_write(rt2x00dev, 30, bbp);
84- rt2800_rfcsr_write(rt2x00dev, 39, 0);
85- if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
86- rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
87- else
88- rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
89- } else {
90- bbp = rt2800_bbp_read(rt2x00dev, 30);
91- bbp = 0x1f;
92- rt2800_bbp_write(rt2x00dev, 30, bbp);
93- rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
94- if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
95- rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
96- else
97- rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
98+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
99+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
100+ if (chan->center_freq > 2457) {
101+ bbp = rt2800_bbp_read(rt2x00dev, 30);
102+ bbp = 0x40;
103+ rt2800_bbp_write(rt2x00dev, 30, bbp);
104+ rt2800_rfcsr_write(rt2x00dev, 39, 0);
105+ if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
106+ rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
107+ else
108+ rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
109+ } else {
110+ bbp = rt2800_bbp_read(rt2x00dev, 30);
111+ bbp = 0x1f;
112+ rt2800_bbp_write(rt2x00dev, 30, bbp);
113+ rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
114+ if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
115+ rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
116+ else
117+ rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
118+ }
119 }
120+
121 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
122
123 rt2800_vco_calibration(rt2x00dev);
124@@ -5892,18 +5903,33 @@ static int rt2800_init_registers(struct
125 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
126 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
127 } else if (rt2x00_rt(rt2x00dev, RT6352)) {
128- rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
129- rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
130- rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
131- rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
132- rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
133- rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
134- rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
135- rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
136- rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
137- 0x3630363A);
138- rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
139- 0x3630363A);
140+ if (rt2800_hw_get_chipver(rt2x00dev) <= 1) {
141+ rt2800_register_write(rt2x00dev, TX_ALC_VGA3,
142+ 0x00000000);
143+ rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG0,
144+ 0x000055FF);
145+ rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG1,
146+ 0x00550055);
147+ rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG0,
148+ 0x000055FF);
149+ rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG1,
150+ 0x00550055);
151+ } else {
152+ rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
153+ rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
154+ rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
155+ rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
156+ rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
157+ rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
158+ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
159+ 0x6C6C666C);
160+ rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
161+ 0x6C6C666C);
162+ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
163+ 0x3630363A);
164+ rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
165+ 0x3630363A);
166+ }
167 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
168 rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
169 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
170@@ -7068,14 +7094,16 @@ static void rt2800_init_bbp_6352(struct
171 rt2800_bbp_write(rt2x00dev, 188, 0x00);
172 rt2800_bbp_write(rt2x00dev, 189, 0x00);
173
174- rt2800_bbp_write(rt2x00dev, 91, 0x06);
175- rt2800_bbp_write(rt2x00dev, 92, 0x04);
176- rt2800_bbp_write(rt2x00dev, 93, 0x54);
177- rt2800_bbp_write(rt2x00dev, 99, 0x50);
178- rt2800_bbp_write(rt2x00dev, 148, 0x84);
179- rt2800_bbp_write(rt2x00dev, 167, 0x80);
180- rt2800_bbp_write(rt2x00dev, 178, 0xFF);
181- rt2800_bbp_write(rt2x00dev, 106, 0x13);
182+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
183+ rt2800_bbp_write(rt2x00dev, 91, 0x06);
184+ rt2800_bbp_write(rt2x00dev, 92, 0x04);
185+ rt2800_bbp_write(rt2x00dev, 93, 0x54);
186+ rt2800_bbp_write(rt2x00dev, 99, 0x50);
187+ rt2800_bbp_write(rt2x00dev, 148, 0x84);
188+ rt2800_bbp_write(rt2x00dev, 167, 0x80);
189+ rt2800_bbp_write(rt2x00dev, 178, 0xFF);
190+ rt2800_bbp_write(rt2x00dev, 106, 0x13);
191+ }
192
193 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
194 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
195@@ -10414,31 +10442,36 @@ static void rt2800_init_rfcsr_6352(struc
196 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
197 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
198
199- rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
200- if (rt2800_clk_is_20mhz(rt2x00dev))
201- rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
202- else
203- rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
204- rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
205- rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
206- rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
207- rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
208- rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
209- rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
210- rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
211- rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
212- rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
213- rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
214- rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
215- rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
216- rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
217- rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
218- rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
219- rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
220-
221- rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
222- rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
223- rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
224+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
225+ rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
226+ if (rt2800_clk_is_20mhz(rt2x00dev))
227+ rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
228+ else
229+ rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
230+ rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
231+ rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
232+ rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
233+ rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
234+ rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
235+ rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
236+ rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
237+ rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
238+ rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
239+ rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
240+ rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
241+ rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
242+ rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
243+ rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
244+ rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
245+ rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
246+ }
247+
248+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
249+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
250+ rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
251+ rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
252+ rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
253+ }
254
255 /* Initialize RF channel register to default value */
256 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
257@@ -10504,63 +10537,71 @@ static void rt2800_init_rfcsr_6352(struc
258
259 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
260
261- rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
262- rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
263- rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
264- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
265- rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
266- rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
267- rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
268- rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
269- rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
270- rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
271- rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
272- rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
273- rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
274- rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
275- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
276- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
277- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
278- rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
279- rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
280- rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
281- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
282- rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
283- rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
284- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
285- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
286- rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
287- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
288- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
289- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
290- rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
291-
292- rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
293- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
294- rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
295- rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
296- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
297- rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
298- rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
299- rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
300- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
301-
302- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
303- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
304- rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
305- rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
306- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
307- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
308-
309- /* Initialize RF channel register for DRQFN */
310- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
311- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
312- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
313- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
314- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
315- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
316- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
317- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
318+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
319+ rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
320+ rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
321+ rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
322+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
323+ rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
324+ rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
325+ rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
326+ rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
327+ rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
328+ rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
329+ rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
330+ rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
331+ rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
332+ rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
333+ rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
334+ rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
335+ rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
336+ rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
337+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
338+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
339+ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
340+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
341+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
342+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
343+ rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
344+ rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
345+ rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
346+ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
347+ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
348+ rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
349+ }
350+
351+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
352+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
353+ rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
354+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
355+ rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
356+ rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
357+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
358+ rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
359+ rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
360+ rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
361+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
362+
363+ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
364+ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
365+ rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
366+ rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
367+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
368+ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
369+ }
370+
371+ if (rt2800_hw_get_chippkg(rt2x00dev) == 0 &&
372+ rt2800_hw_get_chipver(rt2x00dev) == 1) {
373+ /* Initialize RF channel register for DRQFN */
374+ rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
375+ rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
376+ rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
377+ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
378+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
379+ rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
380+ rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
381+ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
382+ }
383
384 /* Initialize RF DC calibration register to default value */
385 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
386@@ -10623,12 +10664,17 @@ static void rt2800_init_rfcsr_6352(struc
387 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
388 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
389
390- rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
391- rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
392- rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
393+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
394+ rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
395+ rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
396+ rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
397+ }
398
399- rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
400- rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
401+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
402+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
403+ rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
404+ rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
405+ }
406
407 rt2800_r_calibration(rt2x00dev);
408 rt2800_rf_self_txdc_cal(rt2x00dev);