b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /*++
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| 2 | Copyright (c) Realtek Semiconductor Corp. All rights reserved.
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| 3 |
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| 4 | Module Name:
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| 5 | HalPwrSeqCmd.c
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| 6 |
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| 7 | Abstract:
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| 8 | Implement HW Power sequence configuration CMD handling routine for Realtek devices.
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| 9 |
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| 10 | Major Change History:
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| 11 | When Who What
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| 12 | ---------- --------------- -------------------------------
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| 13 | 2011-07-07 Roger Create.
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| 14 |
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| 15 | --*/
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| 16 | #ifdef __ECOS
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| 17 | #include <cyg/io/eth/rltk/819x/wrapper/sys_support.h>
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| 18 | #include <cyg/io/eth/rltk/819x/wrapper/skbuff.h>
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| 19 | #include <cyg/io/eth/rltk/819x/wrapper/timer.h>
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| 20 | #include <cyg/io/eth/rltk/819x/wrapper/wrapper.h>
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| 21 | #endif
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| 22 |
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| 23 |
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| 24 | /*
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| 25 | #if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE)
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| 26 | #include "mp_precomp.h"
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| 27 | #else
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| 28 | #include "../mp_precomp.h"
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| 29 | #endif
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| 30 | */
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| 31 | #ifdef __KERNEL__
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| 32 | #include <linux/kernel.h>
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| 33 | #endif
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| 34 | #include "8192cd.h"
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| 35 | #include "8192cd_debug.h"
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| 36 | #include "8192cd_headers.h"
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| 37 | #include "8192cd_util.h"
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| 38 |
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| 39 | #if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_RTL_8812_SUPPORT) || defined(CONFIG_RTL_8723B_SUPPORT)
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| 40 |
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| 41 | #define TRUE 1
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| 42 | #define FALSE 0
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| 43 |
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| 44 | //
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| 45 | // Description:
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| 46 | // This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
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| 47 | //
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| 48 | // Assumption:
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| 49 | // We should follow specific format which was released from HW SD.
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| 50 | //
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| 51 | // 2011.07.07, added by Roger.
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| 52 | //
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| 53 | unsigned int HalPwrSeqCmdParsing(struct rtl8192cd_priv *priv, unsigned char CutVersion, unsigned char FabVersion,
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| 54 | unsigned char InterfaceType, WLAN_PWR_CFG PwrSeqCmd[])
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| 55 | {
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| 56 |
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| 57 | WLAN_PWR_CFG PwrCfgCmd = {0};
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| 58 | unsigned int bPollingBit = FALSE;
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| 59 | unsigned int AryIdx=0;
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| 60 | unsigned char value = 0;
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| 61 | unsigned int offset = 0;
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| 62 | unsigned int pollingCount = 0; // polling autoload done.
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| 63 | unsigned int maxPollingCnt = 5000;
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| 64 | unsigned int round = 0;
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| 65 |
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| 66 | do {
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| 67 | PwrCfgCmd=PwrSeqCmd[AryIdx];
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| 68 |
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| 69 | DEBUG_INFO("%s %d, ENTRY, offset:0x%x, cut_msk:0x%x, fab_msk:0x%x, if_msk:0x%x, base:0x%x, cmd:0x%x, msk:0x%x, value:0x%x\n",
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| 70 | __FUNCTION__, __LINE__, GET_PWR_CFG_OFFSET(PwrCfgCmd), GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
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| 71 | GET_PWR_CFG_FAB_MASK(PwrCfgCmd), GET_PWR_CFG_INTF_MASK(PwrCfgCmd), GET_PWR_CFG_BASE(PwrCfgCmd),
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| 72 | GET_PWR_CFG_CMD(PwrCfgCmd), GET_PWR_CFG_MASK(PwrCfgCmd), GET_PWR_CFG_VALUE(PwrCfgCmd));
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| 73 |
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| 74 | //2 Only Handle the command whose FAB, CUT, and Interface are matched
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| 75 | if((GET_PWR_CFG_FAB_MASK(PwrCfgCmd)&FabVersion)&&
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| 76 | (GET_PWR_CFG_CUT_MASK(PwrCfgCmd)&CutVersion)&&
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| 77 | (GET_PWR_CFG_INTF_MASK(PwrCfgCmd)&InterfaceType)) {
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| 78 | switch(GET_PWR_CFG_CMD(PwrCfgCmd))
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| 79 | {
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| 80 | case PWR_CMD_READ:
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| 81 | DEBUG_INFO("%s %d, PWR_CMD_READ\n", __FUNCTION__, __LINE__);
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| 82 | break;
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| 83 |
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| 84 | case PWR_CMD_WRITE:
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| 85 | DEBUG_INFO("%s %d, PWR_CMD_WRITE\n", __FUNCTION__, __LINE__);
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| 86 | offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
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| 87 |
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| 88 | #ifdef CONFIG_SDIO_HCI
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| 89 | //
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| 90 | // <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
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| 91 | // 2011.07.07.
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| 92 | //
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| 93 | if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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| 94 | {
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| 95 | // Read Back SDIO Local value
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| 96 | value = SdioLocalCmd52Read1Byte(priv, offset);
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| 97 |
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| 98 | value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
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| 99 | value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
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| 100 |
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| 101 | // Write Back SDIO Local value
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| 102 | SdioLocalCmd52Write1Byte(priv, offset, value);
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| 103 | }
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| 104 | else
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| 105 | #endif
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| 106 | {
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| 107 | //Read the value from system register
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| 108 | value = RTL_R8(offset);
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| 109 | value = value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
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| 110 | value = value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));
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| 111 |
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| 112 | //Write the value back to sytem register
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| 113 | RTL_W8(offset, value);
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| 114 | }
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| 115 | break;
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| 116 |
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| 117 | case PWR_CMD_POLLING:
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| 118 | DEBUG_INFO("%s %d, PWR_CMD_POLLING\n", __FUNCTION__, __LINE__);
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| 119 | bPollingBit = FALSE;
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| 120 | offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
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| 121 |
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| 122 | do {
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| 123 | #ifdef CONFIG_SDIO_HCI
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| 124 | if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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| 125 | value = SdioLocalCmd52Read1Byte(priv, offset);
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| 126 | else
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| 127 | #endif
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| 128 | value = RTL_R8(offset);
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| 129 | value=value&GET_PWR_CFG_MASK(PwrCfgCmd);
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| 130 | if(value==(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd)))
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| 131 | bPollingBit=TRUE;
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| 132 | else
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| 133 | delay_us(10);
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| 134 |
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| 135 | if(pollingCount++ > maxPollingCnt){
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| 136 | DEBUG_WARN("%s %d, PWR_CMD_POLLING, Fail to polling Offset[0x%x]\n", __FUNCTION__, __LINE__, offset);
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| 137 | return FALSE;
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| 138 | }
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| 139 | }while(!bPollingBit);
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| 140 |
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| 141 | break;
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| 142 |
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| 143 | case PWR_CMD_DELAY:
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| 144 | DEBUG_INFO("%s %d, PWR_CMD_DELAY\n", __FUNCTION__, __LINE__);
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| 145 | if(GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
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| 146 | delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd));
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| 147 | else
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| 148 | delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
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| 149 | break;
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| 150 |
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| 151 | case PWR_CMD_END:
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| 152 | // When this command is parsed, end the process
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| 153 | DEBUG_INFO("%s %d, PWR_CMD_END\n", __FUNCTION__, __LINE__);
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| 154 | return TRUE;
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| 155 | break;
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| 156 |
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| 157 | default:
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| 158 | DEBUG_ERR("%s %d, Unknown CMD!!\n", __FUNCTION__, __LINE__);
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| 159 | break;
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| 160 | }
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| 161 |
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| 162 | }
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| 163 |
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| 164 | AryIdx++;//Add Array Index
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| 165 |
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| 166 | if (++round > 10000) {
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| 167 | panic_printk("%s[%d] while (1) goes too many\n", __FUNCTION__, __LINE__);
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| 168 | break;
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| 169 | }
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| 170 | }while(1);
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| 171 |
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| 172 | return TRUE;
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| 173 | }
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| 174 | #endif
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| 175 |
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