b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards |
| 3 | * |
| 4 | * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <stddef.h> |
| 12 | #include "config.h" |
| 13 | #include "ar71xx_regs.h" |
| 14 | |
| 15 | #define READREG(r) *(volatile unsigned int *)(r) |
| 16 | #define WRITEREG(r,v) *(volatile unsigned int *)(r) = v |
| 17 | |
| 18 | #define KSEG1ADDR(_x) (((_x) & 0x1fffffff) | 0xa0000000) |
| 19 | |
| 20 | #define UART_BASE 0xb8020000 |
| 21 | |
| 22 | #define UART_TX 0 |
| 23 | #define UART_LSR 5 |
| 24 | |
| 25 | #define UART_LSR_THRE 0x20 |
| 26 | |
| 27 | #define UART_READ(r) READREG(UART_BASE + 4 * (r)) |
| 28 | #define UART_WRITE(r,v) WRITEREG(UART_BASE + 4 * (r), (v)) |
| 29 | |
| 30 | void board_putc(int ch) |
| 31 | { |
| 32 | while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); |
| 33 | UART_WRITE(UART_TX, ch); |
| 34 | while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); |
| 35 | } |
| 36 | |
| 37 | #ifdef CONFIG_BOARD_TL_WR1043ND_V1 |
| 38 | static void tlwr1043nd_init(void) |
| 39 | { |
| 40 | unsigned int reg = KSEG1ADDR(AR71XX_RESET_BASE); |
| 41 | unsigned int t; |
| 42 | |
| 43 | t = READREG(reg + AR913X_RESET_REG_RESET_MODULE); |
| 44 | t |= AR71XX_RESET_GE0_PHY; |
| 45 | WRITEREG(reg + AR913X_RESET_REG_RESET_MODULE, t); |
| 46 | /* flush write */ |
| 47 | t = READREG(reg + AR913X_RESET_REG_RESET_MODULE); |
| 48 | } |
| 49 | #else |
| 50 | static inline void tlwr1043nd_init(void) {} |
| 51 | #endif |
| 52 | |
| 53 | void board_init(void) |
| 54 | { |
| 55 | tlwr1043nd_init(); |
| 56 | } |