blob: 0106470d9350ee8cc10f78ad55aa129e5f266717 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001From 110cf6bdc1d79f2ee7a435bc9d1ec900aba11ed5 Mon Sep 17 00:00:00 2001
2From: Maxime Ripard <maxime@cerno.tech>
3Date: Thu, 26 Dec 2019 18:41:53 +0100
4Subject: [PATCH] drm/vc4: hdmi: Add a CSC setup callback
5
6Similarly to the previous patches, the CSC setup is slightly different in
7the BCM2711 than in the previous generations. Let's add a callback for it.
8
9Signed-off-by: Maxime Ripard <maxime@cerno.tech>
10---
11 drivers/gpu/drm/vc4/vc4_hdmi.c | 71 ++++++++++++++++++++--------------
12 drivers/gpu/drm/vc4/vc4_hdmi.h | 3 ++
13 2 files changed, 45 insertions(+), 29 deletions(-)
14
15--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
16+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
17@@ -337,6 +337,41 @@ static void vc4_hdmi_encoder_disable(str
18 DRM_ERROR("Failed to release power domain: %d\n", ret);
19 }
20
21+static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
22+{
23+ u32 csc_ctl;
24+
25+ csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
26+ VC4_HD_CSC_CTL_ORDER);
27+
28+ if (enable) {
29+ /* CEA VICs other than #1 requre limited range RGB
30+ * output unless overridden by an AVI infoframe.
31+ * Apply a colorspace conversion to squash 0-255 down
32+ * to 16-235. The matrix here is:
33+ *
34+ * [ 0 0 0.8594 16]
35+ * [ 0 0.8594 0 16]
36+ * [ 0.8594 0 0 16]
37+ * [ 0 0 0 1]
38+ */
39+ csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
40+ csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
41+ csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
42+ VC4_HD_CSC_CTL_MODE);
43+
44+ HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
45+ HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
46+ HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
47+ HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
48+ HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
49+ HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
50+ }
51+
52+ /* The RGB order applies even when CSC is disabled. */
53+ HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
54+}
55+
56 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
57 {
58 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
59@@ -360,7 +395,6 @@ static void vc4_hdmi_encoder_enable(stru
60 mode->crtc_vsync_end -
61 interlaced,
62 VC4_HDMI_VERTB_VBP));
63- u32 csc_ctl;
64 int ret;
65
66 ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
67@@ -431,41 +465,19 @@ static void vc4_hdmi_encoder_enable(stru
68 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
69 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
70
71- csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
72- VC4_HD_CSC_CTL_ORDER);
73-
74 if (vc4_encoder->hdmi_monitor &&
75- drm_default_rgb_quant_range(mode) ==
76- HDMI_QUANTIZATION_RANGE_LIMITED) {
77- /* CEA VICs other than #1 requre limited range RGB
78- * output unless overridden by an AVI infoframe.
79- * Apply a colorspace conversion to squash 0-255 down
80- * to 16-235. The matrix here is:
81- *
82- * [ 0 0 0.8594 16]
83- * [ 0 0.8594 0 16]
84- * [ 0.8594 0 0 16]
85- * [ 0 0 0 1]
86- */
87- csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
88- csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
89- csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
90- VC4_HD_CSC_CTL_MODE);
91+ drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
92+ if (vc4_hdmi->variant->csc_setup)
93+ vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
94
95- HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
96- HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
97- HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
98- HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
99- HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
100- HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
101 vc4_encoder->limited_rgb_range = true;
102 } else {
103+ if (vc4_hdmi->variant->csc_setup)
104+ vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
105+
106 vc4_encoder->limited_rgb_range = false;
107 }
108
109- /* The RGB order applies even when CSC is disabled. */
110- HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
111-
112 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
113
114 if (debug_dump_regs) {
115@@ -1427,6 +1439,7 @@ static const struct vc4_hdmi_variant bcm
116 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
117
118 .init_resources = vc4_hdmi_init_resources,
119+ .csc_setup = vc4_hdmi_csc_setup,
120 .reset = vc4_hdmi_reset,
121 .phy_init = vc4_hdmi_phy_init,
122 .phy_disable = vc4_hdmi_phy_disable,
123--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
124+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
125@@ -41,6 +41,9 @@ struct vc4_hdmi_variant {
126 /* Callback to reset the HDMI block */
127 void (*reset)(struct vc4_hdmi *vc4_hdmi);
128
129+ /* Callback to enable / disable the CSC */
130+ void (*csc_setup)(struct vc4_hdmi *vc4_hdmi, bool enable);
131+
132 /* Callback to initialize the PHY according to the mode */
133 void (*phy_init)(struct vc4_hdmi *vc4_hdmi,
134 struct drm_display_mode *mode);