blob: 22f1aa674253ce0c08282b726d8cfc790c4c9bb9 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001From cd72d75cfb216a7ef15ec8649e57b03b4fc48b62 Mon Sep 17 00:00:00 2001
2From: Maxime Ripard <maxime@cerno.tech>
3Date: Wed, 27 May 2020 11:13:52 +0200
4Subject: [PATCH] clk: bcm: rpi: Use CCF boundaries instead of
5 rolling our own
6
7The raspberrypi firmware clock driver has a min_rate / max_rate clamping by
8storing the info it needs in a private structure.
9
10However, the CCF already provides such a facility, so we can switch to it
11to remove the boilerplate.
12
13Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
14Signed-off-by: Maxime Ripard <maxime@cerno.tech>
15---
16 drivers/clk/bcm/clk-raspberrypi.c | 49 ++++++++++++++++++++-----------
17 1 file changed, 32 insertions(+), 17 deletions(-)
18
19--- a/drivers/clk/bcm/clk-raspberrypi.c
20+++ b/drivers/clk/bcm/clk-raspberrypi.c
21@@ -57,9 +57,6 @@ struct raspberrypi_clk_data {
22 struct clk_hw hw;
23 unsigned id;
24
25- unsigned long min_rate;
26- unsigned long max_rate;
27-
28 struct raspberrypi_clk *rpi;
29 };
30
31@@ -177,13 +174,11 @@ static int raspberrypi_fw_pll_set_rate(s
32 static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
33 struct clk_rate_request *req)
34 {
35- struct raspberrypi_clk_data *data =
36- container_of(hw, struct raspberrypi_clk_data, hw);
37 u64 div, final_rate;
38 u32 ndiv, fdiv;
39
40 /* We can't use req->rate directly as it would overflow */
41- final_rate = clamp(req->rate, data->min_rate, data->max_rate);
42+ final_rate = clamp(req->rate, req->min_rate, req->max_rate);
43
44 div = (u64)final_rate << A2W_PLL_FRAC_BITS;
45 do_div(div, req->best_parent_rate);
46@@ -254,16 +249,15 @@ static struct clk_hw *raspberrypi_regist
47 dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
48 min_rate, max_rate);
49
50- data->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
51- data->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
52-
53 data->hw.init = &init;
54
55 ret = devm_clk_hw_register(rpi->dev, &data->hw);
56- if (ret)
57- return ERR_PTR(ret);
58+ if (!ret)
59+ clk_hw_set_rate_range(&data->hw,
60+ min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE,
61+ max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE);
62
63- return &data->hw;
64+ return ret;
65 }
66
67 static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {
68@@ -299,22 +293,22 @@ static struct clk_hw *raspberrypi_regist
69 return &raspberrypi_clk_pllb_arm.hw;
70 }
71
72-static long raspberrypi_fw_dumb_round_rate(struct clk_hw *hw,
73- unsigned long rate,
74- unsigned long *parent_rate)
75+static int raspberrypi_fw_dumb_determine_rate(struct clk_hw *hw,
76+ struct clk_rate_request *req)
77 {
78 /*
79 * The firmware will do the rounding but that isn't part of
80 * the interface with the firmware, so we just do our best
81 * here.
82 */
83- return rate;
84+ req->rate = clamp(req->rate, req->min_rate, req->max_rate);
85+ return 0;
86 }
87
88 static const struct clk_ops raspberrypi_firmware_clk_ops = {
89 .is_prepared = raspberrypi_fw_is_prepared,
90 .recalc_rate = raspberrypi_fw_get_rate,
91- .round_rate = raspberrypi_fw_dumb_round_rate,
92+ .determine_rate = raspberrypi_fw_dumb_determine_rate,
93 .set_rate = raspberrypi_fw_set_rate,
94 };
95
96@@ -324,6 +318,7 @@ static struct clk_hw *raspberrypi_clk_re
97 {
98 struct raspberrypi_clk_data *data;
99 struct clk_init_data init = {};
100+ u32 min_rate, max_rate;
101 int ret;
102
103 if (id == RPI_FIRMWARE_ARM_CLK_ID) {
104@@ -351,10 +346,30 @@ static struct clk_hw *raspberrypi_clk_re
105
106 data->hw.init = &init;
107
108+ ret = raspberrypi_clock_property(rpi->firmware, data,
109+ RPI_FIRMWARE_GET_MIN_CLOCK_RATE,
110+ &min_rate);
111+ if (ret) {
112+ dev_err(rpi->dev, "Failed to get %s min freq: %d\n",
113+ init.name, ret);
114+ return ERR_PTR(ret);
115+ }
116+
117+ ret = raspberrypi_clock_property(rpi->firmware, data,
118+ RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
119+ &max_rate);
120+ if (ret) {
121+ dev_err(rpi->dev, "Failed to get %s max freq: %d\n",
122+ init.name, ret);
123+ return ERR_PTR(ret);
124+ }
125+
126 ret = devm_clk_hw_register(rpi->dev, &data->hw);
127 if (ret)
128 return ERR_PTR(ret);
129
130+ clk_hw_set_rate_range(&data->hw, min_rate, max_rate);
131+
132 return &data->hw;
133 }
134