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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / target / linux / bcm4908 / patches-5.4 / 040-v6.4-0001-arm64-dts-broadcom-bcmbca-Add-spi-controller-node.patch
blob: e8e122817931e8b67b1dfb953374f58e9161a571 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1From f5d83b714e304d5f3229da434af2eeea033c4f5d Mon Sep 17 00:00:00 2001
2From: William Zhang <william.zhang@broadcom.com>
3Date: Mon, 6 Feb 2023 22:58:15 -0800
4Subject: [PATCH] arm64: dts: broadcom: bcmbca: Add spi controller node
5
6Add support for HSSPI controller in ARMv8 chip dts files.
7
8Signed-off-by: William Zhang <william.zhang@broadcom.com>
9Link: https://lore.kernel.org/r/20230207065826.285013-5-william.zhang@broadcom.com
10Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
11---
12 .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 18 +++++++++++++++++
13 .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 20 +++++++++++++++++++
14 .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 19 ++++++++++++++++++
15 .../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 19 ++++++++++++++++++
16 .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 20 +++++++++++++++++++
17 .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 18 +++++++++++++++++
18 .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 18 +++++++++++++++++
19 .../boot/dts/broadcom/bcmbca/bcm94908.dts | 4 ++++
20 .../boot/dts/broadcom/bcmbca/bcm94912.dts | 4 ++++
21 .../boot/dts/broadcom/bcmbca/bcm963146.dts | 4 ++++
22 .../boot/dts/broadcom/bcmbca/bcm963158.dts | 4 ++++
23 .../boot/dts/broadcom/bcmbca/bcm96813.dts | 4 ++++
24 .../boot/dts/broadcom/bcmbca/bcm96856.dts | 4 ++++
25 .../boot/dts/broadcom/bcmbca/bcm96858.dts | 4 ++++
26 14 files changed, 160 insertions(+)
27
28--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
29+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
30@@ -107,6 +107,12 @@
31 clock-frequency = <50000000>;
32 clock-output-names = "periph";
33 };
34+
35+ hsspi_pll: hsspi-pll {
36+ compatible = "fixed-clock";
37+ #clock-cells = <0>;
38+ clock-frequency = <400000000>;
39+ };
40 };
41
42 soc {
43@@ -531,6 +537,18 @@
44 #size-cells = <0>;
45 };
46
47+ hsspi: spi@1000{
48+ #address-cells = <1>;
49+ #size-cells = <0>;
50+ compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";
51+ reg = <0x1000 0x600>;
52+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
53+ clocks = <&hsspi_pll &hsspi_pll>;
54+ clock-names = "hsspi", "pll";
55+ num-cs = <8>;
56+ status = "disabled";
57+ };
58+
59 nand-controller@1800 {
60 #address-cells = <1>;
61 #size-cells = <0>;
62--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
63+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
64@@ -79,6 +79,7 @@
65 #clock-cells = <0>;
66 clock-frequency = <200000000>;
67 };
68+
69 uart_clk: uart-clk {
70 compatible = "fixed-factor-clock";
71 #clock-cells = <0>;
72@@ -86,6 +87,12 @@
73 clock-div = <4>;
74 clock-mult = <1>;
75 };
76+
77+ hsspi_pll: hsspi-pll {
78+ compatible = "fixed-clock";
79+ #clock-cells = <0>;
80+ clock-frequency = <200000000>;
81+ };
82 };
83
84 psci {
85@@ -117,6 +124,19 @@
86 #size-cells = <1>;
87 ranges = <0x0 0x0 0xff800000 0x800000>;
88
89+ hsspi: spi@1000 {
90+ #address-cells = <1>;
91+ #size-cells = <0>;
92+ compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";
93+ reg = <0x1000 0x600>, <0x2610 0x4>;
94+ reg-names = "hsspi", "spim-ctrl";
95+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
96+ clocks = <&hsspi_pll &hsspi_pll>;
97+ clock-names = "hsspi", "pll";
98+ num-cs = <8>;
99+ status = "disabled";
100+ };
101+
102 uart0: serial@12000 {
103 compatible = "arm,pl011", "arm,primecell";
104 reg = <0x12000 0x1000>;
105--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
106+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
107@@ -60,6 +60,7 @@
108 #clock-cells = <0>;
109 clock-frequency = <200000000>;
110 };
111+
112 uart_clk: uart-clk {
113 compatible = "fixed-factor-clock";
114 #clock-cells = <0>;
115@@ -67,6 +68,12 @@
116 clock-div = <4>;
117 clock-mult = <1>;
118 };
119+
120+ hsspi_pll: hsspi-pll {
121+ compatible = "fixed-clock";
122+ #clock-cells = <0>;
123+ clock-frequency = <200000000>;
124+ };
125 };
126
127 psci {
128@@ -99,6 +106,18 @@
129 #size-cells = <1>;
130 ranges = <0x0 0x0 0xff800000 0x800000>;
131
132+ hsspi: spi@1000 {
133+ #address-cells = <1>;
134+ #size-cells = <0>;
135+ compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0";
136+ reg = <0x1000 0x600>;
137+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
138+ clocks = <&hsspi_pll &hsspi_pll>;
139+ clock-names = "hsspi", "pll";
140+ num-cs = <8>;
141+ status = "disabled";
142+ };
143+
144 uart0: serial@12000 {
145 compatible = "arm,pl011", "arm,primecell";
146 reg = <0x12000 0x1000>;
147--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
148+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
149@@ -79,6 +79,7 @@
150 #clock-cells = <0>;
151 clock-frequency = <200000000>;
152 };
153+
154 uart_clk: uart-clk {
155 compatible = "fixed-factor-clock";
156 #clock-cells = <0>;
157@@ -86,6 +87,12 @@
158 clock-div = <4>;
159 clock-mult = <1>;
160 };
161+
162+ hsspi_pll: hsspi-pll {
163+ compatible = "fixed-clock";
164+ #clock-cells = <0>;
165+ clock-frequency = <400000000>;
166+ };
167 };
168
169 psci {
170@@ -117,6 +124,18 @@
171 #size-cells = <1>;
172 ranges = <0x0 0x0 0xff800000 0x800000>;
173
174+ hsspi: spi@1000 {
175+ #address-cells = <1>;
176+ #size-cells = <0>;
177+ compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0";
178+ reg = <0x1000 0x600>;
179+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
180+ clocks = <&hsspi_pll &hsspi_pll>;
181+ clock-names = "hsspi", "pll";
182+ num-cs = <8>;
183+ status = "disabled";
184+ };
185+
186 uart0: serial@12000 {
187 compatible = "arm,pl011", "arm,primecell";
188 reg = <0x12000 0x1000>;
189--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
190+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
191@@ -79,6 +79,7 @@
192 #clock-cells = <0>;
193 clock-frequency = <200000000>;
194 };
195+
196 uart_clk: uart-clk {
197 compatible = "fixed-factor-clock";
198 #clock-cells = <0>;
199@@ -86,6 +87,12 @@
200 clock-div = <4>;
201 clock-mult = <1>;
202 };
203+
204+ hsspi_pll: hsspi-pll {
205+ compatible = "fixed-clock";
206+ #clock-cells = <0>;
207+ clock-frequency = <200000000>;
208+ };
209 };
210
211 psci {
212@@ -117,6 +124,19 @@
213 #size-cells = <1>;
214 ranges = <0x0 0x0 0xff800000 0x800000>;
215
216+ hsspi: spi@1000 {
217+ #address-cells = <1>;
218+ #size-cells = <0>;
219+ compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1";
220+ reg = <0x1000 0x600>, <0x2610 0x4>;
221+ reg-names = "hsspi", "spim-ctrl";
222+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
223+ clocks = <&hsspi_pll &hsspi_pll>;
224+ clock-names = "hsspi", "pll";
225+ num-cs = <8>;
226+ status = "disabled";
227+ };
228+
229 uart0: serial@12000 {
230 compatible = "arm,pl011", "arm,primecell";
231 reg = <0x12000 0x1000>;
232--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
233+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
234@@ -60,6 +60,12 @@
235 #clock-cells = <0>;
236 clock-frequency = <200000000>;
237 };
238+
239+ hsspi_pll: hsspi-pll {
240+ compatible = "fixed-clock";
241+ #clock-cells = <0>;
242+ clock-frequency = <400000000>;
243+ };
244 };
245
246 psci {
247@@ -100,5 +106,17 @@
248 clock-names = "refclk";
249 status = "disabled";
250 };
251+
252+ hsspi: spi@1000 {
253+ #address-cells = <1>;
254+ #size-cells = <0>;
255+ compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";
256+ reg = <0x1000 0x600>;
257+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
258+ clocks = <&hsspi_pll &hsspi_pll>;
259+ clock-names = "hsspi", "pll";
260+ num-cs = <8>;
261+ status = "disabled";
262+ };
263 };
264 };
265--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
266+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
267@@ -78,6 +78,12 @@
268 #clock-cells = <0>;
269 clock-frequency = <200000000>;
270 };
271+
272+ hsspi_pll: hsspi-pll {
273+ compatible = "fixed-clock";
274+ #clock-cells = <0>;
275+ clock-frequency = <400000000>;
276+ };
277 };
278
279 psci {
280@@ -137,5 +143,17 @@
281 clock-names = "refclk";
282 status = "disabled";
283 };
284+
285+ hsspi: spi@1000 {
286+ #address-cells = <1>;
287+ #size-cells = <0>;
288+ compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0";
289+ reg = <0x1000 0x600>;
290+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
291+ clocks = <&hsspi_pll &hsspi_pll>;
292+ clock-names = "hsspi", "pll";
293+ num-cs = <8>;
294+ status = "disabled";
295+ };
296 };
297 };
298--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
299+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
300@@ -28,3 +28,7 @@
301 &uart0 {
302 status = "okay";
303 };
304+
305+&hsspi {
306+ status = "okay";
307+};
308--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
309+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
310@@ -28,3 +28,7 @@
311 &uart0 {
312 status = "okay";
313 };
314+
315+&hsspi {
316+ status = "okay";
317+};
318--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
319+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
320@@ -28,3 +28,7 @@
321 &uart0 {
322 status = "okay";
323 };
324+
325+&hsspi {
326+ status = "okay";
327+};
328--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
329+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
330@@ -28,3 +28,7 @@
331 &uart0 {
332 status = "okay";
333 };
334+
335+&hsspi {
336+ status = "okay";
337+};
338--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
339+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
340@@ -28,3 +28,7 @@
341 &uart0 {
342 status = "okay";
343 };
344+
345+&hsspi {
346+ status = "okay";
347+};
348--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
349+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
350@@ -28,3 +28,7 @@
351 &uart0 {
352 status = "okay";
353 };
354+
355+&hsspi {
356+ status = "okay";
357+};
358--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
359+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
360@@ -28,3 +28,7 @@
361 &uart0 {
362 status = "okay";
363 };
364+
365+&hsspi {
366+ status = "okay";
367+};