| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /dts-v1/; |
| 2 | |
| 3 | / { |
| 4 | #address-cells = <1>; |
| 5 | #size-cells = <1>; |
| 6 | compatible = "brcm,bcm3368"; |
| 7 | |
| 8 | aliases { |
| 9 | pflash = &pflash; |
| 10 | gpio0 = &gpio0; |
| 11 | gpio1 = &gpio1; |
| 12 | serial0 = &uart0; |
| 13 | serial1 = &uart1; |
| 14 | spi0 = &lsspi; |
| 15 | }; |
| 16 | |
| 17 | cpus { |
| 18 | #address-cells = <1>; |
| 19 | #size-cells = <0>; |
| 20 | |
| 21 | cpu@0 { |
| 22 | compatible = "brcm,bmips4350", "mips,mips4Kc"; |
| 23 | device_type = "cpu"; |
| 24 | reg = <0>; |
| 25 | }; |
| 26 | |
| 27 | cpu@1 { |
| 28 | compatible = "brcm,bmips4350", "mips,mips4Kc"; |
| 29 | device_type = "cpu"; |
| 30 | reg = <1>; |
| 31 | }; |
| 32 | }; |
| 33 | |
| 34 | cpu_intc: interrupt-controller { |
| 35 | #address-cells = <0>; |
| 36 | compatible = "mti,cpu-interrupt-controller"; |
| 37 | |
| 38 | interrupt-controller; |
| 39 | #interrupt-cells = <1>; |
| 40 | }; |
| 41 | |
| 42 | memory { device_type = "memory"; reg = <0 0>; }; |
| 43 | |
| 44 | pflash: nor@1e000000 { |
| 45 | compatible = "cfi-flash"; |
| 46 | reg = <0x1e000000 0x2000000>; |
| 47 | bank-width = <2>; |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <1>; |
| 50 | |
| 51 | status = "disabled"; |
| 52 | }; |
| 53 | |
| 54 | ubus@fff00000 { |
| 55 | #address-cells = <1>; |
| 56 | #size-cells = <1>; |
| 57 | ranges; |
| 58 | compatible = "simple-bus"; |
| 59 | interrupt-parent = <&periph_intc>; |
| 60 | |
| 61 | periph_intc: interrupt-controller@fff8c00c { |
| 62 | compatible = "brcm,bcm6345-l1-intc"; |
| 63 | reg = <0xfff8c00c 0x8>; |
| 64 | |
| 65 | interrupt-controller; |
| 66 | #interrupt-cells = <1>; |
| 67 | |
| 68 | interrupt-parent = <&cpu_intc>; |
| 69 | interrupts = <2>; |
| 70 | }; |
| 71 | |
| 72 | ext_intc0: interrupt-controller@fff8c014 { |
| 73 | compatible = "brcm,bcm6345-ext-intc"; |
| 74 | reg = <0xfff8c014 0x4>; |
| 75 | |
| 76 | interrupt-controller; |
| 77 | #interrupt-cells = <2>; |
| 78 | |
| 79 | interrupts = <25>, <26>, <27>, <28>; |
| 80 | }; |
| 81 | |
| 82 | gpio1: gpio-controller@fff8c080 { |
| 83 | compatible = "brcm,bcm6345-gpio"; |
| 84 | reg = <0xfff8c080 4>, <0xfff8c088 4>; |
| 85 | |
| 86 | gpio-controller; |
| 87 | #gpio-cells = <2>; |
| 88 | |
| 89 | ngpios = <8>; |
| 90 | }; |
| 91 | |
| 92 | gpio0: gpio-controller@fff8c084 { |
| 93 | compatible = "brcm,bcm6345-gpio"; |
| 94 | reg = <0xfff8c084 4>, <0xfff8c08c 4>; |
| 95 | |
| 96 | gpio-controller; |
| 97 | #gpio-cells = <2>; |
| 98 | }; |
| 99 | |
| 100 | uart0: serial@fff8c100 { |
| 101 | compatible = "brcm,bcm6345-uart"; |
| 102 | reg = <0xfff8c100 0x18>; |
| 103 | |
| 104 | interrupt-parent = <&periph_intc>; |
| 105 | interrupts = <2>; |
| 106 | |
| 107 | /* clocks = <&periph_clk>; */ |
| 108 | /* clock-names = "refclk"; */ |
| 109 | |
| 110 | status = "disabled"; |
| 111 | }; |
| 112 | |
| 113 | uart1: serial@fff8c120 { |
| 114 | compatible = "brcm,bcm6345-uart"; |
| 115 | reg = <0xfff8c120 0x18>; |
| 116 | |
| 117 | interrupt-parent = <&periph_intc>; |
| 118 | interrupts = <3>; |
| 119 | |
| 120 | /* clocks = <&periph_clk>; */ |
| 121 | /* clock-names = "refclk"; */ |
| 122 | |
| 123 | status = "disabled"; |
| 124 | }; |
| 125 | |
| 126 | lsspi: spi@fff8c800 { |
| 127 | #address-cells = <1>; |
| 128 | #size-cells = <0>; |
| 129 | compatible = "brcm,bcm6358-spi"; |
| 130 | reg = <0xfff8c800 0x70c>; |
| 131 | interrupts = <1>; |
| 132 | /* clocks = <&clkctl 9>; */ |
| 133 | }; |
| 134 | }; |
| 135 | }; |