| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | From: MarkLee <Mark-MC.Lee@mediatek.com> |
| 2 | Date: Wed, 13 Nov 2019 10:38:42 +0800 |
| 3 | Subject: [PATCH] net: ethernet: mediatek: Integrate GDM/PSE setup operations |
| 4 | |
| 5 | Integrate GDM/PSE setup operations into single function "mtk_gdm_config" |
| 6 | |
| 7 | Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com> |
| 8 | Signed-off-by: David S. Miller <davem@davemloft.net> |
| 9 | --- |
| 10 | |
| 11 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 12 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 13 | @@ -2252,6 +2252,28 @@ static int mtk_start_dma(struct mtk_eth |
| 14 | return 0; |
| 15 | } |
| 16 | |
| 17 | +static void mtk_gdm_config(struct mtk_eth *eth, u32 config) |
| 18 | +{ |
| 19 | + int i; |
| 20 | + |
| 21 | + for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 22 | + u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); |
| 23 | + |
| 24 | + /* default setup the forward port to send frame to PDMA */ |
| 25 | + val &= ~0xffff; |
| 26 | + |
| 27 | + /* Enable RX checksum */ |
| 28 | + val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; |
| 29 | + |
| 30 | + val |= config; |
| 31 | + |
| 32 | + mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); |
| 33 | + } |
| 34 | + /* Reset and enable PSE */ |
| 35 | + mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); |
| 36 | + mtk_w32(eth, 0, MTK_RST_GL); |
| 37 | +} |
| 38 | + |
| 39 | static int mtk_open(struct net_device *dev) |
| 40 | { |
| 41 | struct mtk_mac *mac = netdev_priv(dev); |
| 42 | @@ -2447,8 +2469,6 @@ static int mtk_hw_init(struct mtk_eth *e |
| 43 | mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); |
| 44 | mtk_tx_irq_disable(eth, ~0); |
| 45 | mtk_rx_irq_disable(eth, ~0); |
| 46 | - mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); |
| 47 | - mtk_w32(eth, 0, MTK_RST_GL); |
| 48 | |
| 49 | /* FE int grouping */ |
| 50 | mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); |
| 51 | @@ -2457,18 +2477,7 @@ static int mtk_hw_init(struct mtk_eth *e |
| 52 | mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); |
| 53 | mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); |
| 54 | |
| 55 | - for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 56 | - u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); |
| 57 | - |
| 58 | - /* setup the forward port to send frame to PDMA */ |
| 59 | - val &= ~0xffff; |
| 60 | - |
| 61 | - /* Enable RX checksum */ |
| 62 | - val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; |
| 63 | - |
| 64 | - /* setup the mac dma */ |
| 65 | - mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); |
| 66 | - } |
| 67 | + mtk_gdm_config(eth, MTK_GDMA_TO_PDMA); |
| 68 | |
| 69 | return 0; |
| 70 | |
| 71 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 72 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 73 | @@ -84,6 +84,7 @@ |
| 74 | #define MTK_GDMA_ICS_EN BIT(22) |
| 75 | #define MTK_GDMA_TCS_EN BIT(21) |
| 76 | #define MTK_GDMA_UCS_EN BIT(20) |
| 77 | +#define MTK_GDMA_TO_PDMA 0x0 |
| 78 | |
| 79 | /* Unicast Filter MAC Address Register - Low */ |
| 80 | #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) |