| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | From 04b3b72b5b8fdb883bfdc619cb29b03641b1cc6a Mon Sep 17 00:00:00 2001 |
| 2 | From: Robert Marko <robimarko@gmail.com> |
| 3 | Date: Thu, 15 Aug 2019 19:28:23 +0200 |
| 4 | Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI controller node |
| 5 | |
| 6 | IPQ4019 has a built in SD/eMMC controller which is supported by the |
| 7 | SDHCI MSM driver, by the "qcom,sdhci-msm-v4" binding. |
| 8 | So lets add the appropriate node for it. |
| 9 | |
| 10 | Signed-off-by: Robert Marko <robimarko@gmail.com> |
| 11 | Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> |
| 12 | --- |
| 13 | arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++++++ |
| 14 | 1 file changed, 12 insertions(+) |
| 15 | |
| 16 | --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi |
| 17 | +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi |
| 18 | @@ -207,6 +207,18 @@ |
| 19 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| 20 | }; |
| 21 | |
| 22 | + sdhci: sdhci@7824900 { |
| 23 | + compatible = "qcom,sdhci-msm-v4"; |
| 24 | + reg = <0x7824900 0x11c>, <0x7824000 0x800>; |
| 25 | + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| 26 | + interrupt-names = "hc_irq", "pwr_irq"; |
| 27 | + bus-width = <8>; |
| 28 | + clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, |
| 29 | + <&gcc GCC_DCD_XO_CLK>; |
| 30 | + clock-names = "core", "iface", "xo"; |
| 31 | + status = "disabled"; |
| 32 | + }; |
| 33 | + |
| 34 | blsp_dma: dma@7884000 { |
| 35 | compatible = "qcom,bam-v1.7.0"; |
| 36 | reg = <0x07884000 0x23000>; |