| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | From e2b0ebb44e91e3492f26d21218fb7ea5e14190ec Mon Sep 17 00:00:00 2001 | 
|  | 2 | From: Haiying Wang <Haiying.Wang@nxp.com> | 
|  | 3 | Date: Thu, 20 Apr 2017 11:54:22 -0400 | 
|  | 4 | Subject: [PATCH] soc: fsl: dpio: change CENA regs to be cacheable | 
|  | 5 |  | 
|  | 6 | Change cache enabled regsiter accessed to be cacheable | 
|  | 7 | plus non-shareable to meet the performance requirement. | 
|  | 8 | QMan's CENA region contains registers and structures that | 
|  | 9 | are 64byte in size and are inteneded to be accessed using a | 
|  | 10 | single 64 byte bus transaction, therefore this portal | 
|  | 11 | memory should be configured as cache-enabled. Also because | 
|  | 12 | the write allocate stash transcations of QBMan should be | 
|  | 13 | issued as cachable and non-coherent(non-sharable), we | 
|  | 14 | need to configure this region to be non-shareable. | 
|  | 15 |  | 
|  | 16 | Signed-off-by: Haiying Wang <Haiying.Wang@nxp.com> | 
|  | 17 | --- | 
|  | 18 | drivers/soc/fsl/dpio/dpio-driver.c | 17 ++++++++++------- | 
|  | 19 | 1 file changed, 10 insertions(+), 7 deletions(-) | 
|  | 20 |  | 
|  | 21 | --- a/drivers/soc/fsl/dpio/dpio-driver.c | 
|  | 22 | +++ b/drivers/soc/fsl/dpio/dpio-driver.c | 
|  | 23 | @@ -27,6 +27,11 @@ MODULE_LICENSE("Dual BSD/GPL"); | 
|  | 24 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); | 
|  | 25 | MODULE_DESCRIPTION("DPIO Driver"); | 
|  | 26 |  | 
|  | 27 | +#define PROT_NORMAL_NS		(PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) | 
|  | 28 | + | 
|  | 29 | +#define ioremap_cache_ns(addr, size)	__ioremap((addr), (size), __pgprot(PROT_NORMAL_NS)) | 
|  | 30 | + | 
|  | 31 | + | 
|  | 32 | struct dpio_priv { | 
|  | 33 | struct dpaa2_io *io; | 
|  | 34 | }; | 
|  | 35 | @@ -197,13 +202,11 @@ static int dpaa2_dpio_probe(struct fsl_m | 
|  | 36 | if (dpio_dev->obj_desc.region_count < 3) { | 
|  | 37 | /* No support for DDR backed portals, use classic mapping */ | 
|  | 38 | /* | 
|  | 39 | -		 * Set the CENA regs to be the cache inhibited area of the | 
|  | 40 | -		 * portal to avoid coherency issues if a user migrates to | 
|  | 41 | -		 * another core. | 
|  | 42 | +		 * Set the CENA regs to be the cache enabled area of the portal to | 
|  | 43 | +		 * achieve the best performance. | 
|  | 44 | */ | 
|  | 45 | -		desc.regs_cena = devm_memremap(dev, dpio_dev->regions[1].start, | 
|  | 46 | -					resource_size(&dpio_dev->regions[1]), | 
|  | 47 | -					MEMREMAP_WC); | 
|  | 48 | +		desc.regs_cena = ioremap_cache_ns(dpio_dev->regions[0].start, | 
|  | 49 | +						resource_size(&dpio_dev->regions[0])); | 
|  | 50 | } else { | 
|  | 51 | desc.regs_cena = devm_memremap(dev, dpio_dev->regions[2].start, | 
|  | 52 | resource_size(&dpio_dev->regions[2]), | 
|  | 53 | @@ -211,7 +214,7 @@ static int dpaa2_dpio_probe(struct fsl_m | 
|  | 54 | } | 
|  | 55 |  | 
|  | 56 | if (IS_ERR(desc.regs_cena)) { | 
|  | 57 | -		dev_err(dev, "devm_memremap failed\n"); | 
|  | 58 | +		dev_err(dev, "ioremap_cache_ns failed\n"); | 
|  | 59 | err = PTR_ERR(desc.regs_cena); | 
|  | 60 | goto err_allocate_irqs; | 
|  | 61 | } |