b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Arch specific code for Ralink based boards |
| 3 | * |
| 4 | * Copyright (C) 2013 John Crispin <blogic@openwrt.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <stddef.h> |
| 12 | #include "config.h" |
| 13 | |
| 14 | #define READREG(r) *(volatile unsigned int *)(r) |
| 15 | #define WRITEREG(r,v) *(volatile unsigned int *)(r) = v |
| 16 | |
| 17 | #define KSEG1ADDR(_x) (((_x) & 0x1fffffff) | 0xa0000000) |
| 18 | |
| 19 | #ifdef CONFIG_SOC_RT288X |
| 20 | #define UART_BASE 0xb0300c00 |
| 21 | #else |
| 22 | #define UART_BASE 0xb0000c00 |
| 23 | #endif |
| 24 | |
| 25 | #define UART_TX 1 |
| 26 | #define UART_LSR 7 |
| 27 | |
| 28 | #define UART_LSR_THRE 0x20 |
| 29 | |
| 30 | #define UART_READ(r) READREG(UART_BASE + 4 * (r)) |
| 31 | #define UART_WRITE(r,v) WRITEREG(UART_BASE + 4 * (r), (v)) |
| 32 | |
| 33 | void board_putc(int ch) |
| 34 | { |
| 35 | while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); |
| 36 | UART_WRITE(UART_TX, ch); |
| 37 | while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); |
| 38 | } |
| 39 | |
| 40 | void board_init(void) |
| 41 | { |
| 42 | } |