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b.liue9582032025-04-17 19:18:16 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2023 ASR Microelectronics Co., Ltd.
4 */
5
6/dts-v1/;
7#include "asr1806.dtsi"
8
9/ {
10 model = "ASR 1806(FALCON-T) Board EVB";
11 compatible = "asr,1803-evb", "asr,1803";
12
13 chosen {
14 bootargs = "root=/dev/mtdblock5 rootfstype=squashfs init=/etc/preinit noinitrd console=ttyS0,115200 mem=128M";
15 };
16
17 memory {
18 reg = <0x00000000 0x10000000>;
19 };
20
21 firmware {
22 optee {
23 compatible = "linaro,optee-tz";
24 method = "smc";
25 };
26 };
27
28 soc {
29 axi@d4200000 { /* AXI */
30 usbphy: usbphy@d4207000 {
31 status = "okay";
32 };
33#ifdef CONFIG_USB_DWC2_ASR_OTG /* otg mode */
34 usb: usb@c0000000 {
35 dr_mode = "otg";
36 pinctrl-names = "default","sleep";
37 pinctrl-0 = <&usb_id_pinmux &usb_host_pinmux>;
38 pinctrl-1 = <&usb_id_pinmux_slp &usb_host_pinmux>;
39 usbid_gpio = <99>;
40 edge_detect_gpio = <99>;
41 otg,use-gpio-vbus;
42 gpio-num = <122>;
43 status = "okay";
44 };
45#else
46 usb: usb@c0000000 {
47 status = "okay";
48 };
49#endif
50
51 eth0: asr-eth@0xd4281800 {
52 compatible = "asr,asr-eth";
53 pinctrl-names = "default", "rgmii-pins";
54 pinctrl-0 = <&emac_pmx_func0 &emac_pmx_func2 &emac_pmx_func3>;
55 pinctrl-1 = <&emac_pmx_func0 &emac_pmx_func1 &emac_pmx_func2 &emac_pmx_func3>;
56 reg = <0xd4281800 0x200>;
57 interrupts = <10 11>;
58 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
59 clocks = <&soc_clocks ASR1803_CLK_EMAC
60 &soc_clocks ASR1803_CLK_EMAC_PTP>;
61 clock-names = "emac-clk", "ptp-clk";
62 ptp-support;
63 ptp-clk-rate = <100000000>;
64 status = "okay";
b.liub17525e2025-05-14 17:22:29 +080065 enable-suspend;
66 reset-gpio = <&gpio 42 0>;
b.liue9582032025-04-17 19:18:16 +080067 reset-active-low;
b.liub17525e2025-05-14 17:22:29 +080068 reset-delays-us = <100000 100000 100000>;
69 //ldo-gpio = <&gpio 40 0>;
70 //ldo-active-low;
71 // ldo-delays-us = <0 100000 100000>;
72 //vmmc-supply = <0x19>;
73 mdio-clk-div = <254>;
b.liue9582032025-04-17 19:18:16 +080074 flow-control-threshold = <60 90>;
75 clk-tuning-enable;
76 /* clk-config(32bit)
77 *
78 * clk_sel(clk-config[23:16])
79 * RGMII:
80 * tx | clk_sel: 0 - from external RX clock
81 * 1 - from inverted external RX clock
82 * rx | clk_sel: 0 - from external RX clock
83 * 1 - from inverted external RX clock
84 *
85 * RMII:
86 * tx | clk_sel: 0 - RMII clock
87 * 1 - Inverted RMII clock
88 * rx | clk_sel: 0 - RMII clock
89 * 1 - Inverted RMII clock
90 *
91 */
92#if 0
93 /* enable 1000M phy*/
94 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
b.liub17525e2025-05-14 17:22:29 +080095 phy-handle = <&phy3>;
b.liue9582032025-04-17 19:18:16 +080096#else
97 /* enable 100M phy*/
b.liub17525e2025-05-14 17:22:29 +080098 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
hj.shaofe1632a2025-06-05 00:19:33 -070099 phy-handle = <&phy0>;
b.liue9582032025-04-17 19:18:16 +0800100#endif
101 /* enable fix link for ethernet switch */
102 /*
103 fixed-link {
104 speed = <100>;
105 full-duplex;
106 phy-mode = "rmii";
107 };
108 */
109
110 mdio: mdio-bus {
111 #address-cells = <0x1>;
112 #size-cells = <0x0>;
113 /* YT8521 10M/100M/100OM 1.8V RGMII PHY */
114 phy0: phy@0 {
115 compatible = "ethernet-phy-ieee802.3-c22";
116 device_type = "ethernet-phy";
117 reg = <0x0>; /* set phy address*/
118 phy-mode = "rgmii";
hj.shaofe1632a2025-06-05 00:19:33 -0700119 // tx_rx_delay = <0xb 0x0>; /* 150ps per step*/
b.liue9582032025-04-17 19:18:16 +0800120 };
121
122 /* YT8512B 10M/100M 3.3V RMII PHY */
b.liub17525e2025-05-14 17:22:29 +0800123 // phy3: phy@3 {
124 // compatible = "ethernet-phy-ieee802.3-c22";
125 // device_type = "ethernet-phy";
126 // reg = <0x3>; /* set phy address*/
127 // phy-mode = "rmii";
128 // driver_strength = <0x3>;
129 // };
b.liue9582032025-04-17 19:18:16 +0800130
131 /* IP175D 10M/100M 3.3V RMII SWITCH */
132 phy1: phy@1 {
133 compatible = "ethernet-phy-ieee802.3-c22";
134 device_type = "ethernet-phy";
135 reg = <0x1>; /* set phy address*/
136 phy-mode = "rmii";
137 };
b.liub17525e2025-05-14 17:22:29 +0800138
139
140 /* jl 3103 phy */
141 phy3: phy@3 {
142 compatible = "ethernet-phy-ieee802.3-c22";
143 device_type = "ethernet-phy";
144 reg = <0x3>; /* set phy address*/
145 phy-mode = "rgmii-id";
146 lynq,jl3103=<100 0>;
147 };
b.liue9582032025-04-17 19:18:16 +0800148 };
149 };
150 qspi: spi@0xd420b000 {
151 asr,qspi-freq = <78000000>;
152 status = "okay";
153 };
154 /* SD card */
155 sdh0: sdh@d4280000 {
156 pinctrl-names = "default", "slow", "fast", "sleep";
157 pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>;
158 pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>;
159 pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>;
160 pinctrl-3 = <&sdh0_pmx_cd_wakeup>;
161 /*
162 * Genernal use, juse set vmmc-supply and vqmmc-supply
163 * vmmc-supply = <&supply1>
164 * vqmmc-supply = <&supply2>
165 *
166 * For compatibility, to select one from two supply source
167 * vmmc-supply = <&supply1 &supply1_backup>;
168 * vqmmc-supply = <&supply2 &supply2_backup>;
169 * vmmc2-supply = <&supply1_backup &supply1>;
170 * vqmmc2-supply = <&supply2_backup &supply2>;
171 */
172 vmmc-supply = <&vcc_sdh1>;
zw.wang5deb3e82025-05-30 11:29:23 +0800173 vqmmc-supply = <&pm802ldo6 &pm803ldo8>;
b.liue9582032025-04-17 19:18:16 +0800174#ifndef CONFIG_ASR_DSDS
175 vmmc2-supply = <&vcc_sdh1 &pm802ldo4>;
176 vqmmc2-supply = <&pm803ldo8 &pm802ldo6>;
177#endif
178 bus-width = <4>;
179 no-mmc;
180 no-sdio;
181 /*non-removable;
182 broken-cd;*/
183 wp-inverted;
184 asr,sdh-pm-runtime-en;
185 asr,sdh-host-caps-disable = <(MMC_CAP_UHS_SDR104)>;
186#if 1 /* CD via gpio */
zw.wang5deb3e82025-05-30 11:29:23 +0800187 //cd-gpios = <&gpio 90 1>;
b.liue9582032025-04-17 19:18:16 +0800188 asr,sdh-quirks2 = <(
189 SDHCI_QUIRK2_SET_AIB_MMC |
190 SDHCI_QUIRK2_PRESET_VALUE_BROKEN
191 )>;
192 asr,sdh-host-caps = <(
193 MMC_CAP_CD_WAKE
194 )>;
195 asr,sdh-quirks = <(
196 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
197 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
198 )>;
199#else /* CD via SDH */
200 asr,sdh-quirks = <(
201 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
202 )>;
203 asr,sdh-quirks2 = <(
204 SDHCI_QUIRK2_SET_AIB_MMC |
205 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
206 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON
207 )>;
208#endif
209 /* prop "sdh-dtr-data":
210 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
211 asr,sdh-dtr-data =
212 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
213 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>,
214 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
215 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 0>,
216 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
217 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_104M 0 0 0 0>;
218 status = "okay";
219 };
220
221 /* SDIO */
222 sdh1: sdh@d4280800 {
223 pinctrl-names = "default", "fast", "sleep";
b.liub17525e2025-05-14 17:22:29 +0800224 pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2>;
225 pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast>;
226 /* pinctrl-2 = <&sdh1_pmx_edge_wakeup>;*/
b.liue9582032025-04-17 19:18:16 +0800227 bus-width = <4>;
228 no-mmc;
229 no-sd;
230 non-removable;
231 keep-power-in-suspend;
232 enable-sdio-wakeup;
233 /* clk-scaling-config:
234 <up_threshold down_threshold polling_interval> */
235 clk-scaling-config = <25 12 200>;
236 min-ddr-qos = <156000 312000 400000>;
237 asr,sdh-pm-runtime-en;
238 asr,sdh-quirks = <(
239 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
240 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
241 )>;
242 asr,sdh-quirks2 = <(
243 SDHCI_QUIRK2_NO_TIMER_RETUNING |
244 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
245 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON
246 )>;
247 asr,sdh-pm-caps = <(MMC_PM_KEEP_POWER)>;
248 asr,sdh-host-caps2 = <(
249 MMC_CAP2_ONLY_1_8V |
250 MMC_CAP2_DISABLE_PROBE_CDSCAN |
251 MMC_CAP2_CLK_SCALE |
252 MMC_CAP2_BUS_CLK_NO_SCALE
253 )>;
254 /* prop "sdh-dtr-data":
255 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
256 asr,sdh-dtr-data =
257 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
258 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>,
259 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
260 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_83M PXA_SDH_DTR_83M 0 0 0 3>,
b.liub17525e2025-05-14 17:22:29 +0800261 //<PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
262 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_52M PXA_SDH_DTR_52M 0 0 0 0>,
b.liue9582032025-04-17 19:18:16 +0800263 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>;
264 status = "okay";
265 };
266 pcie0: pcie@0xd4288000{
267 reset-gpios = <&gpio 42 0 >;
b.liub17525e2025-05-14 17:22:29 +0800268 status = "disbabled";
b.liue9582032025-04-17 19:18:16 +0800269 };
270 pciephy0: pcie-phy@d4206000 {
271 status = "okay";
272 };
273 };
274
275 apb@d4000000 {
276 ssp_dai1: pxa-ssp-dai@1 {
277 compatible = "asr,pxa-ssp-dai";
278 reg = <0x1 0x0>;
279
280 port = <&ssp1>;
281 pinctrl-names = "default","ssp";
282 pinctrl-0 = <&i2s_gpio>;
283 pinctrl-1 = <&i2s_func>;
284 ssp-gpio = <&gpio 25 0 &gpio 26 0 &gpio 27 0 &gpio 28 0>;
285
286 dmas = <&pdma0 54 1
287 &pdma0 55 1>;
288 dma-names = "rx", "tx";
289
290 platform_driver_name = "pdma_platform";
291 burst_size = <4>;
292 playback_period_bytes = <2048>;
293 playback_buffer_bytes = <4096>;
294 capture_period_bytes = <2048>;
295 capture_buffer_bytes = <4096>;
296 };
297 mfpr: mfpr@d401e000 {
298 status = "okay";
299 /* intend to replace lpm-board-cfg
300 no-apbsd-in-d1pp = <0x1>; //"wakeup-state-d1pp"
301 pin1:pin1@d401e01B0 {
302 offset = <0x1B0>;
303 udr-cfg = <0xA040>;
304 };
305 pin2:pin2@d401e01B4 {
306 offset = <0x1B4>;
307 udr-cfg = <0xA040>;
308 };
309 */
310 };
311 timer0: timer@d4014000 {
312 status = "okay";
313 };
314 uart1: uart@d4017000 { /* nezhas evb use ap uart */
315 pinctrl-names = "default","sleep";
316 pinctrl-0 = <&uart1_pmx_func1 &uart1_pmx_func2>;
317 pinctrl-1 = <&uart1_pmx_func1_sleep &uart1_pmx_func2>;
b.liub17525e2025-05-14 17:22:29 +0800318 //edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */
b.liue9582032025-04-17 19:18:16 +0800319 status = "okay";
320 };
321 uart2: uart@d4036000 {
322 pinctrl-names = "default";
b.liub17525e2025-05-14 17:22:29 +0800323 pinctrl-0 = <&gps_pmx_uart_rxd &gps_pmx_uart_txd &gps_pmx_func_cts_rts>;
b.liue9582032025-04-17 19:18:16 +0800324 status = "okay";
325 };
326 uart3: uart@d4018000 {
327 pinctrl-names = "default";
328 pinctrl-0 = <&uart3_pmx_func>;
b.liub17525e2025-05-14 17:22:29 +0800329 status = "okay";
b.liue9582032025-04-17 19:18:16 +0800330 };
331 uart4: uart@d401f000 {
332 pinctrl-names = "default";
b.liub17525e2025-05-14 17:22:29 +0800333 pinctrl-0 = <&uart4_pmx_func>; /*BAUD :9600*/
334 /*pinctrl-0 = <&uart4_pmx_func_rxd &uart4_pmx_func_txd &uart4_pmx_func_cts_rts>;*/
335 status = "okay";
b.liue9582032025-04-17 19:18:16 +0800336 };
337 rtc: rtc@d4010000 {
338 status = "okay";
339 };
340 pmx: pinmux@d401e000 {
341 /* pin base = base_addr / 4, nr pins & gpio function */
342 pinctrl-single,gpio-range = <
343 /*
344 * GPIO number is hardcoded for range at here.
345 * In gpio chip, GPIO number is not hardcoded for range.
346 * Since one gpio pin may be routed to multiple pins,
347 * define these gpio range in pxa910-dkb.dts not pxa910.dtsi.
348 */
349 /*&range 80 4 0 */ /* GPIO25 ~ GPIO28 */
350 &range 55 32 0 /* GPIO0 ~ GPIO31 */
351 &range 87 32 0 /* GPIO32 ~ GPIO63 */
352 &range 119 32 0 /* GPIO64 ~ GPIO95 */
353 &range 151 32 0 /* GPIO96 ~ GPIO127 */
354 >;
355
356 ssp0_pmx_func: ssp0_pmx_func {
357 pinctrl-single,pins = <
358 GPIO36 AF1 /* TXD */
359 GPIO35 AF1 /* RXD */
360 GPIO34 AF1 /* FRM */
361 /*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */
362 GPIO33 AF1 /* SCLK */
363 >;
b.liub17525e2025-05-14 17:22:29 +0800364 DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage
365 };
366 ssp2_pmx_func: ssp2_pmx_func {
367 pinctrl-single,pins = <
368 GPIO37 AF3 /* TXD */
369 GPIO38 AF3 /* SCLK */
370 GPIO39 AF3 /* FRM */
371 GPIO40 AF3 /* RXD */
372 >;
373 DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage
b.liue9582032025-04-17 19:18:16 +0800374 };
375 lcd_bl_func: lcd_bl_func {
376 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800377 /* VCXO_OUT AF1 GPIO126, lcd bl */
378 /* GPIO24 AF0 reset */
379 /* GPIO22 AF0 lcd d/c */
b.liue9582032025-04-17 19:18:16 +0800380 >;
381 MFP_DEFAULT;
382 };
383 uart1_pmx_func1: uart1_pmx_func1 {
384 pinctrl-single,pins = <
385 GPIO29 AF1
386 >;
387 MFP_DEFAULT;
388 };
389 uart1_pmx_func2: uart1_pmx_func2 {
390 pinctrl-single,pins = <
391 GPIO30 AF1
392 >;
393 MFP_DEFAULT;
394 };
395 uart1_pmx_func1_sleep: uart1_pmx_func1_sleep {
396 pinctrl-single,pins = <
397 GPIO29 AF1
398 >;
b.liub17525e2025-05-14 17:22:29 +0800399 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
b.liue9582032025-04-17 19:18:16 +0800400 };
401 twsi0_pmx_func: twsi0_pmx_func {
402 pinctrl-single,pins = <
403 GPIO49 AF1
404 GPIO50 AF1
405 >;
b.liub17525e2025-05-14 17:22:29 +0800406 DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT;
b.liue9582032025-04-17 19:18:16 +0800407 };
408 twsi0_pmx_gpio: twsi0_pmx_gpio {
409 pinctrl-single,pins = <
410 GPIO49 AF0
411 GPIO50 AF0
412 >;
b.liub17525e2025-05-14 17:22:29 +0800413 DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT;
b.liue9582032025-04-17 19:18:16 +0800414 };
b.liub17525e2025-05-14 17:22:29 +0800415#if 1
b.liue9582032025-04-17 19:18:16 +0800416 twsi1_pmx_func: twsi1_pmx_func {
417 pinctrl-single,pins = <
418 GPIO10 AF1
419 GPIO11 AF1
420 >;
b.liub17525e2025-05-14 17:22:29 +0800421 DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT;
b.liue9582032025-04-17 19:18:16 +0800422 };
423 twsi1_pmx_gpio: twsi1_pmx_gpio {
424 pinctrl-single,pins = <
425 GPIO10 AF0
426 GPIO11 AF0
427 >;
b.liub17525e2025-05-14 17:22:29 +0800428 DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT;
b.liue9582032025-04-17 19:18:16 +0800429 };
430#endif
431 /* no pull, no LPM */
432 dvc_pmx_func: dvc_pmx_func {
433 /* hw-dvc */
434 pinctrl-single,pins = <
435 TDS_DIO0 AF0
436 TDS_DIO1 AF0
437 >;
438 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
439 };
440 leds_pmx_func: leds_pmx_func {
441 pinctrl-single,pins = <
442 DF_IO10 AF1
443 DF_IO11 AF1
444 DF_IO12 AF1
445 >;
446 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
447 };
448
449 gps_pmx_onoff: gps_pmx_onoff {
450 pinctrl-single,pins = <
451 TDS_TXREV AF1
452 >;
453 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
454 };
455 gps_pmx_reset: gps_pmx_reset {
456 pinctrl-single,pins = <
457 TDS_RXON AF1
458 >;
459 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
460 };
b.liub17525e2025-05-14 17:22:29 +0800461
462 //zqy
463 gnss_clk_on: gnss_clk_on {
464 pinctrl-single,pins = <
465 GPIO43 AF2 /*32K CLK */
466
467 /*VCXO_REQ AF1 GPIO[125] GPS_WAKE_HOST */
468 GPIO47 AF0 /* HOST_WAKE_GPS */
469 GPIO45 AF0 /*RESET */
470 CLK_REQ AF1 /*sleep en*/
471
472 >;
473 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
474 };
b.liue9582032025-04-17 19:18:16 +0800475 gps_pmx_uart_rxd: gps_pmx_uart_rxd {
476 /* gps dedicated uart */
477 pinctrl-single,pins = <
478 GPIO51 AF1
479 GPIO32 AF1
480 >;
b.liub17525e2025-05-14 17:22:29 +0800481 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
b.liue9582032025-04-17 19:18:16 +0800482 };
483 gps_pmx_uart_txd: gps_pmx_uart_txd {
484 /* gps dedicated uart */
485 pinctrl-single,pins = <
486 GPIO52 AF1
487 GPIO31 AF1
488 >;
b.liub17525e2025-05-14 17:22:29 +0800489 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
b.liue9582032025-04-17 19:18:16 +0800490 };
b.liub17525e2025-05-14 17:22:29 +0800491 gps_pmx_func_cts_rts: gps_pmx_func_cts_rts {
492 pinctrl-single,pins = <
493 GPIO31 AF1 /* cts */
494 GPIO32 AF1 /* rts */
495 >;
496 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
497 };
498
b.liue9582032025-04-17 19:18:16 +0800499 uart3_pmx_func: uart3_pmx_func {
500 pinctrl-single,pins = <
501 GPIO53 AF1 /* RX */
yu.dongca721ca2025-06-04 07:21:21 -0700502 /* GPIO54 AF1 TX */
b.liue9582032025-04-17 19:18:16 +0800503 >;
504 MFP_DEFAULT;
505 };
b.liub17525e2025-05-14 17:22:29 +0800506
507
508 uart4_pmx_func_rxd: uart4_pmx_func_rxd {
509 pinctrl-single,pins = <
510 GPIO37 AF2
511 GPIO40 AF2
512 >;
513 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
514 };
515 uart4_pmx_func_txd: uart4_pmx_func_txd {
516 pinctrl-single,pins = <
517 GPIO38 AF2
518 GPIO39 AF2
519 >;
520 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
521 };
522
523 uart4_pmx_func_cts_rts: uart4_pmx_func_cts_rts {
524 pinctrl-single,pins = <
525 GPIO39 AF2
526 GPIO40 AF2
527 >;
528 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
529 };
b.liue9582032025-04-17 19:18:16 +0800530 uart4_pmx_func: uart4_pmx_func {
531 pinctrl-single,pins = <
532 GPIO44 AF1 /* RX */
533 GPIO45 AF1 /* TX */
534 >;
b.liub17525e2025-05-14 17:22:29 +0800535 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
b.liue9582032025-04-17 19:18:16 +0800536 };
537 panel_rst_func: panel_rst_func {
538 pinctrl-single,pins = <
539 DF_nCS1 AF1
540 >;
541 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
542 };
543
544 sd_ldo_en: sd_ldo_en {
545 pinctrl-single,pins = <
546 GPIO45 AF0
547 >;
548 MFP_PULL_DOWN;
549 };
550 sdh0_pmx_func1: sdh0_pmx_func1 {
551 pinctrl-single,pins = <
552 MMC1_DAT3 AF0
553 MMC1_DAT2 AF0
554 MMC1_DAT1 AF0
555 MMC1_DAT0 AF0
556 MMC1_CMD AF0
557 >;
558 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
559 };
560 sdh0_pmx_func2: sdh0_pmx_func2 {
561 pinctrl-single,pins = <
562 MMC1_CLK AF0
563 >;
564 DS_MEDIUM;PULL_NONE;EDGE_NONE;
565 };
566 sdh0_pmx_func3: sdh0_pmx_func3 {
567 pinctrl-single,pins = <
568 MMC1_CD AF1
569 >;
570 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
571 };
572 sdh0_pmx_cd_wakeup: sdh0_pmx_func1_cd_wakeup {
573 pinctrl-single,pins = <
574 MMC1_CD AF1
575 >;
576 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
577 };
578 sdh0_pmx_func1_slow: sdh0_pmx_func1_slow {
579 pinctrl-single,pins = <
580 MMC1_DAT3 AF0
581 MMC1_DAT2 AF0
582 MMC1_DAT1 AF0
583 MMC1_DAT0 AF0
584 MMC1_CMD AF0
585 >;
586 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
587 };
588 sdh0_pmx_func2_slow: sdh0_pmx_func2_slow {
589 pinctrl-single,pins = <
590 MMC1_CLK AF0
591 >;
592 DS_FAST0;PULL_NONE;EDGE_NONE;
593 };
594 sdh0_pmx_func1_fast: sdh0_pmx_func1_fast {
595 pinctrl-single,pins = <
596 MMC1_DAT3 AF0
597 MMC1_DAT2 AF0
598 MMC1_DAT1 AF0
599 MMC1_DAT0 AF0
600 MMC1_CMD AF0
601 >;
602 DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL;
603 };
604 sdh0_pmx_func2_fast: sdh0_pmx_func2_fast {
605 pinctrl-single,pins = <
606 MMC1_CLK AF0
607 >;
608 DS_FAST1;PULL_NONE;EDGE_NONE;
609 };
610 sdh1_pmx_func1_fast: sdh1_pmx_func1_fast {
611 pinctrl-single,pins = <
612 TDS_DIO13 AF0 /* WLAN_DAT3 */
613 TDS_DIO14 AF0 /* WLAN_DAT2 */
614 TDS_DIO15 AF0 /* WLAN_DAT1 */
615 TDS_DIO16 AF0 /* WLAN_DAT0 */
616 TDS_DIO17 AF0 /* WLAN_CMD */
617 >;
618 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
619 };
620 sdh1_pmx_func2_fast: sdh1_pmx_func2_fast {
621 pinctrl-single,pins = <
622 TDS_DIO18 AF0 /* WLAN_CLK */
623 >;
624 DS_FAST0;PULL_DOWN;EDGE_NONE;SL_NORMAL;
625 };
626 sdh1_pmx_func1: sdh1_pmx_func1 {
627 pinctrl-single,pins = <
628 TDS_DIO13 AF0 /* WLAN_DAT3 */
629 TDS_DIO14 AF0 /* WLAN_DAT2 */
630 TDS_DIO15 AF0 /* WLAN_DAT1 */
631 TDS_DIO16 AF0 /* WLAN_DAT0 */
632 TDS_DIO17 AF0 /* WLAN_CMD */
633 >;
634 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
635 };
636 sdh1_pmx_func2: sdh1_pmx_func2 {
637 pinctrl-single,pins = <
638 TDS_DIO18 AF0 /* WLAN_CLK */
639 >;
640 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_LOW;
641 };
642 sdh1_pmx_func3: sdh1_pmx_func3 {
643 pinctrl-single,pins = <
644 GPIO10 AF0 /* VCXO_REQ AF1 WLAN_WAKE_HOST */
645 >;
646 MFP_PULL_DOWN;
647 };
648 sdh1_pmx_edge_wakeup: sdh1_pmx_edge_wakeup {
649 pinctrl-single,pins = <
650 GPIO10 AF0 /* VCXO_REQ AF1 */
651 >;
652 DS_MEDIUM;PULL_DOWN;EDGE_RISE;SL_NORMAL;
653 };
654 sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off {
655 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800656 /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */
657 /* GPIO08 AF0 GPIO32 AF0 LDO_EN */
658 MMC1_CD AF1
b.liue9582032025-04-17 19:18:16 +0800659 >;
660 MFP_PULL_DOWN;
661 };
662 sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on {
663 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800664 /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */
665 /* GPIO08 AF0 GPIO32 AF0 LDO_EN */
666 MMC1_CD AF1
667 >;
668 MFP_PULL_UP;
669 };
670
671
672 mbtk_sdh_pmx_off: mbtk_sdh_pmx_off {
673 pinctrl-single,pins = <
674 VCXO_REQ AF1 //gpio125 wlan en
675 GPIO123 AF1 //wlan pwr en
you.chen9824a892025-06-04 20:23:26 +0800676 /*VCXO_OUT AF1 /*gpio127 wifi wake*/
b.liub17525e2025-05-14 17:22:29 +0800677 >;
678 MFP_PULL_DOWN;
679 };
680 mbtk_sdh_pmx_on: mbtk_sdh_pmx_on {
681 pinctrl-single,pins = <
682 VCXO_REQ AF1 //gpio125 wlan en
683 GPIO123 AF1 //wlan pwr en
you.chen9824a892025-06-04 20:23:26 +0800684 /*VCXO_OUT AF1 /*gpio127 wifi wake*/
b.liue9582032025-04-17 19:18:16 +0800685 >;
686 MFP_PULL_UP;
687 };
688 alc5616_pmx_func1: alc5616_pmx_func1 {
689 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800690 /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */
b.liue9582032025-04-17 19:18:16 +0800691 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
692 >;
693 MFP_DEFAULT;
694 };
695 alc5616_pmx_func2: alc5616_pmx_func2 {
696 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800697 /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */
698 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
699 >;
700 MFP_DEFAULT;
701 };
702
703 es8311_pa_func1: es8311_pa_func1 {
704 pinctrl-single,pins = <
705 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
yu.dongca721ca2025-06-04 07:21:21 -0700706 GPIO54 AF0
707 GPIO24 AF0
b.liub17525e2025-05-14 17:22:29 +0800708 >;
709 MFP_DEFAULT;
710 };
711 es8311_pa_func2: es8311_pa_func2 {
712 pinctrl-single,pins = <
b.liue9582032025-04-17 19:18:16 +0800713 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
yu.dongca721ca2025-06-04 07:21:21 -0700714 GPIO54 AF0
715 GPIO24 AF0
b.liue9582032025-04-17 19:18:16 +0800716 >;
717 MFP_DEFAULT;
718 };
719 audio_pa_pmx_func: audio_pa_pmx_func {
720 pinctrl-single,pins = <
721 GPIO14 AF0 /* PA */
722 >;
723 MFP_DEFAULT;
724 };
725 ecall_pmx_func: ecall_pmx_func {
726 pinctrl-single,pins = <
727 GPIO08 AF0 /* auto mode ecall */
728 GPIO09 AF0 /* manual mode ecall */
729 >;
730 MFP_DEFAULT;
731 };
732 slic_pmx_func1: slic_pmx_func1 {
733 pinctrl-single,pins = <
734 GPIO20 AF0 /* SLIC_INT, GPIO20 */
735 VCXO_OUT AF1 /* GPIO127, SLIC_3V3LDO_EN/LCD_BK_EN */
736 >;
737 MFP_DEFAULT;
738 };
739 slic_pmx_func2: slic_pmx_func2 {
740 pinctrl-single,pins = <
741 GPIO21 AF0 /* SLIC_RESET, GPIO21 */
742 >;
743 MFP_DEFAULT;
744 };
745 slic_pmx_func1_sleep: slic_pmx_func1_sleep {
746 pinctrl-single,pins = <
747 GPIO20 AF0 /* SLIC_INT, GPIO20 */
748 >;
749 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
750 };
751
752 otg_vbus_func: otg_vbus_func {
753 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800754 /* VBUS_DRV AF1 GPIO[122] */
b.liue9582032025-04-17 19:18:16 +0800755 >;
756 DS_MEDIUM;PULL_DOWN;EDGE_NONE;
757 };
758
759 emac_pmx_func0: emac_pmx_func0 {
760 pinctrl-single,pins = <
761 GPIO00 AF1 /* GMAC1_RX_DV */
762 GPIO01 AF1 /* GMAC1_RX_D0 */
763 GPIO02 AF1 /* GMAC1_RX_D1 */
764 GPIO03 AF1 /* GMAC1_RX_CLK */
765 /* GPIO04 AF1 GMAC1_RX_D2 */
766 /* GPIO05 AF1 GMAC1_RX_D3 */
767 GPIO06 AF1 /* GMAC1_TX_D0 */
768 GPIO07 AF1 /* GMAC1_TX_D1 */
769 /* GPIO12 AF1 GMAC1_TX_CLK */
770 /* GPIO13 AF1 GMAC1_TX_D2 */
771 /* GPIO14 AF1 GMAC1_TX_D3 */
772 GPIO15 AF1 /* GMAC1_TX_EN */
773 GPIO16 AF1 /* GMAC1_TX_MDC */
774 /* GPIO17 AF1 GMAC1_TX_MDIO */
775 >;
776 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
777 };
778 emac_pmx_func1: emac_pmx_func1 {
779 pinctrl-single,pins = <
780 GPIO04 AF1 /* GMAC1_RX_D2 */
781 GPIO05 AF1 /* GMAC1_RX_D3 */
782 GPIO12 AF1 /* GMAC1_TX_CLK */
783 GPIO13 AF1 /* GMAC1_TX_D2 */
784 GPIO14 AF1 /* GMAC1_TX_D3 */
785 >;
786 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
787 };
788 emac_pmx_func2: emac_pmx_func2 {
789 pinctrl-single,pins = <
790 GPIO17 AF1 /* GMAC1_TX_MDIO */
791 GPIO18 AF1 /* GMAC1_TX_INT_N */
792 >;
793 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
794 };
795 emac_pmx_func3: emac_pmx_func3 {
796 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800797 GPIO42 AF0 /* RESET */
798 /* GPIO40 AF0 LDO_EN */
b.liue9582032025-04-17 19:18:16 +0800799 >;
800 DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
801 };
802 usim1_pmx_func: usim1_pmx_func {
803 pinctrl-single,pins = <
yq.wang107f9862025-05-12 15:44:50 +0800804 PRI_TCK AF1
b.liue9582032025-04-17 19:18:16 +0800805 >;
806 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
807 };
808 usim1_pmx_func_sleep: usim1_pmx_func_sleep {
809 pinctrl-single,pins = <
yq.wang107f9862025-05-12 15:44:50 +0800810 PRI_TCK AF1
b.liue9582032025-04-17 19:18:16 +0800811 >;
812 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
813 };
814 usim2_pmx_func: usim2_pmx_func {
815 pinctrl-single,pins = <
816 GPIO44 AF0
817 >;
818 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
819 };
820 usim2_pmx_func_sleep: usim2_pmx_func_sleep {
821 pinctrl-single,pins = <
822 GPIO44 AF0
823 >;
824 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
825 };
826 pcie_pmx_pd_rst_off: pcie_pmx_pd_rst_off {
827 pinctrl-single,pins = <
828 GPIO42 AF0 /* PERST_N */
829 GPIO24 AF0 /* DC_EN */
830 >;
831 MFP_PULL_DOWN;
832 };
833 pcie_pmx_pd_rst_on: pcie_pmx_pd_rst_on {
834 pinctrl-single,pins = <
835 GPIO42 AF0 /* PERST_N */
836 GPIO24 AF0 /* DC_EN */
837 >;
838 MFP_PULL_UP;
839 };
b.liub17525e2025-05-14 17:22:29 +0800840 pin_func_work: pin_func_work {
841 pinctrl-single,pins = <
842
843 GPIO08 AF0 /*T108 status led* /
844
845 VBUS_DRV AF2 /*32k*/
846
847
848 GPIO46 AF0 /*wifi en*/
849
850 GPIO19 AF0 /*bt en*/
851
852 >;
853 MFP_DEFAULT;
854 };
855
856
857 sc_ext_int0: sc_ext_int0 {
858 pinctrl-single,pins = <
859 GPIO21 AF0
860 >;
861 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
862 };
863 sc_ext_int1: sc_ext_int1 {
864 pinctrl-single,pins = <
865 GPIO22 AF0
866 >;
867 MFP_DEFAULT;
868 };
869
870 sc_ext_int2: sc_ext_int2 {
871 pinctrl-single,pins = <
872 GPIO23 AF0
873 >;
874 MFP_DEFAULT;
875 };
876
877
878 sc_ext_int3: sc_ext_int3 {
879 pinctrl-single,pins = <
880 GPIO24 AF0
881 >;
882 MFP_DEFAULT;
883 };
884
885
886 mbtk_plat_irq_func: mbtk_plat_irq_func {
887 pinctrl-single,pins = <
888
you.chen9824a892025-06-04 20:23:26 +0800889 /*GPIO21 AF0
890 GPIO22 AF0 */
b.liub17525e2025-05-14 17:22:29 +0800891 GPIO23 AF0
yu.dongca721ca2025-06-04 07:21:21 -0700892 GPIO24 AF0
b.liub17525e2025-05-14 17:22:29 +0800893
894 >;
895 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
896 };
897 mbtk_plat_irq_func_sleep: mbtk_plat_irq_func_sleep {
898 pinctrl-single,pins = <
you.chen9824a892025-06-04 20:23:26 +0800899 /*GPIO21 AF0
900 GPIO22 AF0*/
b.liub17525e2025-05-14 17:22:29 +0800901 GPIO23 AF0
yu.dongca721ca2025-06-04 07:21:21 -0700902 GPIO24 AF0
b.liub17525e2025-05-14 17:22:29 +0800903 >;
904 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
905 };
906
907
b.liue9582032025-04-17 19:18:16 +0800908 gpiokey_pmx_func: gpiokey_pmx_func {
909 pinctrl-single,pins = <
910 GPIO09 AF0
911 >;
912 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
913 };
b.liub17525e2025-05-14 17:22:29 +0800914
915 wake_pmx_func1: wake_pmx_func1 {
916 pinctrl-single,pins = <
917 USB_ID AF1
918 >;
919 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
920 };
921
hong.liuf2416882025-05-23 20:41:06 -0700922 led_pmx_func1: led_pmx_func1 {
923 pinctrl-single,pins = <
924 GPIO08 AF0
925 >;
926 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
927 };
928
b.liub17525e2025-05-14 17:22:29 +0800929
930 wake_pmx_func: wake_pmx_func {
931 pinctrl-single,pins = <
932 PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/
933
934 PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/
935 GPIO41 AF0
936 PRI_TDO AF1 /*GPIO120*/
937
938
939 >;
940 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
941 };
942 wake_pmx_func_sleep: wake_pmx_func_sleep {
943 pinctrl-single,pins = <
944 PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/
945
946 PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/
947 GPIO41 AF0
948 PRI_TDO AF1 /*GPIO120*/
949
950 >;
951 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
952 };
953 usb_id_pinmux: usb_id_pinmux {
b.liue9582032025-04-17 19:18:16 +0800954 pinctrl-single,pins = <
955 USB_ID AF1/* usbid-gpio99 */
956 >;
957 DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE;
958 };
959 usb_id_pinmux_slp: usb_id_pinmux_slp {
960 pinctrl-single,pins = <
961 USB_ID AF1 /* usbid-gpio99 */
962 >;
963 DS_MEDIUM;PULL_UP;EDGE_BOTH;LPM_NONE;
964 };
965 usb_host_pinmux: usb_host_pinmux {
966 pinctrl-single,pins = <
967 VBUS_DRV AF1 /* gpio-122 */
968 >;
969 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE;
970 };
971 i2s_func: i2s_func {
972 pinctrl-single,pins = <
973 GPIO25 AF2
974 GPIO26 AF2
975 GPIO27 AF2
976 GPIO28 AF2
977 >;
978 MFP_DEFAULT;
979 };
980 i2s_gpio: i2s_gpio {
981 pinctrl-single,pins = <
982 GPIO25 AF0
983 GPIO26 AF0
984 GPIO27 AF0
985 GPIO28 AF0
986 >;
987 MFP_LPM_FLOAT;
988 };
you.chen9824a892025-06-04 20:23:26 +0800989 sensors_int:sensors_int {
990 pinctrl-single,pins = <
991 GPIO22 AF0
992 >;
993 MFP_PULL_DOWN;
994 };
995 sensors_csb:sensors_csb {
996 pinctrl-single,pins = <
997 VCXO_OUT AF1
998 >;
999 DS_MEDIUM;PULL_UP;EDGE_NONE;
1000 };
b.liue9582032025-04-17 19:18:16 +08001001 };
1002
1003 ssp0: spi@d401b000 {
1004 status = "okay";
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&ssp0_pmx_func>;
1007 asr,spi-inc-mode;
1008#ifdef CONFIG_FB_SPI_LCD
1009 /* this enhancemnet feature is not suitable for
1010 3 line 9bits spi lcd. */
1011 /* asr,ssp-enhancement; */
1012
1013 lcd: spidev@0 {
1014 #address-cells = <1>;
1015 #size-cells = <1>;
1016 compatible = "spilcd";
b.liub17525e2025-05-14 17:22:29 +08001017 // pinctrl-names = "default";
1018 // pinctrl-0 = <&lcd_bl_func>;
b.liue9582032025-04-17 19:18:16 +08001019 reg = <0>;
1020 /* ST7735: need to set spi-max-frequency to 26M
1021 * ST7789V: can set spi-max-frequency to 52M
1022 */
1023 spi-max-frequency = <26000000>;
1024 xres = <128>;
1025 yres = <128>;
1026 bits = <8>; /* 8: 4line, 9: 3line */
1027 rst_gpio = <&gpio 24 0>;
b.liub17525e2025-05-14 17:22:29 +08001028 // bl_gpio = <&gpio 126 0>;
b.liue9582032025-04-17 19:18:16 +08001029 rs_gpio = <&gpio 22 0>;
1030 /* if comment the following statement, it means
1031 * the avdd is sit on the "always-on" ldo.
1032 */
1033 /* avdd-supply = <&LDO1>; */
1034 };
1035#else
1036 /*cs-gpios = <&gpio 34 0>;*//* DXS101 Use the config of Cs-gpios */
1037 slic: spidev@0{
1038 #address-cells = <1>;
1039 #size-cells = <1>;
1040 compatible = "asr,slic";
1041 reg = <0>;
1042 spi-cpol;
1043 spi-cpha;
1044 spi-max-frequency = <6500000>;
1045 };
1046#endif
1047 };
b.liub17525e2025-05-14 17:22:29 +08001048 ssp2: spi@d401c000{
1049 status = "okay";
1050 pinctrl-names = "default";
1051 pinctrl-0 = <&ssp2_pmx_func>;
1052 asr,spi-inc-mode;
1053 cs-gpios = <&gpio 39 0>;
1054 status = "okay";
1055 mbtk: spidev@0{
1056 compatible = "asr,spidev";
1057 reg = <0>;
1058 status = "okay";
1059 spi-cpol;
1060 spi-cpha;
1061 spi-max-frequency = <6500000>;
1062 };
1063 };
b.liue9582032025-04-17 19:18:16 +08001064 twsi0: i2c@d4011000 {
1065 status= "okay";
1066 alc5616@1b {
b.liub17525e2025-05-14 17:22:29 +08001067 status= "disabled";
b.liue9582032025-04-17 19:18:16 +08001068 compatible = "asrmicro,alc5616";
1069 reg = <0x1b>;
1070 pinctrl-names = "default", "sleep";
1071 pinctrl-0 = <&alc5616_pmx_func1>;
1072 pinctrl-1 = <&alc5616_pmx_func2>;
1073 clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
1074 clock-names = "i2s_sys_clk";
1075#if 0
1076 3V3-gpio = <&gpio 23 0>;/* CODEC_LDO_EN */
1077 irq-gpio = <&gpio 24 0>;/* CODEC_IRQ for headset detection */
1078#else
1079 irq-gpio = <&gpio 8 0>;/* CODEC_IRQ for headset detection */
1080#endif
1081 };
1082
b.liub17525e2025-05-14 17:22:29 +08001083 nau8810@1a {
1084 compatible = "marvell,nau8810";
1085 clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
1086 clock-names = "i2s_sys_clk";
1087
1088
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&es8311_pa_func1>;
1091 pinctrl-1 = <&es8311_pa_func2>;
1092 reg = <0x1a>;
1093 status= "disabled";
1094 };
1095
1096 es8311@18 {
1097 compatible = "ambarella,es8311";
1098 reg = <0x18>;
1099 clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
1100 clock-names = "i2s_sys_clk";
1101
1102 pinctrl-names = "default";
1103 pinctrl-0 = <&es8311_pa_func1>;
1104 pinctrl-1 = <&es8311_pa_func2>;
1105
1106 // gpios = <&gpio 21 0>,
1107 // <&gpio 23 0>,
1108 // <&gpio 24 0>,
1109 // <&gpio 22 0>;
1110
1111 status= "okay";
1112 };
1113
you.chen9824a892025-06-04 20:23:26 +08001114 asm330lhhx-imu@0x6a {
1115 compatible = "st,asm330lhhx";
1116 reg = <0x6b>;
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&sensors_int &sensors_csb>;
1119 interrupt-parent = <&gpio>;
1120 interrupts = <22 1>;
1121 //interrupts = <22>;
1122 vddio-supply = <&sensors_vddio>;
1123 //vdd-supply = <&sensors_vdd>;
1124 st,int-pin = <1>;
1125 //st,mlc-int-pin = <2>;
1126 mount-matrix = "1", "0", "0",
1127 "0", "1", "0",
1128 "0", "0", "1";
1129 };
yu.dongb39db3e2025-06-06 03:15:42 -07001130 /* AWINIC AW87XXX Smart K PA */
1131 aw87xxx_pa@58 {
1132 compatible = "awinic,aw87xxx_pa";
1133 reg = <0x58>;
1134 reset-gpio = <&gpio 24 0>;
1135 dev_index = < 0 >;
1136 status = "okay";
1137 };
1138 /* AWINIC AW87XXX Smart K PA End */
b.liue9582032025-04-17 19:18:16 +08001139 /*
1140 pmic4: 88pm805@38 {
1141 compatible = "marvell,88pm805";
1142 reg = <0x38>;
1143 };
1144 */
1145 };
1146 twsi1: i2c@d4010800 {
b.liub17525e2025-05-14 17:22:29 +08001147#if 1
b.liue9582032025-04-17 19:18:16 +08001148 pinctrl-names = "default","gpio";
1149 pinctrl-0 = <&twsi1_pmx_func>;
1150 pinctrl-1 = <&twsi1_pmx_gpio>;
1151 i2c-gpio = <&gpio 10 0 &gpio 11 0>;
1152#endif
b.liub17525e2025-05-14 17:22:29 +08001153 status= "okay";
1154 //nau8810@1a {
1155 // compatible = "marvell,nau8810";
1156 // reg = <0x1a>;
1157 //};
1158
1159
b.liue9582032025-04-17 19:18:16 +08001160 };
1161 twsi2: i2c@d4037000 {
1162 status = "okay";
1163
1164 pmic4: 88pm805@38 {
1165 compatible = "marvell,88pm805";
1166 reg = <0x38>;
1167 };
1168
1169 pmic5: pm802@0 {
1170 compatible = "asr,pm802";
1171 reg = <0x00>;
1172 interrupts = <4>;
1173 interrupt-parent = <&intc>;
1174 interrupt-controller;
1175 #interrupt-cells = <1>;
1176 chg_irq_from_exton;
1177 scs-int-active-high;
1178 battery {
1179 compatible = "asr,pm802-bat";
1180 status = "disabled";
1181
1182 online-gpadc = <1>;
1183 temperature-gpadc = <1>;
1184
1185 hi-volt-online = <1150>; /* mV */
1186 lo-volt-online = <20>; /* mV */
1187 hi-volt-temp = <1150>; /* mV */
1188 lo-volt-temp = <200>; /* mV */
1189
1190 sw-fg-use-ntc;
1191 full-capacity = <2050>; /* mAh */
1192 r1-resistor = <40>; /* mohm */
1193 r2-resistor = <30>; /* mohm */
1194 rs-resistor = <120>; /* mohm */
1195 roff-resistor = <0>; /* mohm */
1196 roff-initial-resistor = <0>; /* mohm */
1197
1198 times-in-zero-degree = <1>;
1199 offset-in-zero-degree = <0>;
1200
1201 times-in-ten-degree = <2>;
1202 offset-in-ten-degree = <100>;
1203
1204 power-off-threshold = <3350>; /* mV */
1205 safe-power-off-threshold = <3200>; /* mV */
1206
1207 online-gp-bias-curr = <11>; /* uA */
1208
1209 soc-ramp-up-interval = <150>; /* s */
1210 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
1211 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
1212 ntc-table-size = <88>;
1213 stop-chg-for-vbatmeas;
1214 /* -24C, -23C, ..., 62C, 63C */
1215 ntc-table = <
1216 89680 85130 80840 76790 72970 69360 65960 62740
1217 59700 56830 54130 51530 49100 46800 44610 42550
1218 40590 38730 36970 35300 33710 32210 30780 29420
1219 28130 26910 25750 24640 23590 22580 21630 20720
1220 19860 19030 18250 17500 16790 16110 15460 14840
1221 14250 13690 13150 12640 12150 11680 11230 10800
1222 10390 10000 9620 9270 8920 8590 8280 7980
1223 7690 7410 7150 6890 6650 6410 6190 5970
1224 5770 5570 5380 5190 5020 4850 4680 4530
1225 4380 4230 4100 3960 3830 3710 3590 3480
1226 3370 3260 3160 3060 2960 2870 2780 2700
1227 >;
1228 };
1229 usb {
1230 status = "disabled";
1231 vbus_gpio = <0xff>; /* set_vbus */
1232 id-gpadc = <0xff>; /* usb-id */
1233 vchg-from-exton = <1>;
1234 vbus-detect = <1>; /* vbus-irq */
1235 get-vbus = <1>; /* get-vbus */
1236 };
1237 };
1238 pmic6: pm803@30 {
1239 compatible = "asr,pm803";
1240 reg = <0x30>;
1241 interrupts = <4>;
1242 interrupt-parent = <&intc>;
1243 interrupt-controller;
1244 #interrupt-cells = <1>;
1245 chg_irq_from_exton;
1246 scs-int-active-high;
1247 battery {
1248 compatible = "asr,pm803-bat";
1249 status = "disabled";
1250
1251 online-gpadc = <1>;
1252 temperature-gpadc = <1>;
1253
1254 hi-volt-online = <1150>; /* mV */
1255 lo-volt-online = <20>; /* mV */
1256 hi-volt-temp = <1150>; /* mV */
1257 lo-volt-temp = <200>; /* mV */
1258
1259 sw-fg-use-ntc;
1260 full-capacity = <2050>; /* mAh */
1261 r1-resistor = <40>; /* mohm */
1262 r2-resistor = <30>; /* mohm */
1263 rs-resistor = <120>; /* mohm */
1264 roff-resistor = <0>; /* mohm */
1265 roff-initial-resistor = <0>; /* mohm */
1266
1267 times-in-zero-degree = <1>;
1268 offset-in-zero-degree = <0>;
1269
1270 times-in-ten-degree = <2>;
1271 offset-in-ten-degree = <100>;
1272
1273 power-off-threshold = <3350>; /* mV */
1274 safe-power-off-threshold = <3200>; /* mV */
1275
1276 online-gp-bias-curr = <11>; /* uA */
1277
1278 soc-ramp-up-interval = <150>; /* s */
1279 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
1280 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
1281 ntc-table-size = <88>;
1282 stop-chg-for-vbatmeas;
1283 /* -24C, -23C, ..., 62C, 63C */
1284 ntc-table = <
1285 89680 85130 80840 76790 72970 69360 65960 62740
1286 59700 56830 54130 51530 49100 46800 44610 42550
1287 40590 38730 36970 35300 33710 32210 30780 29420
1288 28130 26910 25750 24640 23590 22580 21630 20720
1289 19860 19030 18250 17500 16790 16110 15460 14840
1290 14250 13690 13150 12640 12150 11680 11230 10800
1291 10390 10000 9620 9270 8920 8590 8280 7980
1292 7690 7410 7150 6890 6650 6410 6190 5970
1293 5770 5570 5380 5190 5020 4850 4680 4530
1294 4380 4230 4100 3960 3830 3710 3590 3480
1295 3370 3260 3160 3060 2960 2870 2780 2700
1296 >;
1297 };
1298 usb {
1299 status = "disabled";
1300 vbus_gpio = <0xff>; /* set_vbus */
1301 id-gpadc = <0xff>; /* usb-id */
1302 vchg-from-exton = <1>;
1303 vbus-detect = <1>; /* vbus-irq */
1304 get-vbus = <1>; /* get-vbus */
1305 };
1306 };
1307 };
1308 };
1309 };
1310
1311 vcc_sdh1: sd-regulator {
1312 compatible = "regulator-fixed";
b.liub17525e2025-05-14 17:22:29 +08001313 /*pinctrl-names = "default";*/
1314 /*pinctrl-0 = <&sd_ldo_en>;*/
b.liue9582032025-04-17 19:18:16 +08001315 regulator-name = "SDH1 VCC";
1316 regulator-min-microvolt = <3300000>;
1317 regulator-max-microvolt = <3300000>;
b.liub17525e2025-05-14 17:22:29 +08001318 /* gpio = <&gpio 45 0>;*/
b.liue9582032025-04-17 19:18:16 +08001319 enable-active-high;
1320 status = "okay";
1321 };
1322
you.chen9824a892025-06-04 20:23:26 +08001323 sensors_vddio: imu-regulator {
1324 compatible = "regulator-fixed";
1325 /*pinctrl-names = "default";*/
1326 /*pinctrl-0 = <&sd_ldo_en>;*/
1327 regulator-name = "IMU VDDIO";
1328 gpio = <&gpio 21 0>;
1329 enable-active-high;
1330 status = "okay";
1331 };
1332
b.liue9582032025-04-17 19:18:16 +08001333 asr-rfkill {
1334 compatible = "asr,asr-rfkill";
1335 pinctrl-names = "off", "on";
1336 pinctrl-0 = <&sdh1_pmx_pd_rst_off>;
1337 pinctrl-1 = <&sdh1_pmx_pd_rst_on>;
b.liub17525e2025-05-14 17:22:29 +08001338 sd-host = <&sdh0>;
1339 //pd-gpio = <&gpio 90 0>;
1340 rst-gpio = <&gpio 90 0>;
1341
1342 /*3v3-ldo-gpio = <&gpio 8 0>;*/
1343 /*edge-wakeup-gpio = <&gpio 10 0>;*/
1344 status = "okay";
1345 };
1346
1347 mbtk-sdh{
1348 compatible = "mbtk,mbtk-sdh";
1349 pinctrl-names = "off", "on";
1350 pinctrl-0 = <&mbtk_sdh_pmx_off>;
1351 pinctrl-1 = <&mbtk_sdh_pmx_on>;
1352 sd-host = <&sdh1>;
1353 1v8-ldo-gpio = <&gpio 123 0>;
you.chen9824a892025-06-04 20:23:26 +08001354 //host-wakeup-wlan-gpio = <&gpio 127 0>;
b.liub17525e2025-05-14 17:22:29 +08001355 wlan_en_gpio = <&gpio 125 0>;
1356 status = "okay";
1357 };
1358
1359 asr-gps {
1360 compatible = "asr,asr-gnss";
1361 pinctrl-names = "default";
1362 pinctrl-0 = <&gnss_clk_on>;
1363 enable_vctcxo_out1;
1364 host-wakeup-gnss-gpio = <&gpio 47 0>;
1365 /*gnss-wakeup-host-gpio = <&gpio 47 0>;*/
1366 rst-gpio = <&gpio 45 0>;
b.liue9582032025-04-17 19:18:16 +08001367 status = "okay";
1368 };
1369
1370 pcie-rfkill {
1371 compatible = "mrvl,pcie-rfkill";
1372 pinctrl-names = "off", "on";
1373 pinctrl-0 = <&pcie_pmx_pd_rst_off>;
1374 pinctrl-1 = <&pcie_pmx_pd_rst_on>;
1375 rst-gpio = <&gpio 42 0>;
1376 3v3-ldo-gpio = <&gpio 24 0>;
b.liub17525e2025-05-14 17:22:29 +08001377 status = "disabled";
b.liue9582032025-04-17 19:18:16 +08001378 };
1379
1380 sound {
1381 compatible = "ASRMICRO,asrmicro-snd-card";
1382 ssp-controllers = <&ssp_dai1>;
1383 };
1384
b.liub17525e2025-05-14 17:22:29 +08001385 asr-adc {
1386 compatible = "asr,adc";
1387 //pinctrl-names = "default";
1388 //pinctrl-0 = <&pin_func_work>;
1389 status = "okay";
1390 };
1391
1392#if 0
1393
1394 mbtk_PlatIrq{
1395 compatible = "mbtk,plat-irq";
1396 pinctrl-names = "sc_irq0", "sc_irq1", "sc_irq2", "sc_irq3";
1397
1398 pinctrl-0 = <&sc_ext_int0>;
1399 pinctrl-1 = <&sc_ext_int1>;
1400 pinctrl-2 = <&sc_ext_int2>;
1401 pinctrl-3 = <&sc_ext_int3>;
yu.dongca721ca2025-06-04 07:21:21 -07001402 status = "disabled";
b.liub17525e2025-05-14 17:22:29 +08001403 };
1404
1405#else
1406
1407 mbtk_PlatIrq{
1408 compatible = "mbtk,plat-irq";
1409 pinctrl-names = "default", "sleep";
1410 pinctrl-0 = <&mbtk_plat_irq_func>;
1411 pinctrl-1 = <&mbtk_plat_irq_func_sleep>;
you.chen9824a892025-06-04 20:23:26 +08001412 //gpio_irq0 = <&gpio 21 0>;
1413 //gpio_irq1 = <&gpio 22 0>;
b.liub17525e2025-05-14 17:22:29 +08001414 gpio_irq2 = <&gpio 23 0>;
1415 gpio_irq3 = <&gpio 24 0>;
yu.dongca721ca2025-06-04 07:21:21 -07001416 status = "disabled";
b.liub17525e2025-05-14 17:22:29 +08001417 };
1418
1419#endif
1420
b.liue9582032025-04-17 19:18:16 +08001421 ecall {
1422 compatible = "asr,ecall-event";
1423 pinctrl-names = "default";
1424 pinctrl-0 = <&ecall_pmx_func>;
1425 gpio-auto-ecall = <8>;
1426 gpio-manual-ecall = <9>;
1427 status = "disabled";
1428 };
1429
1430 usim1: usim1 {
1431 compatible = "asr,usim1";
1432 pinctrl-names = "default", "sleep";
1433 pinctrl-0 = <&usim1_pmx_func>;
1434 pinctrl-1 = <&usim1_pmx_func_sleep>;
yq.wang107f9862025-05-12 15:44:50 +08001435 edge_detect_gpio = <119>; /* GPIO19: SIM detect pin */
b.liue9582032025-04-17 19:18:16 +08001436 status = "okay";
1437 };
1438 /* set okay for this node if usim2 is needed */
1439 usim2: usim2 {
1440 compatible = "asr,usim2";
1441 pinctrl-names = "default", "sleep";
1442 pinctrl-0 = <&usim2_pmx_func>;
1443 pinctrl-1 = <&usim2_pmx_func_sleep>;
1444 edge_detect_gpio = <44>; /* GPIO44: SIM detect pin */
1445#ifdef CONFIG_ASR_DSDS
1446 status = "okay";
1447#else
1448 status = "disabled";
1449#endif
1450 };
1451 gpio_keys {
1452 compatible = "gpio-keys";
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1455 /* autorepeat; */
1456 pinctrl-names = "default";
1457 pinctrl-0 = <&gpiokey_pmx_func>;
1458 button@1 {
1459 label = "qrcode-key";
1460 linux,code = <139>; /* KEY_MENU, refer to linux/input.h */
1461 /* NOTE:
1462 * We use the FORCE DOWNLOAD key to implement the qrcode key in DKB.
1463 * Customer SHOULD change it to any other gpios.
1464 * Because user may do the misoperation that
1465 * powerup with FDL key pressed,
1466 * then the borad will enter force download mode.
1467 */
1468 gpios = <&gpio 9 1>;
1469 gpio-key,wakeup;
1470 };
1471 };
1472
1473 audio_pa {
1474 compatible = "asrmicro,audio-pa";
1475 pinctrl-names = "default";
1476 pinctrl-0 = <&audio_pa_pmx_func>;
1477 pa-gpio = <&gpio 14 0>;
b.liub17525e2025-05-14 17:22:29 +08001478 status = "disabled";
b.liue9582032025-04-17 19:18:16 +08001479 };
b.liub17525e2025-05-14 17:22:29 +08001480 mbtk_GpioWakeUp {
1481 compatible = "mbtk,GpioWakeUp";
1482 pinctrl-names = "default", "sleep";
1483 pinctrl-0 = <&wake_pmx_func &wake_pmx_func1>;
1484 pinctrl-1 = <&wake_pmx_func_sleep>;
1485 wakeup-in-gpio = <&gpio 118 0>;
1486 wakeup-out-gpio = <&gpio 117 0>;
1487 status = "okay";
1488 };
b.liue9582032025-04-17 19:18:16 +08001489
hong.liuf2416882025-05-23 20:41:06 -07001490
1491 dtsleds{
1492 compatible = "gpio-leds";
1493 pinctrl-names = "default";
1494 pinctrl-0 = <&led_pmx_func1>;
1495 status = "okay";
1496 led0{
1497 label = "red";
1498 gpios = <&gpio 8 0>;
1499 linux,default-trigger = "pattern";
1500 led-pattern = "100:100:100";
1501 default-state = "on";
1502
1503 };
1504
1505 // led1{
1506 // label = "blue";
1507 // gpios = <&gpio 99 0>;
1508 // linux,default-trigger = "timer";
1509 // timer-delay-on = <100>;
1510 // timer-delay-off = <100>;
1511 // brightness-levels = <100>;
1512 // brightness-max = <100>;
1513 // default-state = "on";
1514 // };
1515
1516 };
1517
b.liue9582032025-04-17 19:18:16 +08001518 audio_regs {
1519 compatible = "ASRMICRO,audio-registers";
1520 reg = <0xD4050044 0x4>;
1521 status = "okay";
1522 };
1523
1524 nz3-slic {
1525 compatible = "asr,nz3-slic";
1526 pinctrl-names = "default", "sleep";
1527 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1528 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1529 rst-gpio = <&gpio 21 0>;
1530 edge-wakeup-gpio = <&gpio 20 0>;
1531 vdd-3v3-gpio = <&gpio 127 0>;
1532 status = "disabled";
1533 };
1534 microsemi-slic {
1535 compatible = "asr,microsemi-slic";
1536 pinctrl-names = "default", "sleep";
1537 pinctrl-0 = <&slic_pmx_func1>;
1538 pinctrl-1 = <&slic_pmx_func1_sleep>;
1539 edge-wakeup-gpio = <&gpio 20 0>;
1540 vdd-3v3-gpio = <&gpio 127 0>;
1541 status = "disabled";
1542 };
1543 maxlinear-slic {
1544 compatible = "asr,maxlinear-slic";
1545 pinctrl-names = "default", "sleep";
1546 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1547 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1548 rst-gpio = <&gpio 21 0>;
1549 edge-wakeup-gpio = <&gpio 20 0>;
1550 vdd-3v3-gpio = <&gpio 127 0>;
1551 status = "disabled";
1552 };
1553 /* deprecated, move to mfpr@d401e000
1554 lpm-board-cfg {
1555 compatible = "asr,lpm-board-cfg";
1556 wakeup-state-d1pp = <0x1>;
1557 udr-mfpr-config = <0x1B0 0xA040 0x0
1558 0x1B4 0xA040 0x0>;
1559 };
1560 */
1561};
1562#ifdef CONFIG_ASR_DSDS
1563#include "asr_pm802_2usim.dtsi"
1564#include "88pm805.dtsi"
1565#include "asr_pm803_2usim.dtsi"
1566#else
1567#include "asr_pm802.dtsi"
1568#include "88pm805.dtsi"
1569#include "asr_pm803.dtsi"
1570#endif
1571
1572#ifdef CONFIG_AB_SYSTEM
1573#include "asr1806_ab_flash_layout.dtsi"
1574#else
1575#include "asr1806_flash_layout.dtsi"
1576#endif