b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2023 ASR Microelectronics Co., Ltd. |
| 4 | */ |
| 5 | |
| 6 | /dts-v1/; |
| 7 | #include "asr1806.dtsi" |
| 8 | |
| 9 | / { |
| 10 | model = "ASR 1806(FALCON-T) Board EVB"; |
| 11 | compatible = "asr,1803-evb", "asr,1803"; |
| 12 | |
| 13 | chosen { |
| 14 | bootargs = "root=/dev/mtdblock5 rootfstype=squashfs init=/etc/preinit noinitrd console=ttyS0,115200 mem=128M"; |
| 15 | }; |
| 16 | |
| 17 | memory { |
| 18 | reg = <0x00000000 0x10000000>; |
| 19 | }; |
| 20 | |
| 21 | firmware { |
| 22 | optee { |
| 23 | compatible = "linaro,optee-tz"; |
| 24 | method = "smc"; |
| 25 | }; |
| 26 | }; |
| 27 | |
| 28 | soc { |
| 29 | axi@d4200000 { /* AXI */ |
| 30 | usbphy: usbphy@d4207000 { |
| 31 | status = "okay"; |
| 32 | }; |
| 33 | #ifdef CONFIG_USB_DWC2_ASR_OTG /* otg mode */ |
| 34 | usb: usb@c0000000 { |
| 35 | dr_mode = "otg"; |
| 36 | pinctrl-names = "default","sleep"; |
| 37 | pinctrl-0 = <&usb_id_pinmux &usb_host_pinmux>; |
| 38 | pinctrl-1 = <&usb_id_pinmux_slp &usb_host_pinmux>; |
| 39 | usbid_gpio = <99>; |
| 40 | edge_detect_gpio = <99>; |
| 41 | otg,use-gpio-vbus; |
| 42 | gpio-num = <122>; |
| 43 | status = "okay"; |
| 44 | }; |
| 45 | #else |
| 46 | usb: usb@c0000000 { |
| 47 | status = "okay"; |
| 48 | }; |
| 49 | #endif |
| 50 | |
| 51 | eth0: asr-eth@0xd4281800 { |
| 52 | compatible = "asr,asr-eth"; |
| 53 | pinctrl-names = "default", "rgmii-pins"; |
| 54 | pinctrl-0 = <&emac_pmx_func0 &emac_pmx_func2 &emac_pmx_func3>; |
| 55 | pinctrl-1 = <&emac_pmx_func0 &emac_pmx_func1 &emac_pmx_func2 &emac_pmx_func3>; |
| 56 | reg = <0xd4281800 0x200>; |
| 57 | interrupts = <10 11>; |
| 58 | lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| 59 | clocks = <&soc_clocks ASR1803_CLK_EMAC |
| 60 | &soc_clocks ASR1803_CLK_EMAC_PTP>; |
| 61 | clock-names = "emac-clk", "ptp-clk"; |
| 62 | ptp-support; |
| 63 | ptp-clk-rate = <100000000>; |
| 64 | status = "okay"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 65 | enable-suspend; |
hj.shao | f72d6ff | 2025-06-10 04:34:26 -0700 | [diff] [blame^] | 66 | // reset-gpio = <&gpio 42 0>; |
| 67 | // reset-active-low; |
| 68 | // reset-delays-us = <100000 100000 100000>; |
| 69 | local-mac-address = [02 00 00 00 10 01]; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 70 | //ldo-gpio = <&gpio 40 0>; |
| 71 | //ldo-active-low; |
| 72 | // ldo-delays-us = <0 100000 100000>; |
| 73 | //vmmc-supply = <0x19>; |
| 74 | mdio-clk-div = <254>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 75 | flow-control-threshold = <60 90>; |
| 76 | clk-tuning-enable; |
| 77 | /* clk-config(32bit) |
| 78 | * |
| 79 | * clk_sel(clk-config[23:16]) |
| 80 | * RGMII: |
| 81 | * tx | clk_sel: 0 - from external RX clock |
| 82 | * 1 - from inverted external RX clock |
| 83 | * rx | clk_sel: 0 - from external RX clock |
| 84 | * 1 - from inverted external RX clock |
| 85 | * |
| 86 | * RMII: |
| 87 | * tx | clk_sel: 0 - RMII clock |
| 88 | * 1 - Inverted RMII clock |
| 89 | * rx | clk_sel: 0 - RMII clock |
| 90 | * 1 - Inverted RMII clock |
| 91 | * |
| 92 | */ |
| 93 | #if 0 |
| 94 | /* enable 1000M phy*/ |
| 95 | 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 96 | phy-handle = <&phy3>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 97 | #else |
| 98 | /* enable 100M phy*/ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 99 | 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */ |
hj.shao | fe1632a | 2025-06-05 00:19:33 -0700 | [diff] [blame] | 100 | phy-handle = <&phy0>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 101 | #endif |
| 102 | /* enable fix link for ethernet switch */ |
| 103 | /* |
| 104 | fixed-link { |
| 105 | speed = <100>; |
| 106 | full-duplex; |
| 107 | phy-mode = "rmii"; |
| 108 | }; |
| 109 | */ |
| 110 | |
| 111 | mdio: mdio-bus { |
| 112 | #address-cells = <0x1>; |
| 113 | #size-cells = <0x0>; |
| 114 | /* YT8521 10M/100M/100OM 1.8V RGMII PHY */ |
| 115 | phy0: phy@0 { |
| 116 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 117 | device_type = "ethernet-phy"; |
| 118 | reg = <0x0>; /* set phy address*/ |
hj.shao | f72d6ff | 2025-06-10 04:34:26 -0700 | [diff] [blame^] | 119 | rst-gpio = <&gpio 42 0>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 120 | phy-mode = "rgmii"; |
hj.shao | fe1632a | 2025-06-05 00:19:33 -0700 | [diff] [blame] | 121 | // tx_rx_delay = <0xb 0x0>; /* 150ps per step*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | /* YT8512B 10M/100M 3.3V RMII PHY */ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 125 | // phy3: phy@3 { |
| 126 | // compatible = "ethernet-phy-ieee802.3-c22"; |
| 127 | // device_type = "ethernet-phy"; |
| 128 | // reg = <0x3>; /* set phy address*/ |
| 129 | // phy-mode = "rmii"; |
| 130 | // driver_strength = <0x3>; |
| 131 | // }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 132 | |
| 133 | /* IP175D 10M/100M 3.3V RMII SWITCH */ |
| 134 | phy1: phy@1 { |
| 135 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 136 | device_type = "ethernet-phy"; |
| 137 | reg = <0x1>; /* set phy address*/ |
| 138 | phy-mode = "rmii"; |
| 139 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 140 | |
| 141 | |
| 142 | /* jl 3103 phy */ |
| 143 | phy3: phy@3 { |
| 144 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 145 | device_type = "ethernet-phy"; |
| 146 | reg = <0x3>; /* set phy address*/ |
| 147 | phy-mode = "rgmii-id"; |
| 148 | lynq,jl3103=<100 0>; |
| 149 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 150 | }; |
| 151 | }; |
| 152 | qspi: spi@0xd420b000 { |
| 153 | asr,qspi-freq = <78000000>; |
| 154 | status = "okay"; |
| 155 | }; |
| 156 | /* SD card */ |
| 157 | sdh0: sdh@d4280000 { |
| 158 | pinctrl-names = "default", "slow", "fast", "sleep"; |
| 159 | pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>; |
| 160 | pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>; |
| 161 | pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>; |
| 162 | pinctrl-3 = <&sdh0_pmx_cd_wakeup>; |
| 163 | /* |
| 164 | * Genernal use, juse set vmmc-supply and vqmmc-supply |
| 165 | * vmmc-supply = <&supply1> |
| 166 | * vqmmc-supply = <&supply2> |
| 167 | * |
| 168 | * For compatibility, to select one from two supply source |
| 169 | * vmmc-supply = <&supply1 &supply1_backup>; |
| 170 | * vqmmc-supply = <&supply2 &supply2_backup>; |
| 171 | * vmmc2-supply = <&supply1_backup &supply1>; |
| 172 | * vqmmc2-supply = <&supply2_backup &supply2>; |
| 173 | */ |
| 174 | vmmc-supply = <&vcc_sdh1>; |
zw.wang | 5deb3e8 | 2025-05-30 11:29:23 +0800 | [diff] [blame] | 175 | vqmmc-supply = <&pm802ldo6 &pm803ldo8>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 176 | #ifndef CONFIG_ASR_DSDS |
| 177 | vmmc2-supply = <&vcc_sdh1 &pm802ldo4>; |
| 178 | vqmmc2-supply = <&pm803ldo8 &pm802ldo6>; |
| 179 | #endif |
| 180 | bus-width = <4>; |
| 181 | no-mmc; |
| 182 | no-sdio; |
| 183 | /*non-removable; |
| 184 | broken-cd;*/ |
| 185 | wp-inverted; |
| 186 | asr,sdh-pm-runtime-en; |
| 187 | asr,sdh-host-caps-disable = <(MMC_CAP_UHS_SDR104)>; |
| 188 | #if 1 /* CD via gpio */ |
zw.wang | 5deb3e8 | 2025-05-30 11:29:23 +0800 | [diff] [blame] | 189 | //cd-gpios = <&gpio 90 1>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 190 | asr,sdh-quirks2 = <( |
| 191 | SDHCI_QUIRK2_SET_AIB_MMC | |
| 192 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
| 193 | )>; |
| 194 | asr,sdh-host-caps = <( |
| 195 | MMC_CAP_CD_WAKE |
| 196 | )>; |
| 197 | asr,sdh-quirks = <( |
| 198 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
| 199 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
| 200 | )>; |
| 201 | #else /* CD via SDH */ |
| 202 | asr,sdh-quirks = <( |
| 203 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
| 204 | )>; |
| 205 | asr,sdh-quirks2 = <( |
| 206 | SDHCI_QUIRK2_SET_AIB_MMC | |
| 207 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
| 208 | SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON |
| 209 | )>; |
| 210 | #endif |
| 211 | /* prop "sdh-dtr-data": |
| 212 | <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */ |
| 213 | asr,sdh-dtr-data = |
| 214 | <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>, |
| 215 | <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>, |
| 216 | <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>, |
| 217 | <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 0>, |
| 218 | <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>, |
| 219 | <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_104M 0 0 0 0>; |
| 220 | status = "okay"; |
| 221 | }; |
| 222 | |
| 223 | /* SDIO */ |
| 224 | sdh1: sdh@d4280800 { |
| 225 | pinctrl-names = "default", "fast", "sleep"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 226 | pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2>; |
| 227 | pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast>; |
| 228 | /* pinctrl-2 = <&sdh1_pmx_edge_wakeup>;*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 229 | bus-width = <4>; |
| 230 | no-mmc; |
| 231 | no-sd; |
| 232 | non-removable; |
| 233 | keep-power-in-suspend; |
| 234 | enable-sdio-wakeup; |
| 235 | /* clk-scaling-config: |
| 236 | <up_threshold down_threshold polling_interval> */ |
| 237 | clk-scaling-config = <25 12 200>; |
| 238 | min-ddr-qos = <156000 312000 400000>; |
| 239 | asr,sdh-pm-runtime-en; |
| 240 | asr,sdh-quirks = <( |
| 241 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
| 242 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
| 243 | )>; |
| 244 | asr,sdh-quirks2 = <( |
| 245 | SDHCI_QUIRK2_NO_TIMER_RETUNING | |
| 246 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
| 247 | SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON |
| 248 | )>; |
| 249 | asr,sdh-pm-caps = <(MMC_PM_KEEP_POWER)>; |
| 250 | asr,sdh-host-caps2 = <( |
| 251 | MMC_CAP2_ONLY_1_8V | |
| 252 | MMC_CAP2_DISABLE_PROBE_CDSCAN | |
| 253 | MMC_CAP2_CLK_SCALE | |
| 254 | MMC_CAP2_BUS_CLK_NO_SCALE |
| 255 | )>; |
| 256 | /* prop "sdh-dtr-data": |
| 257 | <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */ |
| 258 | asr,sdh-dtr-data = |
| 259 | <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>, |
| 260 | <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>, |
| 261 | <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>, |
| 262 | <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_83M PXA_SDH_DTR_83M 0 0 0 3>, |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 263 | //<PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>, |
| 264 | <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_52M PXA_SDH_DTR_52M 0 0 0 0>, |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 265 | <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>; |
| 266 | status = "okay"; |
| 267 | }; |
| 268 | pcie0: pcie@0xd4288000{ |
| 269 | reset-gpios = <&gpio 42 0 >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 270 | status = "disbabled"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 271 | }; |
| 272 | pciephy0: pcie-phy@d4206000 { |
| 273 | status = "okay"; |
| 274 | }; |
| 275 | }; |
| 276 | |
| 277 | apb@d4000000 { |
| 278 | ssp_dai1: pxa-ssp-dai@1 { |
| 279 | compatible = "asr,pxa-ssp-dai"; |
| 280 | reg = <0x1 0x0>; |
| 281 | |
| 282 | port = <&ssp1>; |
| 283 | pinctrl-names = "default","ssp"; |
| 284 | pinctrl-0 = <&i2s_gpio>; |
| 285 | pinctrl-1 = <&i2s_func>; |
| 286 | ssp-gpio = <&gpio 25 0 &gpio 26 0 &gpio 27 0 &gpio 28 0>; |
| 287 | |
| 288 | dmas = <&pdma0 54 1 |
| 289 | &pdma0 55 1>; |
| 290 | dma-names = "rx", "tx"; |
| 291 | |
| 292 | platform_driver_name = "pdma_platform"; |
| 293 | burst_size = <4>; |
| 294 | playback_period_bytes = <2048>; |
| 295 | playback_buffer_bytes = <4096>; |
| 296 | capture_period_bytes = <2048>; |
| 297 | capture_buffer_bytes = <4096>; |
| 298 | }; |
| 299 | mfpr: mfpr@d401e000 { |
| 300 | status = "okay"; |
| 301 | /* intend to replace lpm-board-cfg |
| 302 | no-apbsd-in-d1pp = <0x1>; //"wakeup-state-d1pp" |
| 303 | pin1:pin1@d401e01B0 { |
| 304 | offset = <0x1B0>; |
| 305 | udr-cfg = <0xA040>; |
| 306 | }; |
| 307 | pin2:pin2@d401e01B4 { |
| 308 | offset = <0x1B4>; |
| 309 | udr-cfg = <0xA040>; |
| 310 | }; |
| 311 | */ |
| 312 | }; |
| 313 | timer0: timer@d4014000 { |
| 314 | status = "okay"; |
| 315 | }; |
| 316 | uart1: uart@d4017000 { /* nezhas evb use ap uart */ |
| 317 | pinctrl-names = "default","sleep"; |
| 318 | pinctrl-0 = <&uart1_pmx_func1 &uart1_pmx_func2>; |
| 319 | pinctrl-1 = <&uart1_pmx_func1_sleep &uart1_pmx_func2>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 320 | //edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 321 | status = "okay"; |
| 322 | }; |
| 323 | uart2: uart@d4036000 { |
| 324 | pinctrl-names = "default"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 325 | pinctrl-0 = <&gps_pmx_uart_rxd &gps_pmx_uart_txd &gps_pmx_func_cts_rts>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 326 | status = "okay"; |
| 327 | }; |
| 328 | uart3: uart@d4018000 { |
| 329 | pinctrl-names = "default"; |
| 330 | pinctrl-0 = <&uart3_pmx_func>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 331 | status = "okay"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 332 | }; |
| 333 | uart4: uart@d401f000 { |
| 334 | pinctrl-names = "default"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 335 | pinctrl-0 = <&uart4_pmx_func>; /*BAUD :9600*/ |
| 336 | /*pinctrl-0 = <&uart4_pmx_func_rxd &uart4_pmx_func_txd &uart4_pmx_func_cts_rts>;*/ |
| 337 | status = "okay"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 338 | }; |
| 339 | rtc: rtc@d4010000 { |
| 340 | status = "okay"; |
| 341 | }; |
| 342 | pmx: pinmux@d401e000 { |
| 343 | /* pin base = base_addr / 4, nr pins & gpio function */ |
| 344 | pinctrl-single,gpio-range = < |
| 345 | /* |
| 346 | * GPIO number is hardcoded for range at here. |
| 347 | * In gpio chip, GPIO number is not hardcoded for range. |
| 348 | * Since one gpio pin may be routed to multiple pins, |
| 349 | * define these gpio range in pxa910-dkb.dts not pxa910.dtsi. |
| 350 | */ |
| 351 | /*&range 80 4 0 */ /* GPIO25 ~ GPIO28 */ |
| 352 | &range 55 32 0 /* GPIO0 ~ GPIO31 */ |
| 353 | &range 87 32 0 /* GPIO32 ~ GPIO63 */ |
| 354 | &range 119 32 0 /* GPIO64 ~ GPIO95 */ |
| 355 | &range 151 32 0 /* GPIO96 ~ GPIO127 */ |
| 356 | >; |
| 357 | |
| 358 | ssp0_pmx_func: ssp0_pmx_func { |
| 359 | pinctrl-single,pins = < |
| 360 | GPIO36 AF1 /* TXD */ |
| 361 | GPIO35 AF1 /* RXD */ |
| 362 | GPIO34 AF1 /* FRM */ |
| 363 | /*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */ |
| 364 | GPIO33 AF1 /* SCLK */ |
| 365 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 366 | DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage |
| 367 | }; |
| 368 | ssp2_pmx_func: ssp2_pmx_func { |
| 369 | pinctrl-single,pins = < |
| 370 | GPIO37 AF3 /* TXD */ |
| 371 | GPIO38 AF3 /* SCLK */ |
| 372 | GPIO39 AF3 /* FRM */ |
| 373 | GPIO40 AF3 /* RXD */ |
| 374 | >; |
| 375 | DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 376 | }; |
| 377 | lcd_bl_func: lcd_bl_func { |
| 378 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 379 | /* VCXO_OUT AF1 GPIO126, lcd bl */ |
| 380 | /* GPIO24 AF0 reset */ |
| 381 | /* GPIO22 AF0 lcd d/c */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 382 | >; |
| 383 | MFP_DEFAULT; |
| 384 | }; |
| 385 | uart1_pmx_func1: uart1_pmx_func1 { |
| 386 | pinctrl-single,pins = < |
| 387 | GPIO29 AF1 |
| 388 | >; |
| 389 | MFP_DEFAULT; |
| 390 | }; |
| 391 | uart1_pmx_func2: uart1_pmx_func2 { |
| 392 | pinctrl-single,pins = < |
| 393 | GPIO30 AF1 |
| 394 | >; |
| 395 | MFP_DEFAULT; |
| 396 | }; |
| 397 | uart1_pmx_func1_sleep: uart1_pmx_func1_sleep { |
| 398 | pinctrl-single,pins = < |
| 399 | GPIO29 AF1 |
| 400 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 401 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 402 | }; |
| 403 | twsi0_pmx_func: twsi0_pmx_func { |
| 404 | pinctrl-single,pins = < |
| 405 | GPIO49 AF1 |
| 406 | GPIO50 AF1 |
| 407 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 408 | DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 409 | }; |
| 410 | twsi0_pmx_gpio: twsi0_pmx_gpio { |
| 411 | pinctrl-single,pins = < |
| 412 | GPIO49 AF0 |
| 413 | GPIO50 AF0 |
| 414 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 415 | DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 416 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 417 | #if 1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 418 | twsi1_pmx_func: twsi1_pmx_func { |
| 419 | pinctrl-single,pins = < |
| 420 | GPIO10 AF1 |
| 421 | GPIO11 AF1 |
| 422 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 423 | DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 424 | }; |
| 425 | twsi1_pmx_gpio: twsi1_pmx_gpio { |
| 426 | pinctrl-single,pins = < |
| 427 | GPIO10 AF0 |
| 428 | GPIO11 AF0 |
| 429 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 430 | DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 431 | }; |
| 432 | #endif |
| 433 | /* no pull, no LPM */ |
| 434 | dvc_pmx_func: dvc_pmx_func { |
| 435 | /* hw-dvc */ |
| 436 | pinctrl-single,pins = < |
| 437 | TDS_DIO0 AF0 |
| 438 | TDS_DIO1 AF0 |
| 439 | >; |
| 440 | DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| 441 | }; |
| 442 | leds_pmx_func: leds_pmx_func { |
| 443 | pinctrl-single,pins = < |
| 444 | DF_IO10 AF1 |
| 445 | DF_IO11 AF1 |
| 446 | DF_IO12 AF1 |
| 447 | >; |
| 448 | DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| 449 | }; |
| 450 | |
| 451 | gps_pmx_onoff: gps_pmx_onoff { |
| 452 | pinctrl-single,pins = < |
| 453 | TDS_TXREV AF1 |
| 454 | >; |
| 455 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 456 | }; |
| 457 | gps_pmx_reset: gps_pmx_reset { |
| 458 | pinctrl-single,pins = < |
| 459 | TDS_RXON AF1 |
| 460 | >; |
| 461 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 462 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 463 | |
| 464 | //zqy |
| 465 | gnss_clk_on: gnss_clk_on { |
| 466 | pinctrl-single,pins = < |
| 467 | GPIO43 AF2 /*32K CLK */ |
| 468 | |
| 469 | /*VCXO_REQ AF1 GPIO[125] GPS_WAKE_HOST */ |
| 470 | GPIO47 AF0 /* HOST_WAKE_GPS */ |
| 471 | GPIO45 AF0 /*RESET */ |
| 472 | CLK_REQ AF1 /*sleep en*/ |
| 473 | |
| 474 | >; |
| 475 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW; |
| 476 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 477 | gps_pmx_uart_rxd: gps_pmx_uart_rxd { |
| 478 | /* gps dedicated uart */ |
| 479 | pinctrl-single,pins = < |
| 480 | GPIO51 AF1 |
| 481 | GPIO32 AF1 |
| 482 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 483 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 484 | }; |
| 485 | gps_pmx_uart_txd: gps_pmx_uart_txd { |
| 486 | /* gps dedicated uart */ |
| 487 | pinctrl-single,pins = < |
| 488 | GPIO52 AF1 |
| 489 | GPIO31 AF1 |
| 490 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 491 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 492 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 493 | gps_pmx_func_cts_rts: gps_pmx_func_cts_rts { |
| 494 | pinctrl-single,pins = < |
| 495 | GPIO31 AF1 /* cts */ |
| 496 | GPIO32 AF1 /* rts */ |
| 497 | >; |
| 498 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 499 | }; |
| 500 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 501 | uart3_pmx_func: uart3_pmx_func { |
| 502 | pinctrl-single,pins = < |
| 503 | GPIO53 AF1 /* RX */ |
yu.dong | ca721ca | 2025-06-04 07:21:21 -0700 | [diff] [blame] | 504 | /* GPIO54 AF1 TX */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 505 | >; |
| 506 | MFP_DEFAULT; |
| 507 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 508 | |
| 509 | |
| 510 | uart4_pmx_func_rxd: uart4_pmx_func_rxd { |
| 511 | pinctrl-single,pins = < |
| 512 | GPIO37 AF2 |
| 513 | GPIO40 AF2 |
| 514 | >; |
| 515 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 516 | }; |
| 517 | uart4_pmx_func_txd: uart4_pmx_func_txd { |
| 518 | pinctrl-single,pins = < |
| 519 | GPIO38 AF2 |
| 520 | GPIO39 AF2 |
| 521 | >; |
| 522 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 523 | }; |
| 524 | |
| 525 | uart4_pmx_func_cts_rts: uart4_pmx_func_cts_rts { |
| 526 | pinctrl-single,pins = < |
| 527 | GPIO39 AF2 |
| 528 | GPIO40 AF2 |
| 529 | >; |
| 530 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 531 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 532 | uart4_pmx_func: uart4_pmx_func { |
| 533 | pinctrl-single,pins = < |
| 534 | GPIO44 AF1 /* RX */ |
| 535 | GPIO45 AF1 /* TX */ |
| 536 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 537 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 538 | }; |
| 539 | panel_rst_func: panel_rst_func { |
| 540 | pinctrl-single,pins = < |
| 541 | DF_nCS1 AF1 |
| 542 | >; |
| 543 | DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| 544 | }; |
| 545 | |
| 546 | sd_ldo_en: sd_ldo_en { |
| 547 | pinctrl-single,pins = < |
| 548 | GPIO45 AF0 |
| 549 | >; |
| 550 | MFP_PULL_DOWN; |
| 551 | }; |
| 552 | sdh0_pmx_func1: sdh0_pmx_func1 { |
| 553 | pinctrl-single,pins = < |
| 554 | MMC1_DAT3 AF0 |
| 555 | MMC1_DAT2 AF0 |
| 556 | MMC1_DAT1 AF0 |
| 557 | MMC1_DAT0 AF0 |
| 558 | MMC1_CMD AF0 |
| 559 | >; |
| 560 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 561 | }; |
| 562 | sdh0_pmx_func2: sdh0_pmx_func2 { |
| 563 | pinctrl-single,pins = < |
| 564 | MMC1_CLK AF0 |
| 565 | >; |
| 566 | DS_MEDIUM;PULL_NONE;EDGE_NONE; |
| 567 | }; |
| 568 | sdh0_pmx_func3: sdh0_pmx_func3 { |
| 569 | pinctrl-single,pins = < |
| 570 | MMC1_CD AF1 |
| 571 | >; |
| 572 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 573 | }; |
| 574 | sdh0_pmx_cd_wakeup: sdh0_pmx_func1_cd_wakeup { |
| 575 | pinctrl-single,pins = < |
| 576 | MMC1_CD AF1 |
| 577 | >; |
| 578 | DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| 579 | }; |
| 580 | sdh0_pmx_func1_slow: sdh0_pmx_func1_slow { |
| 581 | pinctrl-single,pins = < |
| 582 | MMC1_DAT3 AF0 |
| 583 | MMC1_DAT2 AF0 |
| 584 | MMC1_DAT1 AF0 |
| 585 | MMC1_DAT0 AF0 |
| 586 | MMC1_CMD AF0 |
| 587 | >; |
| 588 | DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 589 | }; |
| 590 | sdh0_pmx_func2_slow: sdh0_pmx_func2_slow { |
| 591 | pinctrl-single,pins = < |
| 592 | MMC1_CLK AF0 |
| 593 | >; |
| 594 | DS_FAST0;PULL_NONE;EDGE_NONE; |
| 595 | }; |
| 596 | sdh0_pmx_func1_fast: sdh0_pmx_func1_fast { |
| 597 | pinctrl-single,pins = < |
| 598 | MMC1_DAT3 AF0 |
| 599 | MMC1_DAT2 AF0 |
| 600 | MMC1_DAT1 AF0 |
| 601 | MMC1_DAT0 AF0 |
| 602 | MMC1_CMD AF0 |
| 603 | >; |
| 604 | DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 605 | }; |
| 606 | sdh0_pmx_func2_fast: sdh0_pmx_func2_fast { |
| 607 | pinctrl-single,pins = < |
| 608 | MMC1_CLK AF0 |
| 609 | >; |
| 610 | DS_FAST1;PULL_NONE;EDGE_NONE; |
| 611 | }; |
| 612 | sdh1_pmx_func1_fast: sdh1_pmx_func1_fast { |
| 613 | pinctrl-single,pins = < |
| 614 | TDS_DIO13 AF0 /* WLAN_DAT3 */ |
| 615 | TDS_DIO14 AF0 /* WLAN_DAT2 */ |
| 616 | TDS_DIO15 AF0 /* WLAN_DAT1 */ |
| 617 | TDS_DIO16 AF0 /* WLAN_DAT0 */ |
| 618 | TDS_DIO17 AF0 /* WLAN_CMD */ |
| 619 | >; |
| 620 | DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 621 | }; |
| 622 | sdh1_pmx_func2_fast: sdh1_pmx_func2_fast { |
| 623 | pinctrl-single,pins = < |
| 624 | TDS_DIO18 AF0 /* WLAN_CLK */ |
| 625 | >; |
| 626 | DS_FAST0;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 627 | }; |
| 628 | sdh1_pmx_func1: sdh1_pmx_func1 { |
| 629 | pinctrl-single,pins = < |
| 630 | TDS_DIO13 AF0 /* WLAN_DAT3 */ |
| 631 | TDS_DIO14 AF0 /* WLAN_DAT2 */ |
| 632 | TDS_DIO15 AF0 /* WLAN_DAT1 */ |
| 633 | TDS_DIO16 AF0 /* WLAN_DAT0 */ |
| 634 | TDS_DIO17 AF0 /* WLAN_CMD */ |
| 635 | >; |
| 636 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW; |
| 637 | }; |
| 638 | sdh1_pmx_func2: sdh1_pmx_func2 { |
| 639 | pinctrl-single,pins = < |
| 640 | TDS_DIO18 AF0 /* WLAN_CLK */ |
| 641 | >; |
| 642 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_LOW; |
| 643 | }; |
| 644 | sdh1_pmx_func3: sdh1_pmx_func3 { |
| 645 | pinctrl-single,pins = < |
| 646 | GPIO10 AF0 /* VCXO_REQ AF1 WLAN_WAKE_HOST */ |
| 647 | >; |
| 648 | MFP_PULL_DOWN; |
| 649 | }; |
| 650 | sdh1_pmx_edge_wakeup: sdh1_pmx_edge_wakeup { |
| 651 | pinctrl-single,pins = < |
| 652 | GPIO10 AF0 /* VCXO_REQ AF1 */ |
| 653 | >; |
| 654 | DS_MEDIUM;PULL_DOWN;EDGE_RISE;SL_NORMAL; |
| 655 | }; |
| 656 | sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off { |
| 657 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 658 | /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */ |
| 659 | /* GPIO08 AF0 GPIO32 AF0 LDO_EN */ |
| 660 | MMC1_CD AF1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 661 | >; |
| 662 | MFP_PULL_DOWN; |
| 663 | }; |
| 664 | sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on { |
| 665 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 666 | /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */ |
| 667 | /* GPIO08 AF0 GPIO32 AF0 LDO_EN */ |
| 668 | MMC1_CD AF1 |
| 669 | >; |
| 670 | MFP_PULL_UP; |
| 671 | }; |
| 672 | |
| 673 | |
| 674 | mbtk_sdh_pmx_off: mbtk_sdh_pmx_off { |
| 675 | pinctrl-single,pins = < |
| 676 | VCXO_REQ AF1 //gpio125 wlan en |
| 677 | GPIO123 AF1 //wlan pwr en |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 678 | /*VCXO_OUT AF1 /*gpio127 wifi wake*/ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 679 | >; |
| 680 | MFP_PULL_DOWN; |
| 681 | }; |
| 682 | mbtk_sdh_pmx_on: mbtk_sdh_pmx_on { |
| 683 | pinctrl-single,pins = < |
| 684 | VCXO_REQ AF1 //gpio125 wlan en |
| 685 | GPIO123 AF1 //wlan pwr en |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 686 | /*VCXO_OUT AF1 /*gpio127 wifi wake*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 687 | >; |
| 688 | MFP_PULL_UP; |
| 689 | }; |
| 690 | alc5616_pmx_func1: alc5616_pmx_func1 { |
| 691 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 692 | /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 693 | GPIO20 AF7 /* MCLK:I2S_SYSCLK */ |
| 694 | >; |
| 695 | MFP_DEFAULT; |
| 696 | }; |
| 697 | alc5616_pmx_func2: alc5616_pmx_func2 { |
| 698 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 699 | /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */ |
| 700 | GPIO20 AF7 /* MCLK:I2S_SYSCLK */ |
| 701 | >; |
| 702 | MFP_DEFAULT; |
| 703 | }; |
| 704 | |
| 705 | es8311_pa_func1: es8311_pa_func1 { |
| 706 | pinctrl-single,pins = < |
| 707 | GPIO20 AF7 /* MCLK:I2S_SYSCLK */ |
yu.dong | ca721ca | 2025-06-04 07:21:21 -0700 | [diff] [blame] | 708 | GPIO54 AF0 |
| 709 | GPIO24 AF0 |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 710 | >; |
| 711 | MFP_DEFAULT; |
| 712 | }; |
| 713 | es8311_pa_func2: es8311_pa_func2 { |
| 714 | pinctrl-single,pins = < |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 715 | GPIO20 AF7 /* MCLK:I2S_SYSCLK */ |
yu.dong | ca721ca | 2025-06-04 07:21:21 -0700 | [diff] [blame] | 716 | GPIO54 AF0 |
| 717 | GPIO24 AF0 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 718 | >; |
| 719 | MFP_DEFAULT; |
| 720 | }; |
| 721 | audio_pa_pmx_func: audio_pa_pmx_func { |
| 722 | pinctrl-single,pins = < |
| 723 | GPIO14 AF0 /* PA */ |
| 724 | >; |
| 725 | MFP_DEFAULT; |
| 726 | }; |
| 727 | ecall_pmx_func: ecall_pmx_func { |
| 728 | pinctrl-single,pins = < |
| 729 | GPIO08 AF0 /* auto mode ecall */ |
| 730 | GPIO09 AF0 /* manual mode ecall */ |
| 731 | >; |
| 732 | MFP_DEFAULT; |
| 733 | }; |
| 734 | slic_pmx_func1: slic_pmx_func1 { |
| 735 | pinctrl-single,pins = < |
| 736 | GPIO20 AF0 /* SLIC_INT, GPIO20 */ |
| 737 | VCXO_OUT AF1 /* GPIO127, SLIC_3V3LDO_EN/LCD_BK_EN */ |
| 738 | >; |
| 739 | MFP_DEFAULT; |
| 740 | }; |
| 741 | slic_pmx_func2: slic_pmx_func2 { |
| 742 | pinctrl-single,pins = < |
| 743 | GPIO21 AF0 /* SLIC_RESET, GPIO21 */ |
| 744 | >; |
| 745 | MFP_DEFAULT; |
| 746 | }; |
| 747 | slic_pmx_func1_sleep: slic_pmx_func1_sleep { |
| 748 | pinctrl-single,pins = < |
| 749 | GPIO20 AF0 /* SLIC_INT, GPIO20 */ |
| 750 | >; |
| 751 | DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| 752 | }; |
| 753 | |
| 754 | otg_vbus_func: otg_vbus_func { |
| 755 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 756 | /* VBUS_DRV AF1 GPIO[122] */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 757 | >; |
| 758 | DS_MEDIUM;PULL_DOWN;EDGE_NONE; |
| 759 | }; |
| 760 | |
| 761 | emac_pmx_func0: emac_pmx_func0 { |
| 762 | pinctrl-single,pins = < |
| 763 | GPIO00 AF1 /* GMAC1_RX_DV */ |
| 764 | GPIO01 AF1 /* GMAC1_RX_D0 */ |
| 765 | GPIO02 AF1 /* GMAC1_RX_D1 */ |
| 766 | GPIO03 AF1 /* GMAC1_RX_CLK */ |
| 767 | /* GPIO04 AF1 GMAC1_RX_D2 */ |
| 768 | /* GPIO05 AF1 GMAC1_RX_D3 */ |
| 769 | GPIO06 AF1 /* GMAC1_TX_D0 */ |
| 770 | GPIO07 AF1 /* GMAC1_TX_D1 */ |
| 771 | /* GPIO12 AF1 GMAC1_TX_CLK */ |
| 772 | /* GPIO13 AF1 GMAC1_TX_D2 */ |
| 773 | /* GPIO14 AF1 GMAC1_TX_D3 */ |
| 774 | GPIO15 AF1 /* GMAC1_TX_EN */ |
| 775 | GPIO16 AF1 /* GMAC1_TX_MDC */ |
| 776 | /* GPIO17 AF1 GMAC1_TX_MDIO */ |
| 777 | >; |
| 778 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 779 | }; |
| 780 | emac_pmx_func1: emac_pmx_func1 { |
| 781 | pinctrl-single,pins = < |
| 782 | GPIO04 AF1 /* GMAC1_RX_D2 */ |
| 783 | GPIO05 AF1 /* GMAC1_RX_D3 */ |
| 784 | GPIO12 AF1 /* GMAC1_TX_CLK */ |
| 785 | GPIO13 AF1 /* GMAC1_TX_D2 */ |
| 786 | GPIO14 AF1 /* GMAC1_TX_D3 */ |
| 787 | >; |
| 788 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 789 | }; |
| 790 | emac_pmx_func2: emac_pmx_func2 { |
| 791 | pinctrl-single,pins = < |
| 792 | GPIO17 AF1 /* GMAC1_TX_MDIO */ |
| 793 | GPIO18 AF1 /* GMAC1_TX_INT_N */ |
| 794 | >; |
| 795 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 796 | }; |
| 797 | emac_pmx_func3: emac_pmx_func3 { |
| 798 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 799 | GPIO42 AF0 /* RESET */ |
| 800 | /* GPIO40 AF0 LDO_EN */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 801 | >; |
| 802 | DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| 803 | }; |
| 804 | usim1_pmx_func: usim1_pmx_func { |
| 805 | pinctrl-single,pins = < |
yq.wang | 107f986 | 2025-05-12 15:44:50 +0800 | [diff] [blame] | 806 | PRI_TCK AF1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 807 | >; |
| 808 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 809 | }; |
| 810 | usim1_pmx_func_sleep: usim1_pmx_func_sleep { |
| 811 | pinctrl-single,pins = < |
yq.wang | 107f986 | 2025-05-12 15:44:50 +0800 | [diff] [blame] | 812 | PRI_TCK AF1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 813 | >; |
| 814 | DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| 815 | }; |
| 816 | usim2_pmx_func: usim2_pmx_func { |
| 817 | pinctrl-single,pins = < |
| 818 | GPIO44 AF0 |
| 819 | >; |
| 820 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 821 | }; |
| 822 | usim2_pmx_func_sleep: usim2_pmx_func_sleep { |
| 823 | pinctrl-single,pins = < |
| 824 | GPIO44 AF0 |
| 825 | >; |
| 826 | DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| 827 | }; |
| 828 | pcie_pmx_pd_rst_off: pcie_pmx_pd_rst_off { |
| 829 | pinctrl-single,pins = < |
| 830 | GPIO42 AF0 /* PERST_N */ |
| 831 | GPIO24 AF0 /* DC_EN */ |
| 832 | >; |
| 833 | MFP_PULL_DOWN; |
| 834 | }; |
| 835 | pcie_pmx_pd_rst_on: pcie_pmx_pd_rst_on { |
| 836 | pinctrl-single,pins = < |
| 837 | GPIO42 AF0 /* PERST_N */ |
| 838 | GPIO24 AF0 /* DC_EN */ |
| 839 | >; |
| 840 | MFP_PULL_UP; |
| 841 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 842 | pin_func_work: pin_func_work { |
| 843 | pinctrl-single,pins = < |
| 844 | |
| 845 | GPIO08 AF0 /*T108 status led* / |
| 846 | |
| 847 | VBUS_DRV AF2 /*32k*/ |
| 848 | |
| 849 | |
| 850 | GPIO46 AF0 /*wifi en*/ |
| 851 | |
| 852 | GPIO19 AF0 /*bt en*/ |
| 853 | |
| 854 | >; |
| 855 | MFP_DEFAULT; |
| 856 | }; |
| 857 | |
| 858 | |
| 859 | sc_ext_int0: sc_ext_int0 { |
| 860 | pinctrl-single,pins = < |
| 861 | GPIO21 AF0 |
| 862 | >; |
| 863 | DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL; |
| 864 | }; |
| 865 | sc_ext_int1: sc_ext_int1 { |
| 866 | pinctrl-single,pins = < |
| 867 | GPIO22 AF0 |
| 868 | >; |
| 869 | MFP_DEFAULT; |
| 870 | }; |
| 871 | |
| 872 | sc_ext_int2: sc_ext_int2 { |
| 873 | pinctrl-single,pins = < |
| 874 | GPIO23 AF0 |
| 875 | >; |
| 876 | MFP_DEFAULT; |
| 877 | }; |
| 878 | |
| 879 | |
| 880 | sc_ext_int3: sc_ext_int3 { |
| 881 | pinctrl-single,pins = < |
| 882 | GPIO24 AF0 |
| 883 | >; |
| 884 | MFP_DEFAULT; |
| 885 | }; |
| 886 | |
| 887 | |
| 888 | mbtk_plat_irq_func: mbtk_plat_irq_func { |
| 889 | pinctrl-single,pins = < |
| 890 | |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 891 | /*GPIO21 AF0 |
| 892 | GPIO22 AF0 */ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 893 | GPIO23 AF0 |
yu.dong | ca721ca | 2025-06-04 07:21:21 -0700 | [diff] [blame] | 894 | GPIO24 AF0 |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 895 | |
| 896 | >; |
| 897 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 898 | }; |
| 899 | mbtk_plat_irq_func_sleep: mbtk_plat_irq_func_sleep { |
| 900 | pinctrl-single,pins = < |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 901 | /*GPIO21 AF0 |
| 902 | GPIO22 AF0*/ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 903 | GPIO23 AF0 |
yu.dong | ca721ca | 2025-06-04 07:21:21 -0700 | [diff] [blame] | 904 | GPIO24 AF0 |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 905 | >; |
| 906 | DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL; |
| 907 | }; |
| 908 | |
| 909 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 910 | gpiokey_pmx_func: gpiokey_pmx_func { |
| 911 | pinctrl-single,pins = < |
| 912 | GPIO09 AF0 |
| 913 | >; |
| 914 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 915 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 916 | |
| 917 | wake_pmx_func1: wake_pmx_func1 { |
| 918 | pinctrl-single,pins = < |
| 919 | USB_ID AF1 |
| 920 | >; |
| 921 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 922 | }; |
| 923 | |
hong.liu | f241688 | 2025-05-23 20:41:06 -0700 | [diff] [blame] | 924 | led_pmx_func1: led_pmx_func1 { |
| 925 | pinctrl-single,pins = < |
| 926 | GPIO08 AF0 |
| 927 | >; |
| 928 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 929 | }; |
| 930 | |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 931 | |
| 932 | wake_pmx_func: wake_pmx_func { |
| 933 | pinctrl-single,pins = < |
| 934 | PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/ |
| 935 | |
| 936 | PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/ |
| 937 | GPIO41 AF0 |
| 938 | PRI_TDO AF1 /*GPIO120*/ |
| 939 | |
| 940 | |
| 941 | >; |
| 942 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 943 | }; |
| 944 | wake_pmx_func_sleep: wake_pmx_func_sleep { |
| 945 | pinctrl-single,pins = < |
| 946 | PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/ |
| 947 | |
| 948 | PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/ |
| 949 | GPIO41 AF0 |
| 950 | PRI_TDO AF1 /*GPIO120*/ |
| 951 | |
| 952 | >; |
| 953 | DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL; |
| 954 | }; |
| 955 | usb_id_pinmux: usb_id_pinmux { |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 956 | pinctrl-single,pins = < |
| 957 | USB_ID AF1/* usbid-gpio99 */ |
| 958 | >; |
| 959 | DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE; |
| 960 | }; |
| 961 | usb_id_pinmux_slp: usb_id_pinmux_slp { |
| 962 | pinctrl-single,pins = < |
| 963 | USB_ID AF1 /* usbid-gpio99 */ |
| 964 | >; |
| 965 | DS_MEDIUM;PULL_UP;EDGE_BOTH;LPM_NONE; |
| 966 | }; |
| 967 | usb_host_pinmux: usb_host_pinmux { |
| 968 | pinctrl-single,pins = < |
| 969 | VBUS_DRV AF1 /* gpio-122 */ |
| 970 | >; |
| 971 | DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE; |
| 972 | }; |
| 973 | i2s_func: i2s_func { |
| 974 | pinctrl-single,pins = < |
| 975 | GPIO25 AF2 |
| 976 | GPIO26 AF2 |
| 977 | GPIO27 AF2 |
| 978 | GPIO28 AF2 |
| 979 | >; |
| 980 | MFP_DEFAULT; |
| 981 | }; |
| 982 | i2s_gpio: i2s_gpio { |
| 983 | pinctrl-single,pins = < |
| 984 | GPIO25 AF0 |
| 985 | GPIO26 AF0 |
| 986 | GPIO27 AF0 |
| 987 | GPIO28 AF0 |
| 988 | >; |
| 989 | MFP_LPM_FLOAT; |
| 990 | }; |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 991 | sensors_int:sensors_int { |
| 992 | pinctrl-single,pins = < |
| 993 | GPIO22 AF0 |
| 994 | >; |
| 995 | MFP_PULL_DOWN; |
| 996 | }; |
| 997 | sensors_csb:sensors_csb { |
| 998 | pinctrl-single,pins = < |
| 999 | VCXO_OUT AF1 |
| 1000 | >; |
| 1001 | DS_MEDIUM;PULL_UP;EDGE_NONE; |
| 1002 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1003 | }; |
| 1004 | |
| 1005 | ssp0: spi@d401b000 { |
| 1006 | status = "okay"; |
| 1007 | pinctrl-names = "default"; |
| 1008 | pinctrl-0 = <&ssp0_pmx_func>; |
| 1009 | asr,spi-inc-mode; |
| 1010 | #ifdef CONFIG_FB_SPI_LCD |
| 1011 | /* this enhancemnet feature is not suitable for |
| 1012 | 3 line 9bits spi lcd. */ |
| 1013 | /* asr,ssp-enhancement; */ |
| 1014 | |
| 1015 | lcd: spidev@0 { |
| 1016 | #address-cells = <1>; |
| 1017 | #size-cells = <1>; |
| 1018 | compatible = "spilcd"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1019 | // pinctrl-names = "default"; |
| 1020 | // pinctrl-0 = <&lcd_bl_func>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1021 | reg = <0>; |
| 1022 | /* ST7735: need to set spi-max-frequency to 26M |
| 1023 | * ST7789V: can set spi-max-frequency to 52M |
| 1024 | */ |
| 1025 | spi-max-frequency = <26000000>; |
| 1026 | xres = <128>; |
| 1027 | yres = <128>; |
| 1028 | bits = <8>; /* 8: 4line, 9: 3line */ |
| 1029 | rst_gpio = <&gpio 24 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1030 | // bl_gpio = <&gpio 126 0>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1031 | rs_gpio = <&gpio 22 0>; |
| 1032 | /* if comment the following statement, it means |
| 1033 | * the avdd is sit on the "always-on" ldo. |
| 1034 | */ |
| 1035 | /* avdd-supply = <&LDO1>; */ |
| 1036 | }; |
| 1037 | #else |
| 1038 | /*cs-gpios = <&gpio 34 0>;*//* DXS101 Use the config of Cs-gpios */ |
| 1039 | slic: spidev@0{ |
| 1040 | #address-cells = <1>; |
| 1041 | #size-cells = <1>; |
| 1042 | compatible = "asr,slic"; |
| 1043 | reg = <0>; |
| 1044 | spi-cpol; |
| 1045 | spi-cpha; |
| 1046 | spi-max-frequency = <6500000>; |
| 1047 | }; |
| 1048 | #endif |
| 1049 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1050 | ssp2: spi@d401c000{ |
| 1051 | status = "okay"; |
| 1052 | pinctrl-names = "default"; |
| 1053 | pinctrl-0 = <&ssp2_pmx_func>; |
| 1054 | asr,spi-inc-mode; |
| 1055 | cs-gpios = <&gpio 39 0>; |
| 1056 | status = "okay"; |
| 1057 | mbtk: spidev@0{ |
| 1058 | compatible = "asr,spidev"; |
| 1059 | reg = <0>; |
| 1060 | status = "okay"; |
| 1061 | spi-cpol; |
| 1062 | spi-cpha; |
| 1063 | spi-max-frequency = <6500000>; |
| 1064 | }; |
| 1065 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1066 | twsi0: i2c@d4011000 { |
| 1067 | status= "okay"; |
| 1068 | alc5616@1b { |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1069 | status= "disabled"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1070 | compatible = "asrmicro,alc5616"; |
| 1071 | reg = <0x1b>; |
| 1072 | pinctrl-names = "default", "sleep"; |
| 1073 | pinctrl-0 = <&alc5616_pmx_func1>; |
| 1074 | pinctrl-1 = <&alc5616_pmx_func2>; |
| 1075 | clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>; |
| 1076 | clock-names = "i2s_sys_clk"; |
| 1077 | #if 0 |
| 1078 | 3V3-gpio = <&gpio 23 0>;/* CODEC_LDO_EN */ |
| 1079 | irq-gpio = <&gpio 24 0>;/* CODEC_IRQ for headset detection */ |
| 1080 | #else |
| 1081 | irq-gpio = <&gpio 8 0>;/* CODEC_IRQ for headset detection */ |
| 1082 | #endif |
| 1083 | }; |
| 1084 | |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1085 | nau8810@1a { |
| 1086 | compatible = "marvell,nau8810"; |
| 1087 | clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>; |
| 1088 | clock-names = "i2s_sys_clk"; |
| 1089 | |
| 1090 | |
| 1091 | pinctrl-names = "default"; |
| 1092 | pinctrl-0 = <&es8311_pa_func1>; |
| 1093 | pinctrl-1 = <&es8311_pa_func2>; |
| 1094 | reg = <0x1a>; |
| 1095 | status= "disabled"; |
| 1096 | }; |
| 1097 | |
| 1098 | es8311@18 { |
| 1099 | compatible = "ambarella,es8311"; |
| 1100 | reg = <0x18>; |
| 1101 | clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>; |
| 1102 | clock-names = "i2s_sys_clk"; |
| 1103 | |
| 1104 | pinctrl-names = "default"; |
| 1105 | pinctrl-0 = <&es8311_pa_func1>; |
| 1106 | pinctrl-1 = <&es8311_pa_func2>; |
| 1107 | |
| 1108 | // gpios = <&gpio 21 0>, |
| 1109 | // <&gpio 23 0>, |
| 1110 | // <&gpio 24 0>, |
| 1111 | // <&gpio 22 0>; |
| 1112 | |
| 1113 | status= "okay"; |
| 1114 | }; |
| 1115 | |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1116 | asm330lhhx-imu@0x6a { |
| 1117 | compatible = "st,asm330lhhx"; |
| 1118 | reg = <0x6b>; |
| 1119 | pinctrl-names = "default"; |
| 1120 | pinctrl-0 = <&sensors_int &sensors_csb>; |
| 1121 | interrupt-parent = <&gpio>; |
| 1122 | interrupts = <22 1>; |
| 1123 | //interrupts = <22>; |
| 1124 | vddio-supply = <&sensors_vddio>; |
| 1125 | //vdd-supply = <&sensors_vdd>; |
| 1126 | st,int-pin = <1>; |
| 1127 | //st,mlc-int-pin = <2>; |
| 1128 | mount-matrix = "1", "0", "0", |
| 1129 | "0", "1", "0", |
| 1130 | "0", "0", "1"; |
| 1131 | }; |
yu.dong | b39db3e | 2025-06-06 03:15:42 -0700 | [diff] [blame] | 1132 | /* AWINIC AW87XXX Smart K PA */ |
| 1133 | aw87xxx_pa@58 { |
| 1134 | compatible = "awinic,aw87xxx_pa"; |
| 1135 | reg = <0x58>; |
| 1136 | reset-gpio = <&gpio 24 0>; |
| 1137 | dev_index = < 0 >; |
| 1138 | status = "okay"; |
| 1139 | }; |
| 1140 | /* AWINIC AW87XXX Smart K PA End */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1141 | /* |
| 1142 | pmic4: 88pm805@38 { |
| 1143 | compatible = "marvell,88pm805"; |
| 1144 | reg = <0x38>; |
| 1145 | }; |
| 1146 | */ |
| 1147 | }; |
| 1148 | twsi1: i2c@d4010800 { |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1149 | #if 1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1150 | pinctrl-names = "default","gpio"; |
| 1151 | pinctrl-0 = <&twsi1_pmx_func>; |
| 1152 | pinctrl-1 = <&twsi1_pmx_gpio>; |
| 1153 | i2c-gpio = <&gpio 10 0 &gpio 11 0>; |
| 1154 | #endif |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1155 | status= "okay"; |
| 1156 | //nau8810@1a { |
| 1157 | // compatible = "marvell,nau8810"; |
| 1158 | // reg = <0x1a>; |
| 1159 | //}; |
| 1160 | |
| 1161 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1162 | }; |
| 1163 | twsi2: i2c@d4037000 { |
| 1164 | status = "okay"; |
| 1165 | |
| 1166 | pmic4: 88pm805@38 { |
| 1167 | compatible = "marvell,88pm805"; |
| 1168 | reg = <0x38>; |
| 1169 | }; |
| 1170 | |
| 1171 | pmic5: pm802@0 { |
| 1172 | compatible = "asr,pm802"; |
| 1173 | reg = <0x00>; |
| 1174 | interrupts = <4>; |
| 1175 | interrupt-parent = <&intc>; |
| 1176 | interrupt-controller; |
| 1177 | #interrupt-cells = <1>; |
| 1178 | chg_irq_from_exton; |
| 1179 | scs-int-active-high; |
| 1180 | battery { |
| 1181 | compatible = "asr,pm802-bat"; |
| 1182 | status = "disabled"; |
| 1183 | |
| 1184 | online-gpadc = <1>; |
| 1185 | temperature-gpadc = <1>; |
| 1186 | |
| 1187 | hi-volt-online = <1150>; /* mV */ |
| 1188 | lo-volt-online = <20>; /* mV */ |
| 1189 | hi-volt-temp = <1150>; /* mV */ |
| 1190 | lo-volt-temp = <200>; /* mV */ |
| 1191 | |
| 1192 | sw-fg-use-ntc; |
| 1193 | full-capacity = <2050>; /* mAh */ |
| 1194 | r1-resistor = <40>; /* mohm */ |
| 1195 | r2-resistor = <30>; /* mohm */ |
| 1196 | rs-resistor = <120>; /* mohm */ |
| 1197 | roff-resistor = <0>; /* mohm */ |
| 1198 | roff-initial-resistor = <0>; /* mohm */ |
| 1199 | |
| 1200 | times-in-zero-degree = <1>; |
| 1201 | offset-in-zero-degree = <0>; |
| 1202 | |
| 1203 | times-in-ten-degree = <2>; |
| 1204 | offset-in-ten-degree = <100>; |
| 1205 | |
| 1206 | power-off-threshold = <3350>; /* mV */ |
| 1207 | safe-power-off-threshold = <3200>; /* mV */ |
| 1208 | |
| 1209 | online-gp-bias-curr = <11>; /* uA */ |
| 1210 | |
| 1211 | soc-ramp-up-interval = <150>; /* s */ |
| 1212 | /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */ |
| 1213 | tbat-threshold = <20 0 10 40 45 55>; /* ohm */ |
| 1214 | ntc-table-size = <88>; |
| 1215 | stop-chg-for-vbatmeas; |
| 1216 | /* -24C, -23C, ..., 62C, 63C */ |
| 1217 | ntc-table = < |
| 1218 | 89680 85130 80840 76790 72970 69360 65960 62740 |
| 1219 | 59700 56830 54130 51530 49100 46800 44610 42550 |
| 1220 | 40590 38730 36970 35300 33710 32210 30780 29420 |
| 1221 | 28130 26910 25750 24640 23590 22580 21630 20720 |
| 1222 | 19860 19030 18250 17500 16790 16110 15460 14840 |
| 1223 | 14250 13690 13150 12640 12150 11680 11230 10800 |
| 1224 | 10390 10000 9620 9270 8920 8590 8280 7980 |
| 1225 | 7690 7410 7150 6890 6650 6410 6190 5970 |
| 1226 | 5770 5570 5380 5190 5020 4850 4680 4530 |
| 1227 | 4380 4230 4100 3960 3830 3710 3590 3480 |
| 1228 | 3370 3260 3160 3060 2960 2870 2780 2700 |
| 1229 | >; |
| 1230 | }; |
| 1231 | usb { |
| 1232 | status = "disabled"; |
| 1233 | vbus_gpio = <0xff>; /* set_vbus */ |
| 1234 | id-gpadc = <0xff>; /* usb-id */ |
| 1235 | vchg-from-exton = <1>; |
| 1236 | vbus-detect = <1>; /* vbus-irq */ |
| 1237 | get-vbus = <1>; /* get-vbus */ |
| 1238 | }; |
| 1239 | }; |
| 1240 | pmic6: pm803@30 { |
| 1241 | compatible = "asr,pm803"; |
| 1242 | reg = <0x30>; |
| 1243 | interrupts = <4>; |
| 1244 | interrupt-parent = <&intc>; |
| 1245 | interrupt-controller; |
| 1246 | #interrupt-cells = <1>; |
| 1247 | chg_irq_from_exton; |
| 1248 | scs-int-active-high; |
| 1249 | battery { |
| 1250 | compatible = "asr,pm803-bat"; |
| 1251 | status = "disabled"; |
| 1252 | |
| 1253 | online-gpadc = <1>; |
| 1254 | temperature-gpadc = <1>; |
| 1255 | |
| 1256 | hi-volt-online = <1150>; /* mV */ |
| 1257 | lo-volt-online = <20>; /* mV */ |
| 1258 | hi-volt-temp = <1150>; /* mV */ |
| 1259 | lo-volt-temp = <200>; /* mV */ |
| 1260 | |
| 1261 | sw-fg-use-ntc; |
| 1262 | full-capacity = <2050>; /* mAh */ |
| 1263 | r1-resistor = <40>; /* mohm */ |
| 1264 | r2-resistor = <30>; /* mohm */ |
| 1265 | rs-resistor = <120>; /* mohm */ |
| 1266 | roff-resistor = <0>; /* mohm */ |
| 1267 | roff-initial-resistor = <0>; /* mohm */ |
| 1268 | |
| 1269 | times-in-zero-degree = <1>; |
| 1270 | offset-in-zero-degree = <0>; |
| 1271 | |
| 1272 | times-in-ten-degree = <2>; |
| 1273 | offset-in-ten-degree = <100>; |
| 1274 | |
| 1275 | power-off-threshold = <3350>; /* mV */ |
| 1276 | safe-power-off-threshold = <3200>; /* mV */ |
| 1277 | |
| 1278 | online-gp-bias-curr = <11>; /* uA */ |
| 1279 | |
| 1280 | soc-ramp-up-interval = <150>; /* s */ |
| 1281 | /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */ |
| 1282 | tbat-threshold = <20 0 10 40 45 55>; /* ohm */ |
| 1283 | ntc-table-size = <88>; |
| 1284 | stop-chg-for-vbatmeas; |
| 1285 | /* -24C, -23C, ..., 62C, 63C */ |
| 1286 | ntc-table = < |
| 1287 | 89680 85130 80840 76790 72970 69360 65960 62740 |
| 1288 | 59700 56830 54130 51530 49100 46800 44610 42550 |
| 1289 | 40590 38730 36970 35300 33710 32210 30780 29420 |
| 1290 | 28130 26910 25750 24640 23590 22580 21630 20720 |
| 1291 | 19860 19030 18250 17500 16790 16110 15460 14840 |
| 1292 | 14250 13690 13150 12640 12150 11680 11230 10800 |
| 1293 | 10390 10000 9620 9270 8920 8590 8280 7980 |
| 1294 | 7690 7410 7150 6890 6650 6410 6190 5970 |
| 1295 | 5770 5570 5380 5190 5020 4850 4680 4530 |
| 1296 | 4380 4230 4100 3960 3830 3710 3590 3480 |
| 1297 | 3370 3260 3160 3060 2960 2870 2780 2700 |
| 1298 | >; |
| 1299 | }; |
| 1300 | usb { |
| 1301 | status = "disabled"; |
| 1302 | vbus_gpio = <0xff>; /* set_vbus */ |
| 1303 | id-gpadc = <0xff>; /* usb-id */ |
| 1304 | vchg-from-exton = <1>; |
| 1305 | vbus-detect = <1>; /* vbus-irq */ |
| 1306 | get-vbus = <1>; /* get-vbus */ |
| 1307 | }; |
| 1308 | }; |
| 1309 | }; |
| 1310 | }; |
| 1311 | }; |
| 1312 | |
| 1313 | vcc_sdh1: sd-regulator { |
| 1314 | compatible = "regulator-fixed"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1315 | /*pinctrl-names = "default";*/ |
| 1316 | /*pinctrl-0 = <&sd_ldo_en>;*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1317 | regulator-name = "SDH1 VCC"; |
| 1318 | regulator-min-microvolt = <3300000>; |
| 1319 | regulator-max-microvolt = <3300000>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1320 | /* gpio = <&gpio 45 0>;*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1321 | enable-active-high; |
| 1322 | status = "okay"; |
| 1323 | }; |
| 1324 | |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1325 | sensors_vddio: imu-regulator { |
| 1326 | compatible = "regulator-fixed"; |
| 1327 | /*pinctrl-names = "default";*/ |
| 1328 | /*pinctrl-0 = <&sd_ldo_en>;*/ |
| 1329 | regulator-name = "IMU VDDIO"; |
| 1330 | gpio = <&gpio 21 0>; |
| 1331 | enable-active-high; |
| 1332 | status = "okay"; |
| 1333 | }; |
| 1334 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1335 | asr-rfkill { |
| 1336 | compatible = "asr,asr-rfkill"; |
| 1337 | pinctrl-names = "off", "on"; |
| 1338 | pinctrl-0 = <&sdh1_pmx_pd_rst_off>; |
| 1339 | pinctrl-1 = <&sdh1_pmx_pd_rst_on>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1340 | sd-host = <&sdh0>; |
| 1341 | //pd-gpio = <&gpio 90 0>; |
| 1342 | rst-gpio = <&gpio 90 0>; |
| 1343 | |
| 1344 | /*3v3-ldo-gpio = <&gpio 8 0>;*/ |
| 1345 | /*edge-wakeup-gpio = <&gpio 10 0>;*/ |
| 1346 | status = "okay"; |
| 1347 | }; |
| 1348 | |
| 1349 | mbtk-sdh{ |
| 1350 | compatible = "mbtk,mbtk-sdh"; |
| 1351 | pinctrl-names = "off", "on"; |
| 1352 | pinctrl-0 = <&mbtk_sdh_pmx_off>; |
| 1353 | pinctrl-1 = <&mbtk_sdh_pmx_on>; |
| 1354 | sd-host = <&sdh1>; |
| 1355 | 1v8-ldo-gpio = <&gpio 123 0>; |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1356 | //host-wakeup-wlan-gpio = <&gpio 127 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1357 | wlan_en_gpio = <&gpio 125 0>; |
| 1358 | status = "okay"; |
| 1359 | }; |
| 1360 | |
| 1361 | asr-gps { |
| 1362 | compatible = "asr,asr-gnss"; |
| 1363 | pinctrl-names = "default"; |
| 1364 | pinctrl-0 = <&gnss_clk_on>; |
| 1365 | enable_vctcxo_out1; |
| 1366 | host-wakeup-gnss-gpio = <&gpio 47 0>; |
| 1367 | /*gnss-wakeup-host-gpio = <&gpio 47 0>;*/ |
| 1368 | rst-gpio = <&gpio 45 0>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1369 | status = "okay"; |
| 1370 | }; |
| 1371 | |
| 1372 | pcie-rfkill { |
| 1373 | compatible = "mrvl,pcie-rfkill"; |
| 1374 | pinctrl-names = "off", "on"; |
| 1375 | pinctrl-0 = <&pcie_pmx_pd_rst_off>; |
| 1376 | pinctrl-1 = <&pcie_pmx_pd_rst_on>; |
| 1377 | rst-gpio = <&gpio 42 0>; |
| 1378 | 3v3-ldo-gpio = <&gpio 24 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1379 | status = "disabled"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1380 | }; |
| 1381 | |
| 1382 | sound { |
| 1383 | compatible = "ASRMICRO,asrmicro-snd-card"; |
| 1384 | ssp-controllers = <&ssp_dai1>; |
| 1385 | }; |
| 1386 | |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1387 | asr-adc { |
| 1388 | compatible = "asr,adc"; |
| 1389 | //pinctrl-names = "default"; |
| 1390 | //pinctrl-0 = <&pin_func_work>; |
| 1391 | status = "okay"; |
| 1392 | }; |
| 1393 | |
| 1394 | #if 0 |
| 1395 | |
| 1396 | mbtk_PlatIrq{ |
| 1397 | compatible = "mbtk,plat-irq"; |
| 1398 | pinctrl-names = "sc_irq0", "sc_irq1", "sc_irq2", "sc_irq3"; |
| 1399 | |
| 1400 | pinctrl-0 = <&sc_ext_int0>; |
| 1401 | pinctrl-1 = <&sc_ext_int1>; |
| 1402 | pinctrl-2 = <&sc_ext_int2>; |
| 1403 | pinctrl-3 = <&sc_ext_int3>; |
yu.dong | ca721ca | 2025-06-04 07:21:21 -0700 | [diff] [blame] | 1404 | status = "disabled"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1405 | }; |
| 1406 | |
| 1407 | #else |
| 1408 | |
| 1409 | mbtk_PlatIrq{ |
| 1410 | compatible = "mbtk,plat-irq"; |
| 1411 | pinctrl-names = "default", "sleep"; |
| 1412 | pinctrl-0 = <&mbtk_plat_irq_func>; |
| 1413 | pinctrl-1 = <&mbtk_plat_irq_func_sleep>; |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1414 | //gpio_irq0 = <&gpio 21 0>; |
| 1415 | //gpio_irq1 = <&gpio 22 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1416 | gpio_irq2 = <&gpio 23 0>; |
| 1417 | gpio_irq3 = <&gpio 24 0>; |
yu.dong | ca721ca | 2025-06-04 07:21:21 -0700 | [diff] [blame] | 1418 | status = "disabled"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1419 | }; |
| 1420 | |
| 1421 | #endif |
| 1422 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1423 | ecall { |
| 1424 | compatible = "asr,ecall-event"; |
| 1425 | pinctrl-names = "default"; |
| 1426 | pinctrl-0 = <&ecall_pmx_func>; |
| 1427 | gpio-auto-ecall = <8>; |
| 1428 | gpio-manual-ecall = <9>; |
| 1429 | status = "disabled"; |
| 1430 | }; |
| 1431 | |
| 1432 | usim1: usim1 { |
| 1433 | compatible = "asr,usim1"; |
| 1434 | pinctrl-names = "default", "sleep"; |
| 1435 | pinctrl-0 = <&usim1_pmx_func>; |
| 1436 | pinctrl-1 = <&usim1_pmx_func_sleep>; |
yq.wang | 107f986 | 2025-05-12 15:44:50 +0800 | [diff] [blame] | 1437 | edge_detect_gpio = <119>; /* GPIO19: SIM detect pin */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1438 | status = "okay"; |
| 1439 | }; |
| 1440 | /* set okay for this node if usim2 is needed */ |
| 1441 | usim2: usim2 { |
| 1442 | compatible = "asr,usim2"; |
| 1443 | pinctrl-names = "default", "sleep"; |
| 1444 | pinctrl-0 = <&usim2_pmx_func>; |
| 1445 | pinctrl-1 = <&usim2_pmx_func_sleep>; |
| 1446 | edge_detect_gpio = <44>; /* GPIO44: SIM detect pin */ |
| 1447 | #ifdef CONFIG_ASR_DSDS |
| 1448 | status = "okay"; |
| 1449 | #else |
| 1450 | status = "disabled"; |
| 1451 | #endif |
| 1452 | }; |
| 1453 | gpio_keys { |
| 1454 | compatible = "gpio-keys"; |
| 1455 | #address-cells = <1>; |
| 1456 | #size-cells = <0>; |
| 1457 | /* autorepeat; */ |
| 1458 | pinctrl-names = "default"; |
| 1459 | pinctrl-0 = <&gpiokey_pmx_func>; |
| 1460 | button@1 { |
| 1461 | label = "qrcode-key"; |
| 1462 | linux,code = <139>; /* KEY_MENU, refer to linux/input.h */ |
| 1463 | /* NOTE: |
| 1464 | * We use the FORCE DOWNLOAD key to implement the qrcode key in DKB. |
| 1465 | * Customer SHOULD change it to any other gpios. |
| 1466 | * Because user may do the misoperation that |
| 1467 | * powerup with FDL key pressed, |
| 1468 | * then the borad will enter force download mode. |
| 1469 | */ |
| 1470 | gpios = <&gpio 9 1>; |
| 1471 | gpio-key,wakeup; |
| 1472 | }; |
| 1473 | }; |
| 1474 | |
| 1475 | audio_pa { |
| 1476 | compatible = "asrmicro,audio-pa"; |
| 1477 | pinctrl-names = "default"; |
| 1478 | pinctrl-0 = <&audio_pa_pmx_func>; |
| 1479 | pa-gpio = <&gpio 14 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1480 | status = "disabled"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1481 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1482 | mbtk_GpioWakeUp { |
| 1483 | compatible = "mbtk,GpioWakeUp"; |
| 1484 | pinctrl-names = "default", "sleep"; |
| 1485 | pinctrl-0 = <&wake_pmx_func &wake_pmx_func1>; |
| 1486 | pinctrl-1 = <&wake_pmx_func_sleep>; |
| 1487 | wakeup-in-gpio = <&gpio 118 0>; |
| 1488 | wakeup-out-gpio = <&gpio 117 0>; |
| 1489 | status = "okay"; |
| 1490 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1491 | |
hong.liu | f241688 | 2025-05-23 20:41:06 -0700 | [diff] [blame] | 1492 | |
| 1493 | dtsleds{ |
| 1494 | compatible = "gpio-leds"; |
| 1495 | pinctrl-names = "default"; |
| 1496 | pinctrl-0 = <&led_pmx_func1>; |
| 1497 | status = "okay"; |
| 1498 | led0{ |
| 1499 | label = "red"; |
| 1500 | gpios = <&gpio 8 0>; |
| 1501 | linux,default-trigger = "pattern"; |
| 1502 | led-pattern = "100:100:100"; |
| 1503 | default-state = "on"; |
| 1504 | |
| 1505 | }; |
| 1506 | |
| 1507 | // led1{ |
| 1508 | // label = "blue"; |
| 1509 | // gpios = <&gpio 99 0>; |
| 1510 | // linux,default-trigger = "timer"; |
| 1511 | // timer-delay-on = <100>; |
| 1512 | // timer-delay-off = <100>; |
| 1513 | // brightness-levels = <100>; |
| 1514 | // brightness-max = <100>; |
| 1515 | // default-state = "on"; |
| 1516 | // }; |
| 1517 | |
| 1518 | }; |
| 1519 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1520 | audio_regs { |
| 1521 | compatible = "ASRMICRO,audio-registers"; |
| 1522 | reg = <0xD4050044 0x4>; |
| 1523 | status = "okay"; |
| 1524 | }; |
| 1525 | |
| 1526 | nz3-slic { |
| 1527 | compatible = "asr,nz3-slic"; |
| 1528 | pinctrl-names = "default", "sleep"; |
| 1529 | pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>; |
| 1530 | pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>; |
| 1531 | rst-gpio = <&gpio 21 0>; |
| 1532 | edge-wakeup-gpio = <&gpio 20 0>; |
| 1533 | vdd-3v3-gpio = <&gpio 127 0>; |
| 1534 | status = "disabled"; |
| 1535 | }; |
| 1536 | microsemi-slic { |
| 1537 | compatible = "asr,microsemi-slic"; |
| 1538 | pinctrl-names = "default", "sleep"; |
| 1539 | pinctrl-0 = <&slic_pmx_func1>; |
| 1540 | pinctrl-1 = <&slic_pmx_func1_sleep>; |
| 1541 | edge-wakeup-gpio = <&gpio 20 0>; |
| 1542 | vdd-3v3-gpio = <&gpio 127 0>; |
| 1543 | status = "disabled"; |
| 1544 | }; |
| 1545 | maxlinear-slic { |
| 1546 | compatible = "asr,maxlinear-slic"; |
| 1547 | pinctrl-names = "default", "sleep"; |
| 1548 | pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>; |
| 1549 | pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>; |
| 1550 | rst-gpio = <&gpio 21 0>; |
| 1551 | edge-wakeup-gpio = <&gpio 20 0>; |
| 1552 | vdd-3v3-gpio = <&gpio 127 0>; |
| 1553 | status = "disabled"; |
| 1554 | }; |
| 1555 | /* deprecated, move to mfpr@d401e000 |
| 1556 | lpm-board-cfg { |
| 1557 | compatible = "asr,lpm-board-cfg"; |
| 1558 | wakeup-state-d1pp = <0x1>; |
| 1559 | udr-mfpr-config = <0x1B0 0xA040 0x0 |
| 1560 | 0x1B4 0xA040 0x0>; |
| 1561 | }; |
| 1562 | */ |
| 1563 | }; |
| 1564 | #ifdef CONFIG_ASR_DSDS |
| 1565 | #include "asr_pm802_2usim.dtsi" |
| 1566 | #include "88pm805.dtsi" |
| 1567 | #include "asr_pm803_2usim.dtsi" |
| 1568 | #else |
| 1569 | #include "asr_pm802.dtsi" |
| 1570 | #include "88pm805.dtsi" |
| 1571 | #include "asr_pm803.dtsi" |
| 1572 | #endif |
| 1573 | |
| 1574 | #ifdef CONFIG_AB_SYSTEM |
| 1575 | #include "asr1806_ab_flash_layout.dtsi" |
| 1576 | #else |
| 1577 | #include "asr1806_flash_layout.dtsi" |
| 1578 | #endif |