| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | From 233d5936fb01dc7b47641e10354f7cc34124c592 Mon Sep 17 00:00:00 2001 |
| 2 | From: Laurentiu Tudor <laurentiu.tudor@nxp.com> |
| 3 | Date: Tue, 6 Feb 2018 14:27:41 +0200 |
| 4 | Subject: [PATCH] arm64: dts: ls1046a: add smmu node |
| 5 | |
| 6 | This allows for the SMMU device to be probed by the SMMU kernel driver. |
| 7 | |
| 8 | Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> |
| 9 | --- |
| 10 | arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 42 ++++++++++++++++++++++++++ |
| 11 | 1 file changed, 42 insertions(+) |
| 12 | |
| 13 | --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |
| 14 | +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |
| 15 | @@ -229,6 +229,48 @@ |
| 16 | bus-width = <4>; |
| 17 | }; |
| 18 | |
| 19 | + smmu: iommu@9000000 { |
| 20 | + compatible = "arm,mmu-500"; |
| 21 | + reg = <0 0x9000000 0 0x400000>; |
| 22 | + dma-coherent; |
| 23 | + #global-interrupts = <2>; |
| 24 | + #iommu-cells = <1>; |
| 25 | + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 26 | + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, |
| 27 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 28 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 29 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 30 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 31 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 32 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 33 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 34 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 35 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 36 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 37 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 38 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 39 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 40 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 41 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 42 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 43 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 44 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 45 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 46 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 47 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 48 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 49 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 50 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 51 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 52 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 53 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 54 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 55 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 56 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 57 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 58 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| 59 | + }; |
| 60 | + |
| 61 | scfg: scfg@1570000 { |
| 62 | compatible = "fsl,ls1046a-scfg", "syscon"; |
| 63 | reg = <0x0 0x1570000 0x0 0x10000>; |