| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | From b3841e7de0be51ddb4e0d17ab0561a12c6db2753 Mon Sep 17 00:00:00 2001 |
| 2 | From: Alex Marginean <alexandru.marginean@nxp.com> |
| 3 | Date: Wed, 8 Jan 2020 12:34:33 +0200 |
| 4 | Subject: [PATCH] drivers: net: dsa: felix: Allow PHY to AN 10/100/1000 with |
| 5 | 2500 serdes link |
| 6 | |
| 7 | If the serdes link is set to 2500 using interfce type 2500base-X, lower |
| 8 | link speeds over on the line side should still be supported. |
| 9 | Rate adaptation is done out of band, in our case using AQR PHYs this is |
| 10 | done using flow control. |
| 11 | |
| 12 | Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> |
| 13 | --- |
| 14 | drivers/net/dsa/ocelot/felix.c | 9 ++++----- |
| 15 | 1 file changed, 4 insertions(+), 5 deletions(-) |
| 16 | |
| 17 | --- a/drivers/net/dsa/ocelot/felix.c |
| 18 | +++ b/drivers/net/dsa/ocelot/felix.c |
| 19 | @@ -218,11 +218,10 @@ static void felix_phylink_validate(struc |
| 20 | phylink_set(mask, Autoneg); |
| 21 | phylink_set(mask, Pause); |
| 22 | phylink_set(mask, Asym_Pause); |
| 23 | - if (state->interface != PHY_INTERFACE_MODE_2500BASEX) { |
| 24 | - phylink_set(mask, 10baseT_Full); |
| 25 | - phylink_set(mask, 100baseT_Full); |
| 26 | - phylink_set(mask, 1000baseT_Full); |
| 27 | - } |
| 28 | + phylink_set(mask, 10baseT_Full); |
| 29 | + phylink_set(mask, 100baseT_Full); |
| 30 | + phylink_set(mask, 1000baseT_Full); |
| 31 | + |
| 32 | /* The internal ports that run at 2.5G are overclocked GMII */ |
| 33 | if (state->interface == PHY_INTERFACE_MODE_GMII || |
| 34 | state->interface == PHY_INTERFACE_MODE_2500BASEX || |