| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | From 494c1f9c5c86396d2974c6072f728e2325b72703 Mon Sep 17 00:00:00 2001 |
| 2 | From: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com> |
| 3 | Date: Wed, 7 Mar 2018 11:35:07 +0200 |
| 4 | Subject: [PATCH] Sound: Soc: fsl: Set SAI Channel Mode to Output Mode |
| 5 | |
| 6 | Transmit data pins will output zero when slots are masked or channels |
| 7 | are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when |
| 8 | slots are masked or channels are disabled. When data pins are tri-stated, |
| 9 | there is noise on some channels when FS clock value is high and data is |
| 10 | read while fsclk is transitioning from high to low. |
| 11 | |
| 12 | Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com> |
| 13 | Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> |
| 14 | --- |
| 15 | sound/soc/fsl/fsl_sai.c | 14 +++++++++++--- |
| 16 | sound/soc/fsl/fsl_sai.h | 2 ++ |
| 17 | 2 files changed, 13 insertions(+), 3 deletions(-) |
| 18 | |
| 19 | --- a/sound/soc/fsl/fsl_sai.c |
| 20 | +++ b/sound/soc/fsl/fsl_sai.c |
| 21 | @@ -589,6 +589,11 @@ static int fsl_sai_hw_params(struct snd_ |
| 22 | |
| 23 | val_cr4 |= FSL_SAI_CR4_FRSZ(slots); |
| 24 | |
| 25 | + /* Output Mode - data pins transmit 0 when slots are masked |
| 26 | + * or channels are disabled |
| 27 | + */ |
| 28 | + val_cr4 |= FSL_SAI_CR4_CHMOD; |
| 29 | + |
| 30 | /* |
| 31 | * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will |
| 32 | * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), |
| 33 | @@ -599,14 +604,16 @@ static int fsl_sai_hw_params(struct snd_ |
| 34 | if (!sai->slave_mode[tx]) { |
| 35 | if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { |
| 36 | regmap_update_bits(sai->regmap, FSL_SAI_TCR4(offset), |
| 37 | - FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, |
| 38 | + FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | |
| 39 | + FSL_SAI_CR4_CHMOD_MASK, |
| 40 | val_cr4); |
| 41 | regmap_update_bits(sai->regmap, FSL_SAI_TCR5(offset), |
| 42 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | |
| 43 | FSL_SAI_CR5_FBT_MASK, val_cr5); |
| 44 | } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { |
| 45 | regmap_update_bits(sai->regmap, FSL_SAI_RCR4(offset), |
| 46 | - FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, |
| 47 | + FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | |
| 48 | + FSL_SAI_CR4_CHMOD_MASK, |
| 49 | val_cr4); |
| 50 | regmap_update_bits(sai->regmap, FSL_SAI_RCR5(offset), |
| 51 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | |
| 52 | @@ -682,7 +689,8 @@ static int fsl_sai_hw_params(struct snd_ |
| 53 | } |
| 54 | |
| 55 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset), |
| 56 | - FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, |
| 57 | + FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | |
| 58 | + FSL_SAI_CR4_CHMOD_MASK, |
| 59 | val_cr4); |
| 60 | regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, offset), |
| 61 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | |
| 62 | --- a/sound/soc/fsl/fsl_sai.h |
| 63 | +++ b/sound/soc/fsl/fsl_sai.h |
| 64 | @@ -129,6 +129,8 @@ |
| 65 | #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16) |
| 66 | #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) |
| 67 | #define FSL_SAI_CR4_SYWD_MASK (0x1f << 8) |
| 68 | +#define FSL_SAI_CR4_CHMOD (1 << 5) |
| 69 | +#define FSL_SAI_CR4_CHMOD_MASK (1 << 5) |
| 70 | #define FSL_SAI_CR4_MF BIT(4) |
| 71 | #define FSL_SAI_CR4_FSE BIT(3) |
| 72 | #define FSL_SAI_CR4_FSP BIT(1) |