| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | From c89d85a39df353290ea7af84a32d5ca692a3c27a Mon Sep 17 00:00:00 2001 |
| 2 | From: Fugang Duan <fugang.duan@nxp.com> |
| 3 | Date: Sat, 2 Nov 2019 15:51:40 +0800 |
| 4 | Subject: [PATCH] PCI: dwc: Use interrupt disabling instead of masking |
| 5 | |
| 6 | commit 830920e065e9("PCI: dwc: Use interrupt masking instead |
| 7 | of disabling") break i.MX platform PCIe suspend/resume when |
| 8 | MSI enabled. |
| 9 | |
| 10 | Revert the commit to keep orinigal method that using interrupt |
| 11 | disabling instead of masking. |
| 12 | |
| 13 | Signed-off-by: Fugang Duan <fugang.duan@nxp.com> |
| 14 | --- |
| 15 | drivers/pci/controller/dwc/pcie-designware-host.c | 19 +++++++------------ |
| 16 | 1 file changed, 7 insertions(+), 12 deletions(-) |
| 17 | |
| 18 | --- a/drivers/pci/controller/dwc/pcie-designware-host.c |
| 19 | +++ b/drivers/pci/controller/dwc/pcie-designware-host.c |
| 20 | @@ -157,8 +157,8 @@ static void dw_pci_bottom_mask(struct ir |
| 21 | bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; |
| 22 | |
| 23 | pp->irq_mask[ctrl] |= BIT(bit); |
| 24 | - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, |
| 25 | - pp->irq_mask[ctrl]); |
| 26 | + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, |
| 27 | + ~pp->irq_mask[ctrl]); |
| 28 | |
| 29 | raw_spin_unlock_irqrestore(&pp->lock, flags); |
| 30 | } |
| 31 | @@ -176,8 +176,8 @@ static void dw_pci_bottom_unmask(struct |
| 32 | bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; |
| 33 | |
| 34 | pp->irq_mask[ctrl] &= ~BIT(bit); |
| 35 | - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, |
| 36 | - pp->irq_mask[ctrl]); |
| 37 | + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, |
| 38 | + ~pp->irq_mask[ctrl]); |
| 39 | |
| 40 | raw_spin_unlock_irqrestore(&pp->lock, flags); |
| 41 | } |
| 42 | @@ -659,15 +659,10 @@ void dw_pcie_setup_rc(struct pcie_port * |
| 43 | num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; |
| 44 | |
| 45 | /* Initialize IRQ Status array */ |
| 46 | - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { |
| 47 | - pp->irq_mask[ctrl] = ~0; |
| 48 | - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + |
| 49 | + for (ctrl = 0; ctrl < num_ctrls; ctrl++) |
| 50 | + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + |
| 51 | (ctrl * MSI_REG_CTRL_BLOCK_SIZE), |
| 52 | - 4, pp->irq_mask[ctrl]); |
| 53 | - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + |
| 54 | - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), |
| 55 | - 4, ~0); |
| 56 | - } |
| 57 | + 4, &pp->irq_mask[ctrl]); |
| 58 | } |
| 59 | |
| 60 | /* Setup RC BARs */ |