b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | From c5324b25fe98c7a4784248b53a75720b226436c2 Mon Sep 17 00:00:00 2001 |
| 2 | From: Li Jun <jun.li@nxp.com> |
| 3 | Date: Tue, 29 Oct 2019 17:40:25 +0800 |
| 4 | Subject: [PATCH] MLK-22675 usb: dwc3: host: disable park mode |
| 5 | |
| 6 | - Advantage of park mode |
| 7 | When only a single Async endpoint is active. |
| 8 | |
| 9 | - Behavior of park mode |
| 10 | 1. The controller prefetches data/TRBs to do 3 * burst_size worth |
| 11 | of packets. |
| 12 | 2. When park mode is disabled there will be some delay between |
| 13 | bursts on the USB. This can be avoided if park mode is enabled |
| 14 | in cases of only one endpoint is active. |
| 15 | 3. But this delay is significant only with systems of large |
| 16 | latencies. |
| 17 | 4. We have noticed that in cases where a device NAKs often, it |
| 18 | tends to bring down the performance for a single endpoint case. |
| 19 | |
| 20 | - Issue on "park mode" |
| 21 | 1. LSP (List Processor) goes in and out of park mode irrespective |
| 22 | of the fact that there are more endpoints active. #LSP consider |
| 23 | that there is only one endpoint active. |
| 24 | 2. This causes master scheduler and transaction handlers to think |
| 25 | that they are in park mode even though they are not. This is |
| 26 | because request to transaction handlers, generated by HSCH is |
| 27 | in park mode when the request is made |
| 28 | 3. This causes a case where the master scheduler calculates wrongly |
| 29 | the number of TRB cache space available. |
| 30 | 4. Because of the wrongly calculated number of TRB spaces, the core |
| 31 | fetches more TRBS than there is space for. |
| 32 | 5. This causes overwriting the TRB cache area into the TRQ cache |
| 33 | area which is next to the TRB cache area. |
| 34 | 6. This causes invalidating an entry in the TRQ |
| 35 | 7. This causes transaction handlers to ignore a request in the TRQ |
| 36 | which it should have processed. |
| 37 | 8. This causes the main scheduler to hang because it is waiting for |
| 38 | status from transaction handler. |
| 39 | 9. This causes host controller to hang. |
| 40 | |
| 41 | - Work Around |
| 42 | Disabling park mode for super speed by setting GUCTL1[17] to be 1. |
| 43 | |
| 44 | The STAR number is 9001415732, which is target to be released around |
| 45 | May,2020. |
| 46 | |
| 47 | Reviewed-by: Peter Chen <peter.chen@nxp.com> |
| 48 | Reviewed-by: Ran Wang <ran.wang_1@nxp.com> |
| 49 | Signed-off-by: Li Jun <jun.li@nxp.com> |
| 50 | --- |
| 51 | drivers/usb/dwc3/core.c | 15 +++++++++++++++ |
| 52 | drivers/usb/dwc3/core.h | 1 + |
| 53 | 2 files changed, 16 insertions(+) |
| 54 | |
| 55 | --- a/drivers/usb/dwc3/core.c |
| 56 | +++ b/drivers/usb/dwc3/core.c |
| 57 | @@ -1045,6 +1045,21 @@ static int dwc3_core_init(struct dwc3 *d |
| 58 | reg |= DWC3_GUCTL_HSTINAUTORETRY; |
| 59 | |
| 60 | dwc3_writel(dwc->regs, DWC3_GUCTL, reg); |
| 61 | + |
| 62 | + /* |
| 63 | + * Disable Park Mode for super speed: |
| 64 | + * Park mode is used in host mode when only a single async |
| 65 | + * endpoint is active, but which has a known issue cause |
| 66 | + * USB3.0 HC may die when read and write at the same time, |
| 67 | + * considering the advantages of this mode are minimal, |
| 68 | + * this issue only impacts super speed and exist on all IP |
| 69 | + * versions, disable it for SS, Synopsys will release a formal |
| 70 | + * STAR 9001415732, and disable it by default in next IP |
| 71 | + * release. |
| 72 | + */ |
| 73 | + reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); |
| 74 | + reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; |
| 75 | + dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); |
| 76 | } |
| 77 | |
| 78 | /* |
| 79 | --- a/drivers/usb/dwc3/core.h |
| 80 | +++ b/drivers/usb/dwc3/core.h |
| 81 | @@ -255,6 +255,7 @@ |
| 82 | #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) |
| 83 | #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) |
| 84 | #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) |
| 85 | +#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) |
| 86 | |
| 87 | /* Global Status Register */ |
| 88 | #define DWC3_GSTS_OTG_IP BIT(10) |