[Bugfix][THW-46][pcie] add mtk patch Adjust-PCIe-Reset-Sequence
Change-Id: I825572f9363f34cc93e020dff0120b19becdc051
diff --git a/src/kernel/linux/v4.19/drivers/pci/controller/pcie-mediatek-gen3.c b/src/kernel/linux/v4.19/drivers/pci/controller/pcie-mediatek-gen3.c
index 91208ec..eee7464 100644
--- a/src/kernel/linux/v4.19/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/src/kernel/linux/v4.19/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -466,16 +466,20 @@
val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
writel(val, port->base + PCIE_RST_CTRL_REG);
+ //you.chen@202221011 add mtk patch for pcie reset sequence begin
+ msleep(100);
+
/* De-assert reset signals*/
- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
writel(val, port->base + PCIE_RST_CTRL_REG);
/* Delay 100ms to wait the reference clocks become stable */
- usleep_range(100 * 1000, 120 * 1000);
+ //usleep_range(100 * 1000, 120 * 1000);
/* De-assert pe reset*/
- val &= ~PCIE_PE_RSTB;
- writel(val, port->base + PCIE_RST_CTRL_REG);
+ //val &= ~PCIE_PE_RSTB;
+ //writel(val, port->base + PCIE_RST_CTRL_REG);
+ //you.chen@202221011 add mtk patch for pcie reset sequence end
/* Check if the link is up or not */
err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_REG, val,