[Bugfix][API-1384] add debug patch for command ping fail (tx_busy)
Affected branch: GSW3.0-No-Connman
Affected module: DATA
Is it affected on both ZXIC and MTK: only MTK
Self-test: Yes
Doc Update: No
Change-Id: I9b64a94a6fbfe411e1eaed26a584ffbdee7da329
diff --git a/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_md_hw_remap.c b/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_md_hw_remap.c
index 13a1f5a..14f6b7a 100644
--- a/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_md_hw_remap.c
+++ b/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_md_hw_remap.c
@@ -49,35 +49,32 @@
uint64_t md_remap_addr = ((lo32_addr&0xFFFFFFFF) | (hi32_addr << 32));
unsigned int write_val;
- INFO("BANK0_MAP_ADDR(0x%llX, 0x%llX, 0x%llX)",
+ INFO("BANK0_MAP_ADDR(0x%llx, 0x%llx, 0x%llx)\n",
md_remap_addr, lo32_addr, hi32_addr);
/* For MDx_BANK0_MAP0: 10 bits each */
write_val = (((md_remap_addr >> 25) & 0x3FF)
+ (((md_remap_addr + 0x2000000*1) >> 15) & 0xFFC00)
+ (((md_remap_addr + 0x2000000*2) >> 5) & 0x3FF00000));
mmio_write_32(MD1_BANK0_MDMCU_INFRA_MAP0, write_val);
- mmio_write_32(CCIF1_SRAM_D0, write_val);
/* For MDx_BANK0_MAP1 */
write_val = ((((md_remap_addr + 0x2000000*3) >> 25) & 0x3FF)
+ (((md_remap_addr + 0x2000000*4) >> 15) & 0xFFC00)
+ (((md_remap_addr + 0x2000000*5) >> 5) & 0x3FF00000));
mmio_write_32(MD1_BANK0_MDMCU_INFRA_MAP1, write_val);
- mmio_write_32(CCIF1_SRAM_D4, write_val);
/* For MDx_BANK0_MAP2 */
write_val = mmio_read_32(MD1_BANK0_MDMCU_INFRA_MAP2); /*29:20 for b1*/
write_val = ((((md_remap_addr + 0x2000000*6) >> 25) & 0x3FF)
+ (((md_remap_addr + 0x2000000*7) >> 15) & 0xFFC00)
+ (write_val & 0x3FF00000));
mmio_write_32(MD1_BANK0_MDMCU_INFRA_MAP2, write_val);
- mmio_write_32(CCIF1_SRAM_D8, write_val);
*ret1 = mmio_read_32(MD1_BANK0_MDMCU_INFRA_MAP0);
*ret2 = mmio_read_32(MD1_BANK0_MDMCU_INFRA_MAP1);
*ret3 = mmio_read_32(MD1_BANK0_MDMCU_INFRA_MAP2);
- INFO("BANK0_MAP0 value:0x%llX\n", *ret1);
- INFO("BANK0_MAP1 value:0x%llX\n", *ret2);
- INFO("BANK0_MAP2 value:0x%llX\n", *ret3);
+ INFO("BANK0_MAP0 value:0x%llx\n", *ret1);
+ INFO("BANK0_MAP1 value:0x%llx\n", *ret2);
+ INFO("BANK0_MAP2 value:0x%llx\n", *ret3);
return 0;
}
@@ -89,7 +86,7 @@
uint64_t ret0;
unsigned int write_val;
- INFO("BANK1_MAP_ADDR(0x%llX, 0x%llX, 0x%llX)",
+ INFO("BANK1_MAP_ADDR(0x%llx, 0x%llx, 0x%llx)\n",
md_remap_addr, lo32_addr, hi32_addr);
// MD needs extra 3*32MB in dummy ap mode for storage
@@ -98,14 +95,12 @@
write_val = ((((md_remap_addr + 0x2000000*8) >> 5) & 0x3FF00000)
+ (write_val & 0xFFFFF));
mmio_write_32(MD1_BANK1_MDMCU_INFRA_MAP0, write_val);
- mmio_write_32(CCIF1_SRAM_D8, write_val);
write_val = mmio_read_32(MD1_BANK1_MDMCU_INFRA_MAP1); /*29:19, 19:0 for b0*/
write_val = ((((md_remap_addr + 0x2000000*9) >> 25) & 0x3FF)
+ (((md_remap_addr + 0x2000000*10) >> 15) & 0xFFC00)
+ (write_val & 0xFFFFF));
mmio_write_32(MD1_BANK1_MDMCU_INFRA_MAP1, write_val);
- mmio_write_32(CCIF1_SRAM_DC, write_val);
}
// for MD DSP special request,
// MD DSP only can access higher memory, so ask to add hw remap to BANK0
@@ -114,20 +109,18 @@
+ (((md_remap_addr + 0x2000000*6) >> 15) & 0xFFC00)
+ (((md_remap_addr + 0x2000000*7) >> 5) & 0x3FF00000));
mmio_write_32(MD1_BANK1_MDMCU_INFRA_MAP2, write_val);
- mmio_write_32(CCIF1_SRAM_E0, write_val);
mmio_write_32(MD1_BANK1_MDMCU_INFRA_MAP3, 0);
- mmio_write_32(CCIF1_SRAM_E4, 0);
ret0 = mmio_read_32(MD1_BANK1_MDMCU_INFRA_MAP0);
*ret1 = mmio_read_32(MD1_BANK1_MDMCU_INFRA_MAP1);
*ret2 = mmio_read_32(MD1_BANK1_MDMCU_INFRA_MAP2);
*ret3 = mmio_read_32(MD1_BANK1_MDMCU_INFRA_MAP3);
- INFO("BANK1_MAP0 value:0x%llX\n", ret0);
- INFO("BANK1_MAP1 value:0x%llX\n", *ret1);
- INFO("BANK1_MAP2 value:0x%llX\n", *ret2);
- INFO("BANK1_MAP3 value:0x%llX\n", *ret3);
+ INFO("BANK1_MAP0 value:0x%llx\n", ret0);
+ INFO("BANK1_MAP1 value:0x%llx\n", *ret1);
+ INFO("BANK1_MAP2 value:0x%llx\n", *ret2);
+ INFO("BANK1_MAP3 value:0x%llx\n", *ret3);
return ret0;
}
@@ -136,12 +129,12 @@
uint64_t slot, uint64_t *ret1)
{
int64_t md_remap_addr = ((lo32_addr&0xFFFFFFFF) | (hi32_addr << 32));
- unsigned int infra_reg_addr, ccif_sram_addr;
+ unsigned int infra_reg_addr;
// needs to shift 32MB for HW REMAP design
// reserve BANK4_MAP0 [19:10] for FP_MD_norm_dummy_120
unsigned int write_val;
- INFO("BANK4_MAP_ADDR(0x%llX, 0x%llX, 0x%llX)",
+ INFO("BANK4_MAP_ADDR(0x%llx, 0x%llx, 0x%llx)\n",
md_remap_addr, lo32_addr, hi32_addr);
switch (slot) {
@@ -150,56 +143,48 @@
write_val = mmio_read_32(MD1_BANK4_MDMCU_INFRA_MAP0);
write_val &= ~(0x3FF00000);
write_val |= ((md_remap_addr >> 5) & 0x3FF00000);
- ccif_sram_addr = CCIF1_SRAM_E4;
break;
case 1:
infra_reg_addr = MD1_BANK4_MDMCU_INFRA_MAP1;
write_val = mmio_read_32(MD1_BANK4_MDMCU_INFRA_MAP1);
write_val &= ~(0x3FF);
write_val |= ((md_remap_addr >> 25) & 0x3FF);
- ccif_sram_addr = CCIF1_SRAM_E8;
break;
case 2:
infra_reg_addr = MD1_BANK4_MDMCU_INFRA_MAP1;
write_val = mmio_read_32(MD1_BANK4_MDMCU_INFRA_MAP1);
write_val &= ~(0xFFC00);
write_val |= ((md_remap_addr >> 15) & 0xFFC00);
- ccif_sram_addr = CCIF1_SRAM_E8;
break;
case 3:
infra_reg_addr = MD1_BANK4_MDMCU_INFRA_MAP1;
write_val = mmio_read_32(MD1_BANK4_MDMCU_INFRA_MAP1);
write_val &= ~(0x3FF00000);
write_val |= ((md_remap_addr >> 5) & 0x3FF00000);
- ccif_sram_addr = CCIF1_SRAM_E8;
break;
case 4:
infra_reg_addr = MD1_BANK4_MDMCU_INFRA_MAP2;
write_val = mmio_read_32(MD1_BANK4_MDMCU_INFRA_MAP2);
write_val &= ~(0x3FF);
write_val |= ((md_remap_addr >> 25) & 0x3FF);
- ccif_sram_addr = CCIF1_SRAM_EC;
break;
case 5:
infra_reg_addr = MD1_BANK4_MDMCU_INFRA_MAP2;
write_val = mmio_read_32(MD1_BANK4_MDMCU_INFRA_MAP2);
write_val &= ~(0xFFC00);
write_val |= ((md_remap_addr >> 15) & 0xFFC00);
- ccif_sram_addr = CCIF1_SRAM_EC;
break;
case 6:
infra_reg_addr = MD1_BANK4_MDMCU_INFRA_MAP2;
write_val = mmio_read_32(MD1_BANK4_MDMCU_INFRA_MAP2);
write_val &= ~(0x3FF00000);
write_val |= ((md_remap_addr >> 5) & 0x3FF00000);
- ccif_sram_addr = CCIF1_SRAM_EC;
break;
case 7:
infra_reg_addr = MD1_BANK4_MDMCU_INFRA_MAP3;
write_val = mmio_read_32(MD1_BANK4_MDMCU_INFRA_MAP3);
write_val &= ~(0x3FF);
write_val |= ((md_remap_addr >> 25) & 0x3FF);
- ccif_sram_addr = CCIF1_SRAM_F0;
break;
default:
return 0;
@@ -207,10 +192,9 @@
/* For MDx_BANK4_MAP */
mmio_write_32(infra_reg_addr, write_val);
- mmio_write_32(ccif_sram_addr, write_val);
*ret1 = mmio_read_32(infra_reg_addr);
- INFO("BANK4_MAP(%llu) value:0x%llX\n", slot, *ret1);
+ INFO("BANK4_MAP(%llu) value:0x%llx\n", slot, *ret1);
return 0;
}
@@ -259,3 +243,34 @@
return 0;
}
+uint64_t md_hw_remap_config_sync(void)
+{
+ // sync hw remap config in pccif1 sram for dpmaif
+ mmio_write_32(CCIF1_SRAM_D0, mmio_read_32(MD1_BANK0_MDMCU_INFRA_MAP0));
+ mmio_write_32(CCIF1_SRAM_D4, mmio_read_32(MD1_BANK0_MDMCU_INFRA_MAP1));
+ mmio_write_32(CCIF1_SRAM_D8, mmio_read_32(MD1_BANK0_MDMCU_INFRA_MAP2));
+ mmio_write_32(CCIF1_SRAM_D8, mmio_read_32(MD1_BANK1_MDMCU_INFRA_MAP0));
+ INFO("CCIF1_SRAM_D0=0x%x, CCIF1_SRAM_D4=0x%x, CCIF1_SRAM_D8=0x%x\n",
+ mmio_read_32(CCIF1_SRAM_D0),
+ mmio_read_32(CCIF1_SRAM_D4),
+ mmio_read_32(CCIF1_SRAM_D8));
+
+ mmio_write_32(CCIF1_SRAM_DC, mmio_read_32(MD1_BANK1_MDMCU_INFRA_MAP1));
+ mmio_write_32(CCIF1_SRAM_E0, mmio_read_32(MD1_BANK1_MDMCU_INFRA_MAP2));
+ mmio_write_32(CCIF1_SRAM_E4, mmio_read_32(MD1_BANK1_MDMCU_INFRA_MAP3));
+ mmio_write_32(CCIF1_SRAM_E4, mmio_read_32(MD1_BANK4_MDMCU_INFRA_MAP0));
+ INFO("CCIF1_SRAM_DC=0x%x, CCIF1_SRAM_E0=0x%x, CCIF1_SRAM_E4=0x%x\n",
+ mmio_read_32(CCIF1_SRAM_DC),
+ mmio_read_32(CCIF1_SRAM_E0),
+ mmio_read_32(CCIF1_SRAM_E4));
+
+ mmio_write_32(CCIF1_SRAM_E8, mmio_read_32(MD1_BANK4_MDMCU_INFRA_MAP1));
+ mmio_write_32(CCIF1_SRAM_EC, mmio_read_32(MD1_BANK4_MDMCU_INFRA_MAP2));
+ mmio_write_32(CCIF1_SRAM_F0, mmio_read_32(MD1_BANK4_MDMCU_INFRA_MAP3));
+ INFO("CCIF1_SRAM_E8=0x%x, CCIF1_SRAM_EC=0x%x, CCIF1_SRAM_F0=0x%x\n",
+ mmio_read_32(CCIF1_SRAM_E8),
+ mmio_read_32(CCIF1_SRAM_EC),
+ mmio_read_32(CCIF1_SRAM_F0));
+
+ return 0;
+}
diff --git a/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_md_hw_remap.h b/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_md_hw_remap.h
index 9549f01..a76047f 100644
--- a/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_md_hw_remap.h
+++ b/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_md_hw_remap.h
@@ -15,6 +15,7 @@
uint64_t slot, uint64_t *ret1);
extern uint64_t md_sib_hw_remap(uint64_t lo32_addr, uint64_t hi32_addr,
uint64_t *ret1, uint64_t *ret2, uint64_t *ret3);
+extern uint64_t md_hw_remap_config_sync(void);
#endif
diff --git a/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_secure_common.c b/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_secure_common.c
index 1922eb9..6a6af3c 100644
--- a/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_secure_common.c
+++ b/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_secure_common.c
@@ -33,6 +33,10 @@
break;
case MD_FLIGHT_MODE_SET:
ret0 = md_flight_mode_set(arg1, arg2, arg3, ret1, ret2, ret3);
+ break;
+ case MD_HW_REMAP_CONFIG_SYNC:
+ ret0 = md_hw_remap_config_sync();
+ break;
default:
break;
}
diff --git a/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_secure_common.h b/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_secure_common.h
index 653dc4c..8c8b18d 100644
--- a/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_secure_common.h
+++ b/src/bsp/trustzone/atf/v1.6/mt2xxx/plat/mediatek/mt2735/drivers/ccci/ccci_secure_common.h
@@ -16,6 +16,7 @@
MD_CLOCK_REQUEST,
MD_POWER_CONFIG,
MD_FLIGHT_MODE_SET,
+ MD_HW_REMAP_CONFIG_SYNC,
};
extern uint64_t ccci_secure_request_dispatch_kernel(uint64_t arg0,
diff --git a/src/kernel/linux/v4.19/drivers/misc/mediatek/eccci/hif/ccci_hif_dpmaif.c b/src/kernel/linux/v4.19/drivers/misc/mediatek/eccci/hif/ccci_hif_dpmaif.c
index 034ee5f..a0e9fa6 100644
--- a/src/kernel/linux/v4.19/drivers/misc/mediatek/eccci/hif/ccci_hif_dpmaif.c
+++ b/src/kernel/linux/v4.19/drivers/misc/mediatek/eccci/hif/ccci_hif_dpmaif.c
@@ -356,6 +356,17 @@
}
}
+void* getDRBtableAddress(int qid)
+{
+ struct dpmaif_tx_queue *txq;
+ if (qid == 2 || qid == 3) {
+ txq = &dpmaif_ctrl->txq[qid];
+ return txq->drb_base;
+ }
+ return NULL;
+}
+EXPORT_SYMBOL_GPL(getDRBtableAddress);
+
static void dpmaif_dump_txq_remain(struct hif_dpmaif_ctrl *hif_ctrl,
unsigned int qno, int dump_multi)
{
diff --git a/src/kernel/linux/v4.19/drivers/misc/mediatek/eccci/modem_sys1.c b/src/kernel/linux/v4.19/drivers/misc/mediatek/eccci/modem_sys1.c
index 11a7c29..f534b4f 100644
--- a/src/kernel/linux/v4.19/drivers/misc/mediatek/eccci/modem_sys1.c
+++ b/src/kernel/linux/v4.19/drivers/misc/mediatek/eccci/modem_sys1.c
@@ -3,6 +3,8 @@
* Copyright (C) 2016 MediaTek Inc.
*/
+#include <linux/arm-smccc.h>
+#include <linux/soc/mediatek/mtk_sip_svc.h>
#include <linux/list.h>
#include <linux/device.h>
#include <linux/module.h>
@@ -39,6 +41,7 @@
#include "ccci_platform.h"
#include "md_sys1_platform.h"
#include "modem_reg_base.h"
+#include "modem_secure_base.h"
#include "ccci_debug.h"
#ifndef M2_SERIAL_PRODUCT
#include "hif/ccci_hif_cldma.h"
@@ -58,6 +61,15 @@
#endif
+static void sync_hw_remap_config(void)
+{
+ struct arm_smccc_res res;
+
+ CCCI_NORMAL_LOG(0, TAG, "sync hw remap config in pccif1\n");
+ arm_smccc_smc(MTK_SIP_KERNEL_CCCI_CONTROL, MD_HW_REMAP_CONFIG_SYNC,
+ 0, 0, 0, 0, 0, 0, &res);
+}
+
void ccif_enable_irq(struct ccci_modem *md)
{
struct md_sys1_info *md_info = (struct md_sys1_info *)md->private_data;
@@ -490,6 +502,10 @@
#endif
ccci_md_hif_start(md, 1);
+
+ // sync the config in pccif1 for dpmaif between ccif ready and md ungate
+ sync_hw_remap_config();
+
/* 4. power on modem, do NOT touch MD register before this */
ret = md_cd_power_on(md);
if (ret) {
diff --git a/src/kernel/linux/v4.19/drivers/misc/mediatek/eccci/mt6890/modem_secure_base.h b/src/kernel/linux/v4.19/drivers/misc/mediatek/eccci/mt6890/modem_secure_base.h
index 4e28fa7..19f0182 100644
--- a/src/kernel/linux/v4.19/drivers/misc/mediatek/eccci/mt6890/modem_secure_base.h
+++ b/src/kernel/linux/v4.19/drivers/misc/mediatek/eccci/mt6890/modem_secure_base.h
@@ -18,6 +18,7 @@
MD_CLOCK_REQUEST,
MD_POWER_CONFIG,
MD_FLIGHT_MODE_SET,
+ MD_HW_REMAP_CONFIG_SYNC,
};
diff --git a/src/kernel/linux/v4.19/drivers/misc/mediatek/medmcu/rv33/v02/medmcu_logger.c b/src/kernel/linux/v4.19/drivers/misc/mediatek/medmcu/rv33/v02/medmcu_logger.c
index f3efc22..55391b9 100644
--- a/src/kernel/linux/v4.19/drivers/misc/mediatek/medmcu/rv33/v02/medmcu_logger.c
+++ b/src/kernel/linux/v4.19/drivers/misc/mediatek/medmcu/rv33/v02/medmcu_logger.c
@@ -796,6 +796,8 @@
extern phys_addr_t gMedmcuDrb0PhyBase;
extern phys_addr_t gMedmcuDrb1PhyBase;
+extern void* getDRBtableAddress(int qid);
+
int print_medhw_dram(struct seq_file *seq) {
u32 i;
u32 *p;
@@ -991,6 +993,58 @@
} else {
pr_notice("+-----------------------------------------------+\n");
}
+
+ pr_notice("Dump DRB2...\n");
+ p = (u32 *)getDRBtableAddress(2);
+ if (seq != NULL) {
+ seq_puts(seq, " <<DRB2 DUMP>>\n");
+ } else {
+ pr_notice(" <<DRB2 DUMP>>\n");
+ }
+ if (p && p != NULL) {
+ for (i = 0; i < gMedmcuDrb0Size/4; i = i + 4) {
+ sprintf(buf, "0x%08llx : 0x%08x 0x%08x 0x%08x 0x%08x\n", gMedmcuDrb0PhyBase + i*4,
+ *(p + i), *(p + i + 1),
+ *(p + i + 2), *(p + i + 3));
+ if (seq != NULL) {
+ seq_printf(seq, "%s", buf);
+ } else {
+ pr_notice("[MEDHW] %s", buf);
+ }
+ }
+ }
+ if (seq != NULL) {
+ seq_puts(seq, "+-----------------------------------------------+\n");
+ seq_puts(seq, "\n");
+ } else {
+ pr_notice("+-----------------------------------------------+\n");
+ }
+
+ pr_notice("Dump DRB3...\n");
+ p = (u32 *)getDRBtableAddress(3);
+ if (seq != NULL) {
+ seq_puts(seq, " <<DRB3 DUMP>>\n");
+ } else {
+ pr_notice(" <<DRB3 DUMP>>\n");
+ }
+ if (p && p != NULL) {
+ for (i = 0; i < gMedmcuDrb0Size/4; i = i + 4) {
+ sprintf(buf, "0x%08llx : 0x%08x 0x%08x 0x%08x 0x%08x\n", gMedmcuDrb0PhyBase + i*4,
+ *(p + i), *(p + i + 1),
+ *(p + i + 2), *(p + i + 3));
+ if (seq != NULL) {
+ seq_printf(seq, "%s", buf);
+ } else {
+ pr_notice("[MEDHW] %s", buf);
+ }
+ }
+ }
+ if (seq != NULL) {
+ seq_puts(seq, "+-----------------------------------------------+\n");
+ seq_puts(seq, "\n");
+ } else {
+ pr_notice("+-----------------------------------------------+\n");
+ }
medhw_dram_logged = 1;//jb.qi change for medmcu sleep fail on 20230418
pr_notice("[MEDHW] read dram end\n");//jb.qi change for medmcu sleep fail on 20230418