[Feature] merge MTK MR3.0 from 20220916
Change-Id: I7e07c7c1a6069994f9938d3d8a01cac6fd3bc5ae
diff --git a/src/kernel/linux/v4.19/drivers/soc/mediatek/mtk-scpsys.c b/src/kernel/linux/v4.19/drivers/soc/mediatek/mtk-scpsys.c
index 20ebc23..d9736f0 100755
--- a/src/kernel/linux/v4.19/drivers/soc/mediatek/mtk-scpsys.c
+++ b/src/kernel/linux/v4.19/drivers/soc/mediatek/mtk-scpsys.c
@@ -186,6 +186,14 @@
CLK_HIFSEL,
CLK_JPGDEC,
CLK_AUDIO,
+ CLK_NETSYS1,
+ CLK_NETSYS2,
+ CLK_NETSYS3,
+ CLK_NETSYS4,
+ CLK_NETSYS5,
+ CLK_NETSYS6,
+ CLK_NETSYS7,
+ CLK_NETSYS8,
CLK_ETH1,
CLK_ETH2,
CLK_ETH3,
@@ -206,6 +214,14 @@
"hif_sel",
"jpgdec",
"audio",
+ "medsys_sel",
+ "netsys_sel",
+ "netsys_500m_sel",
+ "netsys_med_mcu_sel",
+ "netsys_wed_mcu_sel",
+ "netsys_2x_sel",
+ "sgmii_sel",
+ "sgmii_sbus_sel",
"snps_eth_312p5m_sel",
"snps_eth_250m_sel",
"snps_ptp_sel",
@@ -244,6 +260,7 @@
bool sram_iso_ctrl;
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
+ u32 sram_pdn_bits1;
u32 sram_pdn_bits2;
u32 sram_pdn_ack_bits2;
u32 bus_prot_mask;
@@ -459,29 +476,26 @@
u32 val;
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
int tmp;
+ u32 val1;
u32 val2;
u32 pdn_ack2 = scpd->data->sram_pdn_ack_bits2;
int tmp2;
-/*mt6880 pdn_ack1*/
- val = readl(net_sram_addr) & ~scpd->data->sram_pdn_bits;
+ int ret;
+
+pr_notice("netsys SRAM control step 1");
+ val = readl(net_sram_addr) | scpd->data->sram_pdn_bits;
writel(val, net_sram_addr);
- /* Either wait until SRAM_PDN_ACK all 0 or have a force wait */
- if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) {
- /*
- * Currently, MTK_SCPD_FWAIT_SRAM is necessary only for
- * MT7622_POWER_DOMAIN_WB and thus just a trivial setup
- * is applied here.
- */
- usleep_range(12000, 12100);
- } else {
- /* Either wait until SRAM_PDN_ACK all 1 or 0 */
- int ret = readl_poll_timeout(net_sram_addr, tmp,
- (tmp & pdn_ack) == 0,
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
- if (ret < 0)
- return ret;
- }
+ /* Either wait until SRAM_PDN_ACK all 1 or 0 */
+ ret = readl_poll_timeout(net_sram_addr, tmp,
+ (tmp & pdn_ack) == pdn_ack,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ if (ret < 0)
+ return ret;
+
+pr_notice("netsys SRAM control step 2");
+ val1 = readl(net_sram_addr) | scpd->data->sram_pdn_bits1;
+ writel(val1, net_sram_addr);
/*mt6880 pdn_ack2*/
@@ -505,6 +519,7 @@
return ret;
}
+pr_notice("netsys SRAM control step 3");
return 0;
}
@@ -513,26 +528,52 @@
u32 val;
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
int tmp;
+ u32 val1;
u32 val2;
u32 pdn_ack2 = scpd->data->sram_pdn_ack_bits2;
int tmp2;
+ int ret;
- val = readl(net_sram_addr) | scpd->data->sram_pdn_bits;
- writel(val, net_sram_addr);
-
- /* Either wait until SRAM_PDN_ACK all 1 or 0 */
- return readl_poll_timeout(net_sram_addr, tmp,
- (tmp & pdn_ack) == pdn_ack,
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
-
+pr_notice("netsys SRAM control step 1");
/*mt6880 pdn_ack2*/
val2 = readl(net_sram_addr) | scpd->data->sram_pdn_bits2;
writel(val2, net_sram_addr);
/* Either wait until SRAM_PDN_ACK all 1 or 0 */
- return readl_poll_timeout(net_sram_addr, tmp2,
+ ret = readl_poll_timeout(net_sram_addr, tmp2,
(tmp2 & pdn_ack2) == pdn_ack2,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ if (ret < 0)
+ return ret;
+
+pr_notice("netsys SRAM control step 2");
+ val1 = readl(net_sram_addr) & ~scpd->data->sram_pdn_bits1;
+ writel(val1, net_sram_addr);
+
+/*mt6880 pdn_ack1*/
+ val = readl(net_sram_addr) & ~scpd->data->sram_pdn_bits;
+ writel(val, net_sram_addr);
+
+ /* Either wait until SRAM_PDN_ACK all 0 or have a force wait */
+ if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) {
+ /*
+ * Currently, MTK_SCPD_FWAIT_SRAM is necessary only for
+ * MT7622_POWER_DOMAIN_WB and thus just a trivial setup
+ * is applied here.
+ */
+ usleep_range(12000, 12100);
+ } else {
+ /* Either wait until SRAM_PDN_ACK all 1 or 0 */
+ int ret = readl_poll_timeout(net_sram_addr, tmp,
+ (tmp & pdn_ack) == 0,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ if (ret < 0)
+ return ret;
+ }
+
+pr_notice("netsys SRAM control step 3");
+
+ return 0;
}
static int scpsys_bus_protect_enable(struct scp_domain *scpd)
@@ -1320,7 +1361,13 @@
*/
if(strcmp(genpd->name,"conn")){
if(strcmp(genpd->name,"ssusb_phy")==0)
- dev_err(&pdev->dev, "Skip ssusb_phy pwr_on \n");
+ dev_err(&pdev->dev, "Skip ssusb_phy & netsys pwr_on \n");
+ else if (strcmp(genpd->name,"netsys")==0){
+ ret = scpsys_clk_enable(scpd->clk, MAX_CLKS);
+ if (ret)
+ pr_notice("netsys clock on fail");
+ dev_err(&pdev->dev, "Skip netsys pwr_on \n");
+ }
else
genpd->power_on(genpd);
}
@@ -1987,6 +2034,29 @@
MT6890_TOP_AXI_PROT_EN_INFRA_VDNR_1_ETH,MT6890_TOP_AXI_PROT_EN_INFRA_VDNR_1_ETH,0),
},
},
+ [MT6890_POWER_DOMAIN_NETSYS] = {
+ .name = "netsys",
+ .sta_mask = BIT(19),
+ .ctl_offs = 0x34C,
+ .caps = MTK_SCPD_NETSYS_OPS,
+ .sram_pdn_bits = GENMASK(4, 4),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .sram_pdn_bits1 = GENMASK(1, 1),
+ .sram_pdn_bits2 = GENMASK(17, 17),
+ .sram_pdn_ack_bits2 = GENMASK(25, 25),
+ .clk_id = {CLK_NETSYS1, CLK_NETSYS2, CLK_NETSYS3, CLK_NETSYS4,
+ CLK_NETSYS5, CLK_NETSYS6, CLK_NETSYS7, CLK_NETSYS8},
+ /*.bp_table = {
+ BUS_PROT(IFR_TYPE, 0x0714, 0x0718, 0x0710, 0x0724,
+ MT6890_TOP_AXI_PROT_EN_2_NETSYS,MT6890_TOP_AXI_PROT_EN_2_NETSYS,0),
+ BUS_PROT(IFR_TYPE, 0x02A0, 0x02A4, 0x0220, 0x0228,
+ MT6890_TOP_AXI_PROT_EN_NETSYS,MT6890_TOP_AXI_PROT_EN_NETSYS,0),
+ BUS_PROT(IFR_TYPE, 0x02A0, 0x02A4, 0x0220, 0x0228,
+ MT6890_TOP_AXI_PROT_EN_NETSYS_2ND,MT6890_TOP_AXI_PROT_EN_NETSYS_2ND,0),
+ BUS_PROT(IFR_TYPE, 0x0714, 0x0718, 0x0710, 0x0724,
+ MT6890_TOP_AXI_PROT_EN_2_NETSYS_2ND,MT6890_TOP_AXI_PROT_EN_2_NETSYS_2ND,0),
+ },*/
+ },
[MT6890_POWER_DOMAIN_AUDIO] = {
.name = "audio",
.sta_mask = BIT(21),