[Feature]Merge MP1_MR1 from MTK
Change-Id: I3fc364555acf14f1c308b6be7b05f21f92757fd0
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890.c
index de820bc..897d0ef 100755
--- a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890.c
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890.c
@@ -522,7 +522,9 @@
"netsys_sel", 1, 1),
FACTOR(CLK_TOP_MEDSYS, "medsys_ck",
"medsys_sel", 1, 1),
- /* HSM isn't in kernel */
+ /* HSM CRYPTO isn't in kernel */
+ FACTOR(CLK_TOP_HSM_ARC, "hsm_arc_ck",
+ "hsm_arc_sel", 1, 1),
FACTOR(CLK_TOP_EIP97, "eip97_ck",
"eip97_sel", 1, 1),
FACTOR(CLK_TOP_SNPS_ETH_312P5M, "snps_eth_312p5m_ck",
@@ -857,6 +859,13 @@
"univpll_d7"
};
+static const char * const hsm_arc_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d8",
+ "mainpll_d4_d4",
+ "mainpll_d6_d2"
+};
+
static const char * const eip97_parents[] = {
"tck_26m_mx9_ck",
"net2pll_ck",
@@ -1174,9 +1183,13 @@
CLK_CFG_9_CLR/* set parent */, 16/* lsb */, 3/* width */,
INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
TOP_MUX_MEDSYS_SHIFT/* upd shift */),
- /* HSM isn't in kernel */
+ /* HSM crypto isn't in kernel */
/* CLK_CFG_10 */
- /* HSM isn't in kernel */
+ MUX_CLR_SET_UPD(CLK_TOP_HSM_ARC_SEL/* dts */, "hsm_arc_sel",
+ hsm_arc_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_HSM_ARC_SHIFT/* upd shift */),
MUX_CLR_SET_UPD(CLK_TOP_EIP97_SEL/* dts */, "eip97_sel",
eip97_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
CLK_CFG_10_CLR/* set parent */, 8/* lsb */, 3/* width */,
@@ -1445,8 +1458,13 @@
CLK_CFG_9_CLR/* set parent */, 16/* lsb */, 3/* width */,
23/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
TOP_MUX_MEDSYS_SHIFT/* upd shift */),
- /* HSM isn't in kernel. */
+ /* HSM crypto isn't in kernel. */
/* CLK_CFG_10 */
+ MUX_CLR_SET_UPD(CLK_TOP_HSM_ARC_SEL/* dts */, "hsm_arc_sel",
+ hsm_arc_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_HSM_ARC_SHIFT/* upd shift */),
MUX_CLR_SET_UPD(CLK_TOP_EIP97_SEL/* dts */, "eip97_sel",
eip97_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
CLK_CFG_10_CLR/* set parent */, 8/* lsb */, 3/* width */,