diff --git a/src/kernel/linux/v4.19/drivers/net/phy/marvell-88q.c b/src/kernel/linux/v4.19/drivers/net/phy/marvell-88q.c
index d37df67..c51090b 100755
--- a/src/kernel/linux/v4.19/drivers/net/phy/marvell-88q.c
+++ b/src/kernel/linux/v4.19/drivers/net/phy/marvell-88q.c
@@ -5,6 +5,8 @@
 #include <linux/module.h>
 #include <linux/phy.h>
 #include <linux/of.h>
+#include <linux/delay.h>
+
 
 #define PHY_ID_88Q2220			0x002b0b21
 
@@ -58,8 +60,6 @@
 
 	speed = be32_to_cpup(paddr);
 	master = be32_to_cpup(paddr + 1);
-printk("speed = %d\n",speed);
-printk("master = %d\n",master);
 	val = phy_read(phydev, Q2110_T1_PMA_PMD_CTRL);
 	if (val < 0)
 		return val;
@@ -72,23 +72,8 @@
 	if (val < 0)
 		return val;
         
-	/* Software Reset PHY */
-	//phy_write(phydev, (MII_ADDR_C45 | 0x030900), 0x8000);
-	//phy_write(phydev, (MII_ADDR_C45 | 0x03FFE4), 0x000C);
-	
-	val = phy_read(phydev, Q2110_PMA_PMD_CTRL);
-	if (val < 0)
-		return val;
-	val |= Q2110_PMA_PMD_RST;
-	val = phy_write(phydev, Q2110_PMA_PMD_CTRL, val);
-	if (val < 0)
-		return val;
-
-	do {
-		val = phy_read(phydev, Q2110_PMA_PMD_CTRL);
-		if (val < 0)
-			return val;
-	} while (val & Q2110_PMA_PMD_RST);
+	phy_write(phydev, (MII_ADDR_C45 | 0x030900), 0x8000);
+	phy_write(phydev, (MII_ADDR_C45 | 0x03FFE4), 0x000C);
 	
 	printk("q2110 dts init ok!!\n");
 
@@ -142,17 +127,33 @@
 
 static int q2110_config_init(struct phy_device *phydev)
 {
+    int i=0,mrvlId;
 	phydev->supported =
 		SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full;
 	phydev->advertising =
 		SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full;
 	phydev->state = PHY_NOLINK;
 	phydev->autoneg = AUTONEG_DISABLE;
-	
-printk("q2110_config_init \n");
-	q2110_dts_init(phydev);
+	phy_write(phydev, MII_ADDR_C45 | 0x010000, 0x840);
+	phy_write(phydev, MII_ADDR_C45 | 0x03FE1B, 0x48);
+	phy_write(phydev, MII_ADDR_C45 | 0x01FFE4, 0x6B6);
+	phy_write(phydev, MII_ADDR_C45 | 0x010000, 0x0);
+	phy_write(phydev, MII_ADDR_C45 | 0x030000, 0x0);
+	while (i < 5) {
+		mrvlId= phy_read(phydev, MII_ADDR_C45 | 0x03FFE4);
+		if (mrvlId == 0x06BA) {
+			break;
+		}
+		i++;
+		msleep(1);
+	}
+	phy_write(phydev, MII_ADDR_C45 | 0x078032, 0x2020);
+	phy_write(phydev, MII_ADDR_C45 | 0x078031, 0xA28);
+	phy_write(phydev, MII_ADDR_C45 | 0x078031, 0xC28);
 	q2110_timing_init(phydev);
 
+	q2110_dts_init(phydev);
+
 	return 0;
 }