[Bugfix][API-660]the sleep normal after reboot
Change-Id: Iab3c770c95172114f144ad928e2ded9e88bf186b
diff --git a/src/bsp/lk/lib/aee/mrdump_aee.c b/src/bsp/lk/lib/aee/mrdump_aee.c
index b2e03c2..ddc57f2 100644
--- a/src/bsp/lk/lib/aee/mrdump_aee.c
+++ b/src/bsp/lk/lib/aee/mrdump_aee.c
@@ -41,6 +41,8 @@
#include <string.h>
#ifdef MTK_PMIC_FULL_RESET
#include <platform/pmic.h>
+#include <platform/spmi/pmif.h> //jb.qi change for reboot when sleep on 20230309
+#include <platform/spmi/spmi.h> //jb.qi change for reboot when sleep on 20230309
#endif
#include "aee.h"
@@ -438,7 +440,9 @@
#ifdef MTK_PMIC_FULL_RESET
voprintf_debug("Ready for full pmic reset\n");
mrdump_write_result();
- pmic_cold_reset();
+ pmif_spmi_init(SPMI_MASTER_1);
+ pmic_reinit(); //jb.qi change for reboot when sleep on 20230309
+ pmic_cold_reset(); //jb.qi change for reboot when sleep on 20230309
#else
voprintf_debug("Ready for reset\n");
mrdump_write_result();
diff --git a/src/bsp/lk/platform/mt2735/drivers/dpm/dpm.h b/src/bsp/lk/platform/mt2735/drivers/dpm/dpm.h
index 94a654a..37cc34f 100644
--- a/src/bsp/lk/platform/mt2735/drivers/dpm/dpm.h
+++ b/src/bsp/lk/platform/mt2735/drivers/dpm/dpm.h
@@ -13,27 +13,35 @@
#include <platform/mt_typedefs.h>
#include <string.h>
#include <stdlib.h>
-
+/*jb.qi change for reboot when sleep on 20230309 start*/
+#if 0
#define DPM_CFG_CH0_BASE (0x10940000)
#define DRAMC_CH0_TOP5_BASE (0x10238000)
#define DPM_PM_SRAM_BASE (0x10900000)
#define DPM_DM_SRAM_BASE (0x10920000)
-
-#define DPM_VERSION (0x00000000) // DPM version
-#define DPM_HWID (0x00006873) // DPM HWID
+#endif
+/*jb.qi change for reboot when sleep on 20230309 end*/
+#define DPM_VERSION (0x00000001) // DPM version jb.qi change for reboot when sleep on 20230309
+#define DPM_HWID (0x00002735) // DPM HWID jb.qi change for reboot when sleep on 20230309
#define DPM_NUM (0x00000001) // DPM number
-#define DPM_HEAD_SIZE (0x00000020) // DPM header size
+#define DPM_HEAD_SIZE (0x00000024) // DPM header size jb.qi change for reboot when sleep on 20230309
#define DPM_DBG_LEN (0x48) // dpm dbg latch
#define DPM_CFG1_LEN (0x14) // dpm cfg1 latch
#define DPM_CFG2_LEN (0x8) // dpm cfg2 latch
#define DRAM_CHANNEL (0x2) // dramc AO latch
#define DDRPHY_LATCH_LEN (0x20) // ddrphy AO latch
+#define LATCH_PC_NUM 0x10 // dpm last 16 pc jb.qi change for reboot when sleep on 20230309
#define DPM_CFG_CH0 DPM_CFG_CH0_BASE
#define DPM_DBG_LATCH_CH0_OFST (0x7380)
#define DPM_CFG1_CH0_OFST (0x0064)
#define DPM_CFG2_CH0_OFST (0x014C)
-
+/*jb.qi change for reboot when sleep on 20230309 start*/
+#define SSPM_CFGREG_TBUF_SEL ((DPM_CFG_CH0_BASE) + 0x178)
+#define SSPM_CFGREG_TBUFL ((DPM_CFG_CH0_BASE) + 0x17C)
+#define SSPM_CFGREG_TBUFH ((DPM_CFG_CH0_BASE) + 0x180)
+#define SSPM_CFGREG_TBUF_WPTR ((DPM_CFG_CH0_BASE) + 0x4C)
+/*jb.qi change for reboot when sleep on 20230309 end*/
#define DDRPHY_AO_CH0 DRAMC_CH0_TOP5_BASE
#define DDRPHY_LATCH_OFFSET (0x1600)
#define CHANNEL_OFFSET (0x10000)
diff --git a/src/bsp/lk/platform/mt2735/drivers/pmic/pmic.c b/src/bsp/lk/platform/mt2735/drivers/pmic/pmic.c
index c0e48de..d36e99e 100644
--- a/src/bsp/lk/platform/mt2735/drivers/pmic/pmic.c
+++ b/src/bsp/lk/platform/mt2735/drivers/pmic/pmic.c
@@ -6,6 +6,7 @@
#include <platform/regulator/mtk_regulator_errno.h>
#include <platform/pmic/pmic.h>
#include <platform/pmic/mt6330.h>
+#include <platform/pmic/upmu_hw.h> //jb.qi change for reboot when sleep on 20230309
#ifdef EXT_BUCK_MT6315
#include <platform/pmic/mt6315-spmi.h>
@@ -20,7 +21,7 @@
void pmic_cold_reset(void)
{
-
+ pmic_config_interface(MT6330_PPCCTL1, 0x1, 0x1, 0x0); //jb.qi change for reboot when sleep on 20230309
}
/* show vcore for MD before MD boot up */
@@ -665,7 +666,7 @@
U32 ret_code = PMIC_TEST_PASS;
unsigned int val = 0;
- dprintf(INFO, "[PMIC]LK BL2 Start\n");
+ dprintf(ALWAYS, "[PMIC]LK BL2 Start\n"); //jb.qi change for reboot when sleep on 20230309
mt6330_sdev = get_spmi_device(SPMI_MASTER_1, SPMI_SLAVE_4);
if (!mt6330_sdev) {
@@ -673,7 +674,7 @@
return -ENODEV;
}
- dprintf(INFO, "[PMIC] CHIP Code = 0x30%x\n",
+ dprintf(ALWAYS, "[PMIC] CHIP Code = 0x30%x\n", //jb.qi change for reboot when sleep on 20230309
pmic_get_chip_version());
/* Boot debug status */
@@ -691,7 +692,7 @@
mt6315_spmi_probe();
#endif
- dprintf(INFO, "[PMIC]Init done\n");
+ dprintf(ALWAYS, "[PMIC]Init done\n"); //jb.qi change for reboot when sleep on 20230309
/* default disable smart reset, enable it by RGU driver */
pmic_enable_smart_reset(0, 0);
@@ -728,14 +729,14 @@
U32 pmic_reinit(void)
{
- dprintf(INFO, "[PMIC]re-init Start\n");
+ dprintf(ALWAYS, "[PMIC]re-init Start\n"); //jb.qi change for reboot when sleep on 20230309
mt6330_sdev = get_spmi_device(SPMI_MASTER_1, SPMI_SLAVE_4);
if (!mt6330_sdev) {
dprintf(INFO, "%s: get spmi device fail\n", __func__);
return -ENODEV;
}
- dprintf(INFO, "[PMIC] CHIP Code = 0x30%x\n",
+ dprintf(ALWAYS, "[PMIC] CHIP Code = 0x30%x\n", //jb.qi change for reboot when sleep on 20230309
pmic_get_chip_version());
mt6330_probe();
@@ -743,7 +744,7 @@
mt6315_spmi_probe();
#endif
- dprintf(INFO, "[PMIC]re-init done\n");
+ dprintf(ALWAYS, "[PMIC]re-init done\n"); //jb.qi change for reboot when sleep on 20230309
return 0;
}
diff --git a/src/bsp/lk/platform/mt2735/drivers/rules.mk b/src/bsp/lk/platform/mt2735/drivers/rules.mk
index b1bf5cb..46708a5 100644
--- a/src/bsp/lk/platform/mt2735/drivers/rules.mk
+++ b/src/bsp/lk/platform/mt2735/drivers/rules.mk
@@ -116,6 +116,7 @@
ifeq ($(MTK_KEDUMP_MINI_SUPPORT), yes)
MODULE_SRCS += \
+ $(LOCAL_DIR)/dpm/dpm_aee_dump.c \
$(LOCAL_DIR)/spm/spm_aee_dump.c \
$(LOCAL_DIR)/sspm/sspm_expdb.c
endif
diff --git a/src/bsp/lk/platform/mt2735/include/platform/mt_reg_base.h b/src/bsp/lk/platform/mt2735/include/platform/mt_reg_base.h
index 8aad211..c049ee5 100644
--- a/src/bsp/lk/platform/mt2735/include/platform/mt_reg_base.h
+++ b/src/bsp/lk/platform/mt2735/include/platform/mt_reg_base.h
@@ -72,6 +72,13 @@
#define INT_POL_SECCTL0 (MCUSYS_CFGREG_BASE + 0xA00) /* TODO: MT2735 */
#define SEC_POL_CTL_EN0 INT_POL_SECCTL0 /* TODO: MT2735 */
+/*jb.qi change for reboot when sleep on 20230309 start*/
+#define DRAMC_CH0_TOP5_BASE (IO_PHYS + 0x00238000)
+#define DPM_PM_SRAM_BASE (IO_PHYS + 0x00900000)
+#define DPM_DM_SRAM_BASE (IO_PHYS + 0x00920000)
+#define DPM_CFG_CH0_BASE (IO_PHYS + 0x00940000)
+/*jb.qi change for reboot when sleep on 20230309 end*/
+
/* GPIO register definitions */
#define GPIO_BASE (IO_PHYS + 0x00005000)
#define EINT_BASE (IO_PHYS + 0x0000B000)
diff --git a/src/bsp/lk/platform/mt2735/include/platform/pmic/pmic.h b/src/bsp/lk/platform/mt2735/include/platform/pmic/pmic.h
index 7d793e0..de40db2 100644
--- a/src/bsp/lk/platform/mt2735/include/platform/pmic/pmic.h
+++ b/src/bsp/lk/platform/mt2735/include/platform/pmic/pmic.h
@@ -121,6 +121,7 @@
extern void pl_hw_ulc_det(void);
extern void mt6330_dump_record_reg(struct spmi_device *dev);
extern U32 pmic_init (void);
+extern U32 pmic_reinit(void); //jb.qi change for reboot when sleep on 20230309
extern int pmic_get_auxadc_value(unsigned short channel);
extern U32 is_pmic_rtc_alarm(void);
extern U32 is_pmic_spar(void);