[Bugfix][API-660]add file for the sleep normal after reboot
Change-Id: I6a81cc338e3f2f0e5dbb26d02890164a5d27af60
diff --git a/src/bsp/lk/platform/mt2735/drivers/dpm/dpm_aee.h b/src/bsp/lk/platform/mt2735/drivers/dpm/dpm_aee.h
new file mode 100644
index 0000000..e9e4d44
--- /dev/null
+++ b/src/bsp/lk/platform/mt2735/drivers/dpm/dpm_aee.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ *
+ * Use of this source code is governed by a MIT-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/MIT
+ */
+
+#pragma once
+
+#include <debug.h>
+#include <platform/mt_reg_base.h>
+#include <platform/mt_typedefs.h>
+#include <string.h>
+#include <stdlib.h>
+
+//#define DPM_CFG_CH0_BASE (0x10940000+KERNEL_ASPACE_BASE)
+//#define DRAMC_CH0_TOP5_BASE (0x10238000+KERNEL_ASPACE_BASE)
+//#define DPM_PM_SRAM_BASE (0x10900000+KERNEL_ASPACE_BASE)
+//#define DPM_DM_SRAM_BASE (0x10920000+KERNEL_ASPACE_BASE)
+
+#define DPM_VERSION (0x00000001) // DPM version
+#define DPM_HWID (0x00002735) // DPM HWID
+#define DPM_NUM (0x00000001) // DPM number
+#define DPM_HEAD_SIZE (0x00000024) // DPM header size
+#define DPM_DBG_LEN (0x48) // dpm dbg latch
+#define DPM_CFG1_LEN (0x14) // dpm cfg1 latch
+#define DPM_CFG2_LEN (0x8) // dpm cfg2 latch
+#define DRAM_CHANNEL (0x2) // dramc AO latch
+#define DDRPHY_LATCH_LEN (0x20) // ddrphy AO latch
+#define LATCH_PC_NUM 0x10 // dpm last 16 pc
+
+#define DPM_CFG_CH0 DPM_CFG_CH0_BASE
+#define DPM_DBG_LATCH_CH0_OFST (0x7380)
+#define DPM_CFG1_CH0_OFST (0x0064)
+#define DPM_CFG2_CH0_OFST (0x014C)
+
+#define SSPM_CFGREG_TBUF_SEL ((DPM_CFG_CH0_BASE) + 0x178)
+#define SSPM_CFGREG_TBUFL ((DPM_CFG_CH0_BASE) + 0x17C)
+#define SSPM_CFGREG_TBUFH ((DPM_CFG_CH0_BASE) + 0x180)
+#define SSPM_CFGREG_TBUF_WPTR ((DPM_CFG_CH0_BASE) + 0x4C)
+
+#define DDRPHY_AO_CH0 DRAMC_CH0_TOP5_BASE
+#define DDRPHY_LATCH_OFFSET (0x1600)
+#define CHANNEL_OFFSET (0x10000)
+
+#define DPM_PM "dpmpm"
+#define DPM_DM "dpmdm"
+
+#define DPM_MEM_SIZE (0x00190000) // mblock_reserve requires max 100KB
+#define DPM_MEM_ALIGN (0x00190000) // 100KB
+#define DRAM_ADDR_MAX (0xFFFFFFFF) // max address can be remap
+#define DPM_CORE_DUMP_SIZE (0x1000) // 4KB
+#define DPM_REG_DUMP_SIZE (0x08b0) // 1.1KB
+#define DPM_DM_OFST (0x4000) // 16KB
+
+#define DPM_PM1_SRAM_BASE DPM_PM_SRAM_BASE
+#define DPM_DM1_SRAM_BASE DPM_DM_SRAM_BASE
+
+#define DPM_PM_SIZE_LIMIT (0x6000) // 24K
+
+#define DPM_CFG_CH0_BARGS_REG0_OFST (0x6004)
+#define DPM_CFG_CH0_BARGS_REG1_OFST 0x6008
+
+#define DRAMC_MCU_SPM_CON_OFST (0x3BC)
+#define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1)
+#define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4)
+#define DRAMC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 13)
+
+
+#define PT_MAGIC (0x58901690)
+#define PART_MAGIC (0x58881688)
+#define PART_EXT_MAGIC (0x58891689)
+#define PART_HDR_DATA_SIZE (512)
+
+typedef union {
+ struct {
+ unsigned int magic; /* partition magic */
+ unsigned int dsize; /* partition data size */
+ char name[32]; /* partition name */
+ unsigned int maddr; /* partition memory address */
+ unsigned int mode; /* maddr is counted from the beginning or end of RAM */
+ /* extension */
+ unsigned int ext_magic; /* always EXT_MAGIC */
+ unsigned int hdr_size; /* header size is 512 bytes currently, but may extend in the future */
+ unsigned int hdr_version; /* see HDR_VERSION */
+ unsigned int img_type; /* please refer to #define beginning with IMG_TYPE_ */
+ unsigned int img_list_end; /* end of image list? 0: this image is followed by another image 1: end */
+ unsigned int align_size; /* image size alignment setting in bytes, 16 by default for AES encryption */
+ unsigned int dsize_extend; /* high word of image size for 64 bit address support */
+ unsigned int maddr_extend; /* high word of image load address in RAM for 64 bit address support */
+ } info;
+ unsigned char data[PART_HDR_DATA_SIZE];
+} part_hdr_t;
diff --git a/src/bsp/lk/platform/mt2735/drivers/dpm/dpm_aee_dump.c b/src/bsp/lk/platform/mt2735/drivers/dpm/dpm_aee_dump.c
new file mode 100644
index 0000000..3b0864e
--- /dev/null
+++ b/src/bsp/lk/platform/mt2735/drivers/dpm/dpm_aee_dump.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ *
+ * Use of this source code is governed by a MIT-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/MIT
+ */
+#include "dpm_aee.h"
+#include <errno.h>
+#include <kernel/thread.h>
+#include <kernel/vm.h>
+#include <lib/bio.h>
+#include <lib/mempool.h>
+#include <platform/mboot_expdb.h>
+#include <platform/mt_gpt_v4.h>
+#include <platform/mtk_wdt.h>
+#include <stdbool.h>
+#define DPM_DBG_MODE (1)
+#define LOCAL_TRACE 1
+#if DPM_DBG_MODE
+#define dpm_dbg(f, ...) dprintf(ALWAYS, "[DPM][DBG] " f, ##__VA_ARGS__)
+#else
+#define dpm_dbg(f, ...) do{}while(0)
+#endif
+#define dpm_error(f, ...) dprintf(CRITICAL, "[DPM][ERROR] " f, ##__VA_ARGS__)
+#define DOWNLOAD_KEY "download:"
+#define MAX_SIZE (20)
+
+static void wake_dpm_sram_up(void)
+{
+ addr_t reg = SPM_BASE + DRAMC_MCU_SPM_CON_OFST;
+
+ DRV_WriteReg32(reg, DRV_Reg32(reg) | DRAMC_MCU_SRAM_SLEEP_B_LSB);
+ while (0 == (DRV_Reg32(reg) & DRAMC_MCU_SRAM_SLEEP_B_ACK_LSB))
+ dpm_dbg("waking up dpm SRAM\n");
+
+ DRV_WriteReg32(reg, DRV_Reg32(reg) | DRAMC_MCU_SRAM_ISOINT_B_LSB);
+}
+
+static unsigned int set_dpm_header(unsigned char *buf)
+{
+ unsigned int version = DPM_VERSION;
+ unsigned int hw_id = DPM_HWID;
+ unsigned int nr_dpm = DPM_NUM;
+ unsigned int nr_channel = DRAM_CHANNEL;
+ unsigned int coredump_sz = DPM_DM_OFST;
+ unsigned int lpif_sz = DPM_DBG_LEN;
+ unsigned int cfg_sz = DPM_CFG1_LEN + DPM_CFG2_LEN;
+#if DPM_VERSION >= 1
+ unsigned int last_pc_sz = (4 * (2 * LATCH_PC_NUM + 1));
+#endif
+ unsigned int dram_sz = DDRPHY_LATCH_LEN*DRAM_CHANNEL;
+ unsigned int length = 0;
+ length += sprintf(buf,
+ "DPM_VERSION: 0x%08x\n"
+ "DPM_HWID: 0x%08x\n"
+ "DPM_NUM: 0x%08x\n"
+ "DRAM_CHANNEL: 0x%08x\n"
+ "DPM_DM_OFST: 0x%08x\n"
+ "lpif_sz: 0x%08x\n"
+ "cfg_sz: 0x%08x\n"
+#if DPM_VERSION >= 1
+ "last_pc_sz: 0x%08x\n"
+#endif
+ "dram_sz: 0x%08x\n",
+ version, hw_id, nr_dpm, nr_channel,
+ coredump_sz, lpif_sz, cfg_sz,
+#if DPM_VERSION >= 1
+ last_pc_sz,
+#endif
+ dram_sz);
+ return length;
+}
+static void save_dpm_reg(AEE_DUMP_CALLBACK dev_write)
+{
+ unsigned char *buf = malloc(DPM_REG_DUMP_SIZE);
+#if DPM_VERSION >= 1
+ unsigned int *pc_latch = NULL;
+ int j = 0;
+#endif
+ unsigned int addr = 0;
+ unsigned int channel_index = 0;
+ unsigned int datasize = 0;
+ // Ensure dpm power on
+ wake_dpm_sram_up();
+ if (!buf) {
+ dprintf(CRITICAL, "[dpm] -ENOMEM\n");
+ return;
+ }
+ datasize += set_dpm_header(buf);
+ dpm_dbg("[dpm] set_dpm_header datasize: 0x%x\n", datasize);
+ dpm_dbg("[dpm]1 : 0x%x\n",DPM_CFG_CH0_BASE + DPM_DBG_LATCH_CH0_OFST);
+ dpm_dbg("[dpm] read:0x%x\n", readl(DPM_CFG_CH0_BASE + DPM_DBG_LATCH_CH0_OFST));
+ addr = DPM_CFG_CH0_BASE + DPM_DBG_LATCH_CH0_OFST;
+ dpm_dbg("[dpm] DPM_DBG_LATCH_CH0_OFST[0]: 0x%x\n", readl(DPM_CFG_CH0_BASE + DPM_DBG_LATCH_CH0_OFST));
+ for (int i = 0; i < DPM_DBG_LEN; i += sizeof(unsigned int))
+ datasize += sprintf(buf+datasize, "0x%08x: 0x%08x\n", addr + i,
+ readl(DPM_CFG_CH0_BASE + DPM_DBG_LATCH_CH0_OFST + i));
+ addr = DPM_CFG_CH0_BASE + DPM_CFG1_CH0_OFST;
+ dpm_dbg("[dpm] DPM_CFG1_CH0_OFST[0]: 0x%x\n", readl(DPM_CFG_CH0_BASE + DPM_CFG1_CH0_OFST));
+ for (int i = 0; i < DPM_CFG1_LEN; i += sizeof(unsigned int))
+ datasize += sprintf(buf+datasize, "0x%08x: 0x%08x\n", addr + i,
+ readl(DPM_CFG_CH0_BASE + DPM_CFG1_CH0_OFST + i));
+ addr = DPM_CFG_CH0_BASE + DPM_CFG2_CH0_OFST;
+ dpm_dbg("[dpm] DPM_CFG2_CH0_OFST[0]: 0x%x\n", readl(DPM_CFG_CH0_BASE + DPM_CFG2_CH0_OFST));
+ for (int i = 0; i < DPM_CFG2_LEN; i += sizeof(unsigned int))
+ datasize += sprintf(buf+datasize, "0x%08x: 0x%08x\n", addr + i,
+ readl(DPM_CFG_CH0_BASE + DPM_CFG2_CH0_OFST + i));
+ for (channel_index = 0; channel_index < DRAM_CHANNEL; channel_index++) {
+ //ddrphy RG
+ addr = DDRPHY_AO_CH0 + channel_index * CHANNEL_OFFSET + DDRPHY_LATCH_OFFSET;
+ dpm_dbg("[dpm] DDRPHY_LATCH_OFFSET[0]: 0x%x\n", readl(DDRPHY_AO_CH0 + channel_index * CHANNEL_OFFSET + DDRPHY_LATCH_OFFSET));
+ for (int i = 0; i < DDRPHY_LATCH_LEN; i += sizeof(unsigned int))
+ datasize += sprintf(buf+datasize, "0x%08x: 0x%08x\n", DDRPHY_AO_CH0 + channel_index * CHANNEL_OFFSET + DDRPHY_LATCH_OFFSET + i,
+ readl(DDRPHY_AO_CH0 + channel_index * CHANNEL_OFFSET + DDRPHY_LATCH_OFFSET + i));
+ }
+
+#if DPM_VERSION >= 1
+ dprintf(CRITICAL, "DPM last 16 pc dump !\n");
+ for (j = 0; j < LATCH_PC_NUM; j++) {
+ writel(j, SSPM_CFGREG_TBUF_SEL);
+ datasize += sprintf(buf+datasize, "SSPM_CFGREG_TBUFL_%d: 0x%08x\n", j, readl(SSPM_CFGREG_TBUFL));
+ datasize += sprintf(buf+datasize, "SSPM_CFGREG_TBUFH_%d: 0x%08x\n", j, readl(SSPM_CFGREG_TBUFH));
+ }
+ datasize += sprintf(buf+datasize, "SSPM_CFGREG_TBUF_WPTR: 0x%08x\n", j, readl(SSPM_CFGREG_TBUF_WPTR));
+ dprintf(CRITICAL, "DPM last 16 pc dump done!\n");
+#endif
+
+ //if (!dev_write(paddr_to_kvaddr(buf), datasize))
+ if (!dev_write((buf), datasize))
+ dprintf(CRITICAL, "[dpm] dev_write failed\n");
+ dpm_dbg("[dpm] %s total size: %u\n", __func__, datasize);
+ free(buf);
+ return;
+}
+AEE_EXPDB_INIT_HOOK(SYS_DPM_REG_DUMP, DPM_REG_DUMP_SIZE, save_dpm_reg);
+
+static void save_dpm_data(AEE_DUMP_CALLBACK dev_write)
+{
+ unsigned int addr = 0;
+ unsigned int channel_index = 0;
+ unsigned int datasize = 0;
+ unsigned int *buf = malloc(DPM_CORE_DUMP_SIZE);
+ // Ensure dpm power on
+ wake_dpm_sram_up();
+ if (!buf) {
+ dprintf(CRITICAL, "[dpm] -ENOMEM\n");
+ return;
+ }
+ dpm_dbg("[dpm] DPM_DM1_SRAM_BASE1: 0x%x\n",DPM_DM1_SRAM_BASE);
+ dpm_dbg("[dpm] DPM_DM1_SRAM_BASE read:0x%x\n", readl(DPM_DM1_SRAM_BASE));
+ //dpm_dbg("[dpm] DPM_DM1_SRAM_BASE+kernel:0x%x\n",DPM_DM1_SRAM_BASE+KERNEL_ASPACE_BASE);
+ //dpm_dbg("[dpm] DPM_DM1_SRAM_BASE read:0x%x\n", readl(DPM_DM1_SRAM_BASE+KERNEL_ASPACE_BASE));
+
+ addr = DPM_DM1_SRAM_BASE;
+ for (int i = 0; i < DPM_CORE_DUMP_SIZE; i += sizeof(unsigned int)) {
+
+ //dpm_dbg("[dpm] DPM_DM1_SRAM_BASE + i:0x%x\n", readl((DPM_DM1_SRAM_BASE + i)));
+ buf[datasize + i/sizeof(unsigned int)] = readl((DPM_DM1_SRAM_BASE + i));
+ //dpm_dbg("[dpm] buf[datasize + i]:0x%x\n", buf[datasize + i]);
+ }
+ datasize += DPM_DM_OFST;
+ //if (!dev_write(paddr_to_kvaddr(buf), datasize))
+ if (!dev_write((buf), datasize))
+ dprintf(CRITICAL, "[dpm] dev_write failed\n");
+ dpm_dbg("[dpm] %s total size: %u\n", __func__, datasize);
+ free(buf);
+ return;
+}
+AEE_EXPDB_INIT_HOOK(SYS_DPM_COREDUMP, DPM_CORE_DUMP_SIZE, save_dpm_data);
\ No newline at end of file