[Feature] add GA346 baseline version
Change-Id: Ic62933698569507dcf98240cdf5d9931ae34348f
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/Kconfig b/src/kernel/linux/v4.19/drivers/clk/mediatek/Kconfig
new file mode 100755
index 0000000..aefc152
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/Kconfig
@@ -0,0 +1,563 @@
+#
+# MediaTek Clock Drivers
+#
+menu "Clock driver for MediaTek SoC"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+
+config COMMON_CLK_MEDIATEK
+ bool
+ select RESET_CONTROLLER
+ ---help---
+ MediaTek SoCs' clock support.
+
+config COMMON_CLK_MT2701
+ bool "Clock driver for MediaTek MT2701"
+ depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK && ARM
+ ---help---
+ This driver supports MediaTek MT2701 basic clocks.
+
+config COMMON_CLK_MT2701_MMSYS
+ bool "Clock driver for MediaTek MT2701 mmsys"
+ depends on COMMON_CLK_MT2701
+ ---help---
+ This driver supports MediaTek MT2701 mmsys clocks.
+
+config COMMON_CLK_MT2701_IMGSYS
+ bool "Clock driver for MediaTek MT2701 imgsys"
+ depends on COMMON_CLK_MT2701
+ ---help---
+ This driver supports MediaTek MT2701 imgsys clocks.
+
+config COMMON_CLK_MT2701_VDECSYS
+ bool "Clock driver for MediaTek MT2701 vdecsys"
+ depends on COMMON_CLK_MT2701
+ ---help---
+ This driver supports MediaTek MT2701 vdecsys clocks.
+
+config COMMON_CLK_MT2701_HIFSYS
+ bool "Clock driver for MediaTek MT2701 hifsys"
+ depends on COMMON_CLK_MT2701
+ ---help---
+ This driver supports MediaTek MT2701 hifsys clocks.
+
+config COMMON_CLK_MT2701_ETHSYS
+ bool "Clock driver for MediaTek MT2701 ethsys"
+ depends on COMMON_CLK_MT2701
+ ---help---
+ This driver supports MediaTek MT2701 ethsys clocks.
+
+config COMMON_CLK_MT2701_BDPSYS
+ bool "Clock driver for MediaTek MT2701 bdpsys"
+ depends on COMMON_CLK_MT2701
+ ---help---
+ This driver supports MediaTek MT2701 bdpsys clocks.
+
+config COMMON_CLK_MT2701_AUDSYS
+ bool "Clock driver for Mediatek MT2701 audsys"
+ depends on COMMON_CLK_MT2701
+ ---help---
+ This driver supports Mediatek MT2701 audsys clocks.
+
+config COMMON_CLK_MT2701_G3DSYS
+ bool "Clock driver for MediaTek MT2701 g3dsys"
+ depends on COMMON_CLK_MT2701
+ ---help---
+ This driver supports MediaTek MT2701 g3dsys clocks.
+
+config COMMON_CLK_MT2712
+ bool "Clock driver for MediaTek MT2712"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK && ARM64
+ ---help---
+ This driver supports MediaTek MT2712 basic clocks.
+
+config COMMON_CLK_MT2712_BDPSYS
+ bool "Clock driver for MediaTek MT2712 bdpsys"
+ depends on COMMON_CLK_MT2712
+ ---help---
+ This driver supports MediaTek MT2712 bdpsys clocks.
+
+config COMMON_CLK_MT2712_IMGSYS
+ bool "Clock driver for MediaTek MT2712 imgsys"
+ depends on COMMON_CLK_MT2712
+ ---help---
+ This driver supports MediaTek MT2712 imgsys clocks.
+
+config COMMON_CLK_MT2712_JPGDECSYS
+ bool "Clock driver for MediaTek MT2712 jpgdecsys"
+ depends on COMMON_CLK_MT2712
+ ---help---
+ This driver supports MediaTek MT2712 jpgdecsys clocks.
+
+config COMMON_CLK_MT2712_MFGCFG
+ bool "Clock driver for MediaTek MT2712 mfgcfg"
+ depends on COMMON_CLK_MT2712
+ ---help---
+ This driver supports MediaTek MT2712 mfgcfg clocks.
+
+config COMMON_CLK_MT2712_MMSYS
+ bool "Clock driver for MediaTek MT2712 mmsys"
+ depends on COMMON_CLK_MT2712
+ ---help---
+ This driver supports MediaTek MT2712 mmsys clocks.
+
+config COMMON_CLK_MT2712_VDECSYS
+ bool "Clock driver for MediaTek MT2712 vdecsys"
+ depends on COMMON_CLK_MT2712
+ ---help---
+ This driver supports MediaTek MT2712 vdecsys clocks.
+
+config COMMON_CLK_MT2712_VENCSYS
+ bool "Clock driver for MediaTek MT2712 vencsys"
+ depends on COMMON_CLK_MT2712
+ ---help---
+ This driver supports MediaTek MT2712 vencsys clocks.
+
+config COMMON_CLK_MT6779
+ bool "Clock driver for MediaTek MT6779"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK && ARM64
+
+ help
+ This driver supports MediaTek MT6779 basic clocks,
+ which is used to control basic clock output.
+ If you wish to use clock resources from the MT6779 SOC,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_MMSYS
+ bool "Clock driver for MediaTek MT6779 mmsys"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports MediaTek MT6779 mmsys clocks,
+ which is used to control mmsys clock output.
+ If you wish to use clock resources from the mmsys device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_IMGSYS
+ bool "Clock driver for MediaTek MT6779 imgsys"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports MediaTek MT6779 imgsys clocks,
+ which is used to control imgsys clock output.
+ If you wish to use clock resources from the imgsys device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_IPESYS
+ bool "Clock driver for MediaTek MT6779 ipesys"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports MediaTek MT6779 ipesys clocks,
+ which is used to control ipesys clock output.
+ If you wish to use clock resources from the ipesys device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_CAMSYS
+ bool "Clock driver for MediaTek MT6779 camsys"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports MediaTek MT6779 camsys clocks,
+ which is used to control camsys clock output.
+ If you wish to use clock resources from the camsys device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_VDECSYS
+ bool "Clock driver for MediaTek MT6779 vdecsys"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports MediaTek MT6779 vdecsys clocks,
+ which is used to control vdecsys clock output.
+ If you wish to use clock resources from the vdecsys device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_VENCSYS
+ bool "Clock driver for MediaTek MT6779 vencsys"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports MediaTek MT6779 vencsys clocks,
+ which is used to control vencsys clock output.
+ If you wish to use clock resources from the vencsys device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_MFGCFG
+ bool "Clock driver for MediaTek MT6779 mfgcfg"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports MediaTek MT6779 mfgcfg clocks,
+ which is used to control mfgcfg clock output.
+ If you wish to use clock resources from the mfg device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_AUDSYS
+ bool "Clock driver for Mediatek MT6779 audsys"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports Mediatek MT6779 audsys clocks,
+ which is used to control audsys clock output.
+ If you wish to use clock resources from the audio device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_APUVCORESYS
+ bool "Clock driver for Mediatek MT6779 apuvcoresys"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports Mediatek MT6779 apuvcoresys clocks,
+ which is used to control apuvcoresys clock output.
+ If you wish to use clock resources from the apu vcore device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_APUCONNSYS
+ bool "Clock driver for Mediatek MT6779 apuconnsys"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports Mediatek MT6779 apuconnsys clocks,
+ which is used to control apuconnsys clock output.
+ If you wish to use clock resources from the apu conn device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_APU0SYS
+ bool "Clock driver for Mediatek MT6779 apu0sys"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports Mediatek MT6779 apu0sys clocks,
+ which is used to control apu0sys clock output.
+ If you wish to use clock resources from the apu0 device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_APU1SYS
+ bool "Clock driver for Mediatek MT6779 apu1sys"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports Mediatek MT6779 apu1sys clocks,
+ which is used to control apu1sys clock output.
+ If you wish to use clock resources from the apu1 device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6779_MDLASYS
+ bool "Clock driver for Mediatek MT6779 mdlasys"
+ depends on COMMON_CLK_MT6779
+ help
+ This driver supports Mediatek MT6779 mdlasys clocks,
+ which is used to control mdlasys clock output.
+ If you wish to use clock resources from the mdla device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6797
+ bool "Clock driver for MediaTek MT6797"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK && ARM64
+ ---help---
+ This driver supports MediaTek MT6797 basic clocks.
+
+config COMMON_CLK_MT6797_MMSYS
+ bool "Clock driver for MediaTek MT6797 mmsys"
+ depends on COMMON_CLK_MT6797
+ ---help---
+ This driver supports MediaTek MT6797 mmsys clocks.
+
+config COMMON_CLK_MT6797_IMGSYS
+ bool "Clock driver for MediaTek MT6797 imgsys"
+ depends on COMMON_CLK_MT6797
+ ---help---
+ This driver supports MediaTek MT6797 imgsys clocks.
+
+config COMMON_CLK_MT6797_VDECSYS
+ bool "Clock driver for MediaTek MT6797 vdecsys"
+ depends on COMMON_CLK_MT6797
+ ---help---
+ This driver supports MediaTek MT6797 vdecsys clocks.
+
+config COMMON_CLK_MT6797_VENCSYS
+ bool "Clock driver for MediaTek MT6797 vencsys"
+ depends on COMMON_CLK_MT6797
+ ---help---
+ This driver supports MediaTek MT6797 vencsys clocks.
+
+config COMMON_CLK_MT6880
+ bool "Clock driver for MediaTek MT6880"
+ select COMMON_CLK_MEDIATEK
+ ---help---
+ This driver supports MediaTek MT6880 basic clocks,
+ which is used to control basic clock output.
+ If you wish to use clock resources from the MT6880 SOC,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6880_AUDIOSYS
+ bool "Clock driver for MediaTek MT6880 audiosys"
+ depends on COMMON_CLK_MT6880
+ ---help---
+ This driver supports MediaTek MT6880 audiosys clocks,
+ which is used to control audiosys clock output.
+ If you wish to use clock resources from the audiosys device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6880_DBGSYS_DEM
+ bool "Clock driver for MediaTek MT6880 dbgsys_dem"
+ depends on COMMON_CLK_MT6880
+ ---help---
+ This driver supports MediaTek MT6880 dbgsys_dem clocks,
+ which is used to control dbgsys_dem clock output.
+ If you wish to use clock resources from the dbgsys_dem device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6880_GCE
+ bool "Clock driver for MediaTek MT6880 gce"
+ depends on COMMON_CLK_MT6880
+ ---help---
+ This driver supports MediaTek MT6880 gce clocks,
+ which is used to control gce clock output.
+ If you wish to use clock resources from the gce device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6880_IMP_IIC_WRAP_E
+ bool "Clock driver for MediaTek MT6880 imp_iic_wrap_e"
+ depends on COMMON_CLK_MT6880
+ ---help---
+ This driver supports MediaTek MT6880 imp_iic_wrap_e clocks,
+ which is used to control imp_iic_wrap_e clock output.
+ If you wish to use clock resources from the imp_iic_wrap_e device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6880_MFGSYS
+ bool "Clock driver for MediaTek MT6880 mfgsys"
+ depends on COMMON_CLK_MT6880
+ ---help---
+ This driver supports MediaTek MT6880 mfgsys clocks,
+ which is used to control mfgsys clock output.
+ If you wish to use clock resources from the mfgsys device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6880_MMSYS_CONFIG
+ bool "Clock driver for MediaTek MT6880 mmsys_config"
+ depends on COMMON_CLK_MT6880
+ ---help---
+ This driver supports MediaTek MT6880 mmsys_config clocks,
+ which is used to control mmsys_config clock output.
+ If you wish to use clock resources from the mmsys_config device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6890
+ bool "Clock driver for MediaTek MT6890"
+ select COMMON_CLK_MEDIATEK
+ ---help---
+ This driver supports MediaTek MT6890 basic clocks,
+ which is used to control basic clock output.
+ If you wish to use clock resources from the MT6890 SOC,
+ say Y. Otherwise, pls say N.
+
+config COMMON_CLK_MT6890_AUDIOSYS
+ bool "Clock driver for MediaTek MT6890 audiosys"
+ depends on COMMON_CLK_MT6890
+ ---help---
+ This driver supports MediaTek MT6890 audiosys clocks,
+ which is used to control audiosys clock output.
+ If you wish to use clock resources from the audiosys device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6890_DBGSYS_DEM
+ bool "Clock driver for MediaTek MT6890 dbgsys_dem"
+ depends on COMMON_CLK_MT6890
+ ---help---
+ This driver supports MediaTek MT6890 dbgsys_dem clocks,
+ which is used to control dbgsys_dem clock output.
+ If you wish to use clock resources from the dbgsys_dem device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6890_GCE
+ bool "Clock driver for MediaTek MT6890 gce"
+ depends on COMMON_CLK_MT6890
+ ---help---
+ This driver supports MediaTek MT6890 gce clocks,
+ which is used to control gce clock output.
+ If you wish to use clock resources from the gce device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6890_IMP_IIC_WRAP_E
+ bool "Clock driver for MediaTek MT6890 imp_iic_wrap_e"
+ depends on COMMON_CLK_MT6890
+ ---help---
+ This driver supports MediaTek MT6890 imp_iic_wrap_e clocks,
+ which is used to control imp_iic_wrap_e clock output.
+ If you wish to use clock resources from the imp_iic_wrap_e device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6890_MFGSYS
+ bool "Clock driver for MediaTek MT6890 mfgsys"
+ depends on COMMON_CLK_MT6890
+ ---help---
+ This driver supports MediaTek MT6890 mfgsys clocks,
+ which is used to control mfgsys clock output.
+ If you wish to use clock resources from the mfgsys device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT6890_MMSYS_CONFIG
+ bool "Clock driver for MediaTek MT6890 mmsys_config"
+ depends on COMMON_CLK_MT6890
+ ---help---
+ This driver supports MediaTek MT6890 mmsys_config clocks,
+ which is used to control mmsys_config clock output.
+ If you wish to use clock resources from the mmsys_config device,
+ say Y. Otherwise, say N.
+
+config COMMON_CLK_MT7622
+ bool "Clock driver for MediaTek MT7622"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ ---help---
+ This driver supports MediaTek MT7622 basic clocks and clocks
+ required for various periperals found on MediaTek.
+
+config COMMON_CLK_MT7622_ETHSYS
+ bool "Clock driver for MediaTek MT7622 ETHSYS"
+ depends on COMMON_CLK_MT7622
+ ---help---
+ This driver add support for clocks for Ethernet and SGMII
+ required on MediaTek MT7622 SoC.
+
+config COMMON_CLK_MT7622_HIFSYS
+ bool "Clock driver for MediaTek MT7622 HIFSYS"
+ depends on COMMON_CLK_MT7622
+ ---help---
+ This driver supports MediaTek MT7622 HIFSYS clocks providing
+ to PCI-E and USB.
+
+config COMMON_CLK_MT7622_AUDSYS
+ bool "Clock driver for MediaTek MT7622 AUDSYS"
+ depends on COMMON_CLK_MT7622
+ ---help---
+ This driver supports MediaTek MT7622 AUDSYS clocks providing
+ to audio consumers such as I2S and TDM.
+
+config COMMON_CLK_MT7629
+ bool "Clock driver for MediaTek MT7629"
+ depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK && ARM
+ ---help---
+ This driver supports MediaTek MT7629 basic clocks and clocks
+ required for various periperals found on MediaTek.
+
+config COMMON_CLK_MT7629_ETHSYS
+ bool "Clock driver for MediaTek MT7629 ETHSYS"
+ depends on COMMON_CLK_MT7629
+ ---help---
+ This driver add support for clocks for Ethernet and SGMII
+ required on MediaTek MT7629 SoC.
+
+config COMMON_CLK_MT7629_HIFSYS
+ bool "Clock driver for MediaTek MT7629 HIFSYS"
+ depends on COMMON_CLK_MT7629
+ ---help---
+ This driver supports MediaTek MT7629 HIFSYS clocks providing
+ to PCI-E and USB.
+
+config COMMON_CLK_MT8135
+ bool "Clock driver for MediaTek MT8135"
+ depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK && ARM
+ ---help---
+ This driver supports MediaTek MT8135 clocks.
+
+config COMMON_CLK_MT8168
+ bool "Clock driver for MediaTek MT8168"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK && ARM64
+ ---help---
+ This driver supports MediaTek MT8168 basic clocks.
+
+config COMMON_CLK_MT8168_APU
+ bool "Clock driver for MediaTek MT8168 apu"
+ depends on COMMON_CLK_MT8168
+ ---help---
+ This driver supports MediaTek MT8168 apu clocks.
+
+config COMMON_CLK_MT8168_CAMSYS
+ bool "Clock driver for MediaTek MT8168 camsys"
+ depends on COMMON_CLK_MT8168
+ ---help---
+ This driver supports MediaTek MT8168 camsys clocks.
+
+config COMMON_CLK_MT8168_MFGCFG
+ bool "Clock driver for MediaTek MT8168 mfgcfg"
+ depends on COMMON_CLK_MT8168
+ ---help---
+ This driver supports MediaTek MT8168 mfgcfg clocks.
+
+config COMMON_CLK_MT8168_MMSYS
+ bool "Clock driver for MediaTek MT8168 mmsys"
+ depends on COMMON_CLK_MT8168
+ ---help---
+ This driver supports MediaTek MT8168 mmsys clocks.
+
+config COMMON_CLK_MT8168_VDECSYS
+ bool "Clock driver for MediaTek MT8168 vdecsys"
+ depends on COMMON_CLK_MT8168
+ ---help---
+ This driver supports MediaTek MT8168 vdecsys clocks.
+
+config COMMON_CLK_MT8168_VENCSYS
+ bool "Clock driver for MediaTek MT8168 vencsys"
+ depends on COMMON_CLK_MT8168
+ ---help---
+ This driver supports MediaTek MT8168 vencsys clocks.
+
+config COMMON_CLK_MT8173
+ bool "Clock driver for MediaTek MT8173"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ ---help---
+ This driver supports MediaTek MT8173 clocks.
+
+config COMMON_CLK_MTK_FREQ_HOPPING
+ tristate "MediaTek FREQHOPPING driver"
+ help
+ FREQHOPPING driver support for MediaTek SOC
+ If you want to use MediaTek FREQHOPPING driver,
+ say Y or M here.
+ If unsure, say N.
+
+config COMMON_CLK_MTK_FREQ_HOPPING_DEBUG
+ bool "Mediate Freq Hopping debug fs"
+ depends on DEBUG_FS && COMMON_CLK_MTK_FREQ_HOPPING
+ help
+ This option is for debugging purpose
+ say Y to use debugfs interface to control
+ Freqhopping.
+ Otherwise, say N
+
+config COMMON_CLK_MTK_FREQ_HOPPING_SUBSYS
+ bool
+ depends on COMMON_CLK_MTK_FREQ_HOPPING_SSPM || COMMON_CLK_MTK_FREQ_HOPPING_MCUPM
+ help
+ If FREQHOPPING HW is controlled by other processor,
+ such as SSPM, this should be set.
+
+config COMMON_CLK_MTK_FREQ_HOPPING_SSPM
+ bool "Mediatek FREQHOPPING controlled by SSPM"
+ depends on COMMON_CLK_MTK_FREQ_HOPPING && MTK_TINYSYS_SSPM_SUPPORT
+ select COMMON_CLK_MTK_FREQ_HOPPING_SUBSYS
+ help
+ If FREQHOPPING HW is controlled by SSPM,
+ say Y here.
+ Otherwise, say N.
+ Enabling this config will auto set COMMON_CLK_MTK_FREQ_HOPPING_SUBSYS
+
+config COMMON_CLK_MTK_FREQ_HOPPING_MCUPM
+ bool "Mediatek FREQHOPPING controlled by MCUPM"
+ depends on COMMON_CLK_MTK_FREQ_HOPPING && MTK_TINYSYS_MCUPM_SUPPORT
+ select COMMON_CLK_MTK_FREQ_HOPPING_SUBSYS
+ help
+ If FREQHOPPING HW is controlled by MCUPM,
+ say Y here.
+ Otherwise, say N.
+ Enabling this config will auto set COMMON_CLK_MTK_FREQ_HOPPING_SUBSYS
+
+endmenu
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/Makefile b/src/kernel/linux/v4.19/drivers/clk/mediatek/Makefile
new file mode 100755
index 0000000..1a0db7b
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/Makefile
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0
+ccflags-y += -I$(srctree)/include/linux/soc/mediatek/
+
+ifeq ($(CONFIG_MTK_GCOV_KERNEL),y)
+GCOV_PROFILE := y
+endif
+
+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o clkchk.o
+#obj-$(CONFIG_COMMON_CLK_MT6779) += clk-mt6779.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_MMSYS) += clk-mt6779-mm.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_IMGSYS) += clk-mt6779-img.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_IPESYS) += clk-mt6779-ipe.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_CAMSYS) += clk-mt6779-cam.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_VDECSYS) += clk-mt6779-vdec.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_VENCSYS) += clk-mt6779-venc.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_MFGCFG) += clk-mt6779-mfg.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_AUDSYS) += clk-mt6779-aud.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_APUVCORESYS) += clk-mt6779-apuvcore.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_APUCONNSYS) += clk-mt6779-apuconn.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_APU0SYS) += clk-mt6779-apu0.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_APU1SYS) += clk-mt6779-apu1.o
+#obj-$(CONFIG_COMMON_CLK_MT6779_MDLASYS) += clk-mt6779-mdla.o
+obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
+obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
+obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
+obj-$(CONFIG_COMMON_CLK_MT6797_VDECSYS) += clk-mt6797-vdec.o
+obj-$(CONFIG_COMMON_CLK_MT6797_VENCSYS) += clk-mt6797-venc.o
+obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
+obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
+obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
+obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
+obj-$(CONFIG_COMMON_CLK_MT2701_G3DSYS) += clk-mt2701-g3d.o
+obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
+obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
+obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
+obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
+obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o clkchk-mt2712.o
+obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o
+obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o
+obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o
+obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
+obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
+obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
+obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
+obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622.o
+obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o
+obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o
+obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o
+obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
+obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
+obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
+obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+#obj-$(CONFIG_COMMON_CLK_MT8168) += clk-mt8168.o clk-fixup-div.o clkchk-mt8168.o
+#obj-$(CONFIG_COMMON_CLK_MT8168_APU) += clk-mt8168-apu.o
+#obj-$(CONFIG_COMMON_CLK_MT8168_CAMSYS) += clk-mt8168-cam.o
+#obj-$(CONFIG_COMMON_CLK_MT8168_MFGCFG) += clk-mt8168-mfg.o
+#obj-$(CONFIG_COMMON_CLK_MT8168_MMSYS) += clk-mt8168-mm.o
+#obj-$(CONFIG_COMMON_CLK_MT8168_VDECSYS) += clk-mt8168-vdec.o
+#obj-$(CONFIG_COMMON_CLK_MT8168_VENCSYS) += clk-mt8168-venc.o
+obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
+obj-$(CONFIG_COMMON_CLK_MT6880) += clk-mt6880.o clk-mtk-v1.o clkdbg.o clkchk.o clk-bringup.o clkchk-mt6880.o clkdbg-mt6880.o
+#obj-$(CONFIG_COMMON_CLK_MT6880) += clkdbg-mt6880.o clkchk-mt6880.o
+obj-$(CONFIG_COMMON_CLK_MT6880_AUDIOSYS) += clk-mt6880-audsys.o
+obj-$(CONFIG_COMMON_CLK_MT6880_DBGSYS_DEM) += clk-mt6880-dbgsys_dem.o
+obj-$(CONFIG_COMMON_CLK_MT6880_GCE) += clk-mt6880-gce.o
+obj-$(CONFIG_COMMON_CLK_MT6880_IMP_IIC_WRAP_E) += clk-mt6880-impe.o
+obj-$(CONFIG_COMMON_CLK_MT6880_MFGSYS) += clk-mt6880-mfgcfg.o
+obj-$(CONFIG_COMMON_CLK_MT6880_MMSYS_CONFIG) += clk-mt6880-mm.o
+obj-$(CONFIG_COMMON_CLK_MT6890) += clk-mt6890.o clk-mtk-v1.o clkdbg.o clkchk.o clk-bringup.o clkchk-mt6890.o clkdbg-mt6890.o
+#obj-$(CONFIG_COMMON_CLK_MT6890) += clkdbg-mt6890.o clkchk-mt6890.o
+obj-$(CONFIG_COMMON_CLK_MT6890_AUDIOSYS) += clk-mt6890-audsys.o
+obj-$(CONFIG_COMMON_CLK_MT6890_DBGSYS_DEM) += clk-mt6890-dbgsys_dem.o
+obj-$(CONFIG_COMMON_CLK_MT6890_GCE) += clk-mt6890-gce.o
+obj-$(CONFIG_COMMON_CLK_MT6890_IMP_IIC_WRAP_E) += clk-mt6890-impe.o
+obj-$(CONFIG_COMMON_CLK_MT6890_MFGSYS) += clk-mt6890-mfgcfg.o
+obj-$(CONFIG_COMMON_CLK_MT6890_MMSYS_CONFIG) += clk-mt6890-mm.o
+ifeq ($(CONFIG_DEBUG_FS), y)
+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clkdbg.o
+obj-$(CONFIG_COMMON_CLK_MT2712) += clkdbg-mt2712.o
+#obj-$(CONFIG_COMMON_CLK_MT8168) += clkdbg-mt8168.o
+endif
+obj-$(CONFIG_COMMON_CLK_MTK_FREQ_HOPPING) += fhctl.o
+fhctl-y += clk-fhctl.o
+fhctl-$(CONFIG_DEBUG_FS) += clk-fhctl-debug.o
+ifneq ($(CONFIG_COMMON_CLK_MTK_FREQ_HOPPING_SUBSYS),y)
+fhctl-y += clk-fhctl-ap.o
+else ifeq ($(CONFIG_COMMON_CLK_MTK_FREQ_HOPPING_MCUPM),y)
+fhctl-$(CONFIG_COMMON_CLK_MTK_FREQ_HOPPING_MCUPM) += clk-fhctl-mcupm.o
+else
+ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/
+fhctl-$(CONFIG_COMMON_CLK_MTK_FREQ_HOPPING_SSPM) += clk-fhctl-sspm.o
+endif
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-apmixed.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-apmixed.c
new file mode 100644
index 0000000..5303c59
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-apmixed.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#include "clk-mtk.h"
+
+#define REF2USB_TX_EN BIT(0)
+#define REF2USB_TX_LPF_EN BIT(1)
+#define REF2USB_TX_OUT_EN BIT(2)
+#define REF2USB_EN_MASK (REF2USB_TX_EN | REF2USB_TX_LPF_EN | \
+ REF2USB_TX_OUT_EN)
+
+struct mtk_ref2usb_tx {
+ struct clk_hw hw;
+ void __iomem *base_addr;
+};
+
+static inline struct mtk_ref2usb_tx *to_mtk_ref2usb_tx(struct clk_hw *hw)
+{
+ return container_of(hw, struct mtk_ref2usb_tx, hw);
+}
+
+static int mtk_ref2usb_tx_is_prepared(struct clk_hw *hw)
+{
+ struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
+
+ return (readl(tx->base_addr) & REF2USB_EN_MASK) == REF2USB_EN_MASK;
+}
+
+static int mtk_ref2usb_tx_prepare(struct clk_hw *hw)
+{
+ struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
+ u32 val;
+
+ val = readl(tx->base_addr);
+
+ val |= REF2USB_TX_EN;
+ writel(val, tx->base_addr);
+ udelay(100);
+
+ val |= REF2USB_TX_LPF_EN;
+ writel(val, tx->base_addr);
+
+ val |= REF2USB_TX_OUT_EN;
+ writel(val, tx->base_addr);
+
+ return 0;
+}
+
+static void mtk_ref2usb_tx_unprepare(struct clk_hw *hw)
+{
+ struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
+ u32 val;
+
+ val = readl(tx->base_addr);
+ val &= ~REF2USB_EN_MASK;
+ writel(val, tx->base_addr);
+}
+
+static const struct clk_ops mtk_ref2usb_tx_ops = {
+ .is_prepared = mtk_ref2usb_tx_is_prepared,
+ .prepare = mtk_ref2usb_tx_prepare,
+ .unprepare = mtk_ref2usb_tx_unprepare,
+};
+
+struct clk * __init mtk_clk_register_ref2usb_tx(const char *name,
+ const char *parent_name, void __iomem *reg)
+{
+ struct mtk_ref2usb_tx *tx;
+ struct clk_init_data init = {};
+ struct clk *clk;
+
+ tx = kzalloc(sizeof(*tx), GFP_KERNEL);
+ if (!tx)
+ return ERR_PTR(-ENOMEM);
+
+ tx->base_addr = reg;
+ tx->hw.init = &init;
+
+ init.name = name;
+ init.ops = &mtk_ref2usb_tx_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ clk = clk_register(NULL, &tx->hw);
+
+ if (IS_ERR(clk)) {
+ pr_err("Failed to register clk %s: %ld\n", name, PTR_ERR(clk));
+ kfree(tx);
+ }
+
+ return clk;
+}
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-bringup.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-bringup.c
new file mode 100755
index 0000000..37327cf
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-bringup.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2020 MediaTek Inc.
+
+ */
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+static const struct of_device_id bring_up_id_table[] = {
+ { .compatible = "mediatek,clk-bring-up",},
+ { .compatible = "mediatek,mt8163-bring-up",},
+ { .compatible = "mediatek,mt8173-bring-up",},
+ { },
+};
+MODULE_DEVICE_TABLE(of, bring_up_id_table);
+static int bring_up_probe(struct platform_device *pdev)
+{
+ struct clk *clk;
+ int clk_con, i;
+ int ret = 0;
+ clk_con = of_count_phandle_with_args(pdev->dev.of_node, "clocks",
+ "#clock-cells");
+ pr_notice("sum: %d\n", clk_con);
+ for (i = 0; i < clk_con; i++) {
+ clk = of_clk_get(pdev->dev.of_node, i);
+ if (IS_ERR(clk)) {
+ long ret = PTR_ERR(clk);
+ if (ret == -EPROBE_DEFER)
+ pr_notice("clk %d is not ready\n", i);
+ else
+ pr_notice("get clk %d fail, ret=%d, clk_con=%d\n",
+ i, (int)ret, clk_con);
+ } else {
+ pr_notice("get clk [%d]: %s ok\n", i,
+ __clk_get_name(clk));
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ pr_err("cannot force-on bringup clk node\n");
+ pr_notice("enable clk %d fail, ret=%d, clk_con=%d\n",
+ i, (int)ret, clk_con);
+ }
+ }
+ }
+ return ret;
+}
+static int bring_up_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+static struct platform_driver clk_bring_up = {
+ .probe = bring_up_probe,
+ .remove = bring_up_remove,
+ .driver = {
+ .name = "clk_bring_up",
+ .owner = THIS_MODULE,
+ .of_match_table = bring_up_id_table,
+ },
+};
+module_platform_driver(clk_bring_up);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-cpumux.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-cpumux.c
new file mode 100644
index 0000000..6c7eaa2
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-cpumux.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/slab.h>
+
+#include "clk-mtk.h"
+#include "clk-cpumux.h"
+
+static inline struct mtk_clk_cpumux *to_mtk_clk_cpumux(struct clk_hw *_hw)
+{
+ return container_of(_hw, struct mtk_clk_cpumux, hw);
+}
+
+static u8 clk_cpumux_get_parent(struct clk_hw *hw)
+{
+ struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
+ unsigned int val;
+
+ regmap_read(mux->regmap, mux->reg, &val);
+
+ val >>= mux->shift;
+ val &= mux->mask;
+
+ return val;
+}
+
+static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
+ u32 mask, val;
+
+ val = index << mux->shift;
+ mask = mux->mask << mux->shift;
+
+ return regmap_update_bits(mux->regmap, mux->reg, mask, val);
+}
+
+static const struct clk_ops clk_cpumux_ops = {
+ .get_parent = clk_cpumux_get_parent,
+ .set_parent = clk_cpumux_set_parent,
+};
+
+static struct clk *
+mtk_clk_register_cpumux(const struct mtk_composite *mux,
+ struct regmap *regmap)
+{
+ struct mtk_clk_cpumux *cpumux;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
+ if (!cpumux)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = mux->name;
+ init.ops = &clk_cpumux_ops;
+ init.parent_names = mux->parent_names;
+ init.num_parents = mux->num_parents;
+ init.flags = mux->flags;
+
+ cpumux->reg = mux->mux_reg;
+ cpumux->shift = mux->mux_shift;
+ cpumux->mask = BIT(mux->mux_width) - 1;
+ cpumux->regmap = regmap;
+ cpumux->hw.init = &init;
+
+ clk = clk_register(NULL, &cpumux->hw);
+ if (IS_ERR(clk))
+ kfree(cpumux);
+
+ return clk;
+}
+
+int mtk_clk_register_cpumuxes(struct device_node *node,
+ const struct mtk_composite *clks, int num,
+ struct clk_onecell_data *clk_data)
+{
+ int i;
+ struct clk *clk;
+ struct regmap *regmap;
+
+ regmap = syscon_node_to_regmap(node);
+ if (IS_ERR(regmap)) {
+ pr_err("Cannot find regmap for %pOF: %ld\n", node,
+ PTR_ERR(regmap));
+ return PTR_ERR(regmap);
+ }
+
+ for (i = 0; i < num; i++) {
+ const struct mtk_composite *mux = &clks[i];
+
+ clk = mtk_clk_register_cpumux(mux, regmap);
+ if (IS_ERR(clk)) {
+ pr_err("Failed to register clk %s: %ld\n",
+ mux->name, PTR_ERR(clk));
+ continue;
+ }
+
+ clk_data->clks[mux->id] = clk;
+ }
+
+ return 0;
+}
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-cpumux.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-cpumux.h
new file mode 100644
index 0000000..dddaad5
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-cpumux.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DRV_CLK_CPUMUX_H
+#define __DRV_CLK_CPUMUX_H
+
+struct mtk_clk_cpumux {
+ struct clk_hw hw;
+ struct regmap *regmap;
+ u32 reg;
+ u32 mask;
+ u8 shift;
+};
+
+int mtk_clk_register_cpumuxes(struct device_node *node,
+ const struct mtk_composite *clks, int num,
+ struct clk_onecell_data *clk_data);
+
+#endif /* __DRV_CLK_CPUMUX_H */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-ap.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-ap.c
new file mode 100644
index 0000000..78c6ac5
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-ap.c
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Pierre Lee <pierre.lee@mediatek.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include "clk-fhctl.h"
+
+#define PERCENT_TO_DDSLMT(dds, percent_m10) \
+ ((((dds) * (percent_m10)) >> 5) / 100)
+
+
+#define POSDIV_LSB 24
+#define POSDIV_MASK 0x7
+
+
+static int mt_fh_ipi_init(void)
+{
+ return 0;
+}
+
+
+static int __mt_fh_hw_hopping(struct clk_mt_fhctl *fh,
+ int pll_id, unsigned int new_dds,
+ int postdiv)
+{
+ unsigned int dds_mask, con_temp;
+ unsigned int mon_dds = 0;
+ int ret;
+ struct clk_mt_fhctl_regs *fh_regs;
+ struct clk_mt_fhctl_pll_data *pll_data;
+
+ fh_regs = fh->fh_regs;
+ pll_data = fh->pll_data;
+ dds_mask = fh->pll_data->dds_mask;
+
+ if (new_dds > dds_mask)
+ return -EINVAL;
+
+ /* 1. sync ncpo to DDS of FHCTL */
+ writel((readl(fh_regs->reg_con_pcw) & pll_data->dds_mask) |
+ FH_FHCTLX_PLL_TGL_ORG, fh_regs->reg_dds);
+
+ /* 2. enable DVFS and Hopping control */
+
+ /* enable dvfs mode */
+ fh_set_field(fh_regs->reg_cfg, FH_SFSTRX_EN, 1);
+ /* enable hopping */
+ fh_set_field(fh_regs->reg_cfg, FH_FHCTLX_EN, 1);
+
+ /* for slope setting. */
+
+ writel(pll_data->slope0_value, fh_regs->reg_slope0);
+ /* SLOPE1 is for MEMPLL */
+ writel(pll_data->slope1_value, fh_regs->reg_slope1);
+
+ /* 3. switch to hopping control */
+ fh_set_field(fh_regs->reg_hp_en, (0x1U << pll_id),
+ REG_HP_EN_FHCTL_CTR);
+
+ /* 4. set DFS DDS */
+ writel((new_dds) | (FH_FHCTLX_PLL_DVFS_TRI), fh_regs->reg_dvfs);
+
+ /* 4.1 ensure jump to target DDS */
+ /* Wait 1000 us until DDS stable */
+ ret = readl_poll_timeout_atomic(fh_regs->reg_mon, mon_dds,
+ (mon_dds&pll_data->dds_mask) == new_dds, 10, 1000);
+ if (ret)
+ pr_info("ERROR %s: target_dds=0x%x, mon_dds=0x%x",
+ __func__, new_dds, (mon_dds&pll_data->dds_mask));
+
+ if (postdiv == -1) {
+ /* Don't change DIV for fhctl UT */
+ con_temp = readl(fh_regs->reg_con_pcw) & (~dds_mask);
+ con_temp = (con_temp |
+ (readl(fh_regs->reg_mon) & dds_mask) |
+ FH_XXPLL_CON_PCWCHG);
+ } else {
+ con_temp = readl(fh_regs->reg_con_pcw) & (~dds_mask);
+ con_temp = con_temp & ~(POSDIV_MASK << POSDIV_LSB);
+ con_temp = (con_temp |
+ (readl(fh_regs->reg_mon) & dds_mask) |
+ (postdiv & POSDIV_MASK) << POSDIV_LSB |
+ FH_XXPLL_CON_PCWCHG);
+ }
+
+ /* 5. write back to ncpo */
+ writel(con_temp, fh_regs->reg_con_pcw);
+
+ /* 6. switch to APMIXEDSYS control */
+ fh_set_field(fh_regs->reg_hp_en, BIT(pll_id),
+ REG_HP_EN_APMIXEDSYS_CTR);
+
+
+ return 0;
+}
+
+
+static int clk_mt_fh_hw_pll_init(struct clk_mt_fhctl *fh)
+{
+ struct clk_mt_fhctl_regs *fh_regs;
+ struct clk_mt_fhctl_pll_data *pll_data;
+ int pll_id;
+ unsigned int mask;
+
+ pr_debug("mt_fh_pll_init() start ");
+
+ pll_id = fh->pll_data->pll_id;
+ fh_regs = fh->fh_regs;
+ pll_data = fh->pll_data;
+
+ mask = 1 << pll_id;
+
+ if (fh_regs == NULL) {
+ pr_info("ERROR fh_reg (%d) is NULL", pll_id);
+ return -EFAULT;
+ }
+
+ if (pll_data == NULL) {
+ pr_info("ERROR pll_data (%d) is NULL", pll_id);
+ return -EFAULT;
+ }
+
+ fh_set_field(fh_regs->reg_clk_con, mask, 1);
+
+ /* Release software-reset to reset */
+ fh_set_field(fh_regs->reg_rst_con, mask, 0);
+ fh_set_field(fh_regs->reg_rst_con, mask, 1);
+
+ writel(0x00000000, fh_regs->reg_cfg); /* No SSC/FH enabled */
+ writel(0x00000000, fh_regs->reg_updnlmt); /* clr all setting */
+ writel(0x00000000, fh_regs->reg_dds); /* clr all settings */
+
+ /* Check default enable SSC */
+ if (pll_data->pll_default_ssc_rate != 0) {
+ // Default Enable SSC to 0~-N%;
+ fh->hal_ops->pll_ssc_enable(fh, pll_data->pll_default_ssc_rate);
+ }
+
+ return 0;
+}
+
+static int clk_mt_fh_hw_pll_unpause(struct clk_mt_fhctl *fh)
+{
+ int pll_id;
+ struct clk_mt_fhctl_regs *fh_regs;
+ unsigned long flags = 0;
+
+
+ pll_id = fh->pll_data->pll_id;
+ fh_regs = fh->fh_regs;
+
+ if (fh->pll_data->pll_type != FH_PLL_TYPE_CPU) {
+ pr_info("%s not support unpause.", fh->pll_data->pll_name);
+ return -EFAULT;
+ }
+
+ pr_debug("%s fh_pll_id:%d", __func__, pll_id);
+
+ spin_lock_irqsave(fh->lock, flags);
+
+ /* unpause */
+ fh_set_field(fh_regs->reg_cfg, FH_FHCTLX_CFG_PAUSE, 0);
+
+ spin_unlock_irqrestore(fh->lock, flags);
+
+ return 0;
+}
+
+static int clk_mt_fh_hw_pll_pause(struct clk_mt_fhctl *fh)
+{
+ int pll_id;
+ struct clk_mt_fhctl_regs *fh_regs;
+ unsigned long flags = 0;
+
+ pll_id = fh->pll_data->pll_id;
+ fh_regs = fh->fh_regs;
+
+ if (fh->pll_data->pll_type != FH_PLL_TYPE_CPU) {
+ pr_info("%s not support pause.", fh->pll_data->pll_name);
+ return -EFAULT;
+ }
+
+ pr_debug("%s fh_pll_id:%d", __func__, pll_id);
+
+ spin_lock_irqsave(fh->lock, flags);
+
+ /* pause */
+ fh_set_field(fh_regs->reg_cfg, FH_FHCTLX_CFG_PAUSE, 1);
+
+ spin_unlock_irqrestore(fh->lock, flags);
+
+ return 0;
+}
+
+static int clk_mt_fh_hw_pll_ssc_disable(struct clk_mt_fhctl *fh)
+{
+ int pll_id;
+ unsigned long flags = 0;
+ struct clk_mt_fhctl_regs *fh_regs;
+ struct clk_mt_fhctl_pll_data *pll_data;
+
+
+ pll_id = fh->pll_data->pll_id;
+ fh_regs = fh->fh_regs;
+ pll_data = fh->pll_data;
+
+ if (pll_data->pll_type == FH_PLL_TYPE_NOT_SUPPORT) {
+ pr_info("%s not support SSC.", pll_data->pll_name);
+ return -EPERM;
+ }
+
+ pr_debug("fh_pll_id:%d", pll_id);
+
+ spin_lock_irqsave(fh->lock, flags);
+
+ /* Set the relative registers */
+ fh_set_field(fh_regs->reg_cfg, FH_FRDDSX_EN, 0);
+ fh_set_field(fh_regs->reg_cfg, FH_FHCTLX_EN, 0);
+
+ /* Switch to APMIXEDSYS control */
+ fh_set_field(fh_regs->reg_hp_en, BIT(pll_id),
+ REG_HP_EN_APMIXEDSYS_CTR);
+
+ spin_unlock_irqrestore(fh->lock, flags);
+
+ /* Wait for DDS to be stable */
+ udelay(30);
+
+ return 0;
+}
+
+static int clk_mt_fh_hw_pll_ssc_enable(struct clk_mt_fhctl *fh, int ssc_rate)
+{
+ int pll_id;
+ unsigned long flags = 0;
+ unsigned int dds_mask;
+ unsigned int updnlmt_val;
+ struct clk_mt_fhctl_regs *fh_regs;
+ struct clk_mt_fhctl_pll_data *pll_data;
+
+
+ pll_id = fh->pll_data->pll_id;
+ fh_regs = fh->fh_regs;
+ pll_data = fh->pll_data;
+ dds_mask = fh->pll_data->dds_mask;
+
+ if (pll_data->pll_type == FH_PLL_TYPE_NOT_SUPPORT) {
+ pr_info("%s not support SSC.", pll_data->pll_name);
+ return -EPERM;
+ }
+
+ pr_debug("pll_id:%d ssc:0~-%d%%", pll_id, ssc_rate);
+
+ spin_lock_irqsave(fh->lock, flags);
+
+ /* Set the relative parameter registers (dt/df/upbnd/downbnd) */
+ fh_set_field(fh_regs->reg_cfg, MASK_FRDDSX_DYS, REG_CFG_DF_VAL);
+ fh_set_field(fh_regs->reg_cfg, MASK_FRDDSX_DTS, REG_CFG_DT_VAL);
+
+ writel((readl(fh_regs->reg_con_pcw) & pll_data->dds_mask) |
+ FH_FHCTLX_PLL_TGL_ORG, fh_regs->reg_dds);
+
+ /* Calculate UPDNLMT */
+ updnlmt_val = PERCENT_TO_DDSLMT((readl(fh_regs->reg_dds) &
+ dds_mask), ssc_rate) << 16;
+
+ writel(updnlmt_val, fh_regs->reg_updnlmt);
+
+ /* Switch to FHCTL_CORE controller - Original design */
+ fh_set_field(fh_regs->reg_hp_en, (0x1U << pll_id),
+ REG_HP_EN_FHCTL_CTR);
+
+ /* Enable SSC */
+ fh_set_field(fh_regs->reg_cfg, FH_FRDDSX_EN, 1);
+ /* Enable Hopping control */
+ fh_set_field(fh_regs->reg_cfg, FH_FHCTLX_EN, 1);
+
+ /* Keep last ssc rate */
+ fh->pll_data->pll_default_ssc_rate = ssc_rate;
+
+ spin_unlock_irqrestore(fh->lock, flags);
+
+ return 0;
+}
+
+static int clk_mt_fh_hw_pll_hopping(struct clk_mt_fhctl *fh,
+ unsigned int new_dds,
+ int postdiv)
+{
+ int pll_id;
+ int ret;
+ unsigned long flags = 0;
+ unsigned int dds_mask;
+ unsigned int updnlmt_val;
+ unsigned int must_restore_ssc = 0;
+ struct clk_mt_fhctl_regs *fh_regs;
+ struct clk_mt_fhctl_pll_data *pll_data;
+
+
+ pll_id = fh->pll_data->pll_id;
+ fh_regs = fh->fh_regs;
+ pll_data = fh->pll_data;
+ dds_mask = pll_data->dds_mask;
+
+ if ((fh->pll_data->pll_type == FH_PLL_TYPE_NOT_SUPPORT) ||
+ (fh->pll_data->pll_type == FH_PLL_TYPE_CPU)) {
+ pr_info("%s not support hopping in AP side",
+ pll_data->pll_name);
+ return -EPERM;
+ }
+
+ pr_debug("fh_pll_id:%d", pll_id);
+
+ spin_lock_irqsave(fh->lock, flags);
+
+ /* Check SSC status. */
+ fh_get_field(fh_regs->reg_cfg, FH_FRDDSX_EN, must_restore_ssc);
+ if (must_restore_ssc) {
+ unsigned int pll_dds = 0;
+ unsigned int mon_dds = 0;
+
+ /* only when SSC is enable, turn off ARMPLL hopping */
+ /* disable SSC mode */
+ fh_set_field(fh_regs->reg_cfg, FH_FRDDSX_EN, 0);
+ /* disable dvfs mode */
+ fh_set_field(fh_regs->reg_cfg, FH_SFSTRX_EN, 0);
+ /* disable hp ctl */
+ fh_set_field(fh_regs->reg_cfg, FH_FHCTLX_EN, 0);
+
+ pll_dds = (readl(fh_regs->reg_dds)) & pll_data->dds_mask;
+
+ /* Wait 1000 us until DDS stable */
+ ret = readl_poll_timeout_atomic(fh_regs->reg_mon, mon_dds,
+ (mon_dds&pll_data->dds_mask) == pll_dds, 10, 1000);
+ if (ret)
+ pr_info("ERROR %s: target_dds=0x%x, mon_dds=0x%x",
+ __func__, pll_dds, mon_dds&pll_data->dds_mask);
+
+ }
+
+ ret = __mt_fh_hw_hopping(fh, pll_id, new_dds, postdiv);
+ if (ret)
+ pr_info("__mt_fh_hw_hopping error:%d", ret);
+
+
+ /* Enable SSC status, if need. */
+ if (must_restore_ssc) {
+ /* disable SSC mode */
+ fh_set_field(fh_regs->reg_cfg, FH_FRDDSX_EN, 0);
+ /* disable dvfs mode */
+ fh_set_field(fh_regs->reg_cfg, FH_SFSTRX_EN, 0);
+ /* disable hp ctl */
+ fh_set_field(fh_regs->reg_cfg, FH_FHCTLX_EN, 0);
+
+ fh_set_field(fh_regs->reg_cfg, MASK_FRDDSX_DYS, REG_CFG_DF_VAL);
+ fh_set_field(fh_regs->reg_cfg, MASK_FRDDSX_DTS, REG_CFG_DT_VAL);
+
+ writel((readl(fh_regs->reg_con_pcw) & pll_data->dds_mask) |
+ FH_FHCTLX_PLL_TGL_ORG, fh_regs->reg_dds);
+
+ /* Calculate UPDNLMT */
+ updnlmt_val = PERCENT_TO_DDSLMT(
+ (readl(fh_regs->reg_dds) & dds_mask),
+ pll_data->pll_default_ssc_rate) << 16;
+
+ writel(updnlmt_val, fh_regs->reg_updnlmt);
+
+ /* Switch to FHCTL_CORE controller - Original design */
+ fh_set_field(fh_regs->reg_hp_en,
+ (0x1U << pll_id), REG_HP_EN_FHCTL_CTR);
+
+ /* enable SSC mode */
+ fh_set_field(fh_regs->reg_cfg, FH_FRDDSX_EN, 1);
+ /* enable hopping ctl */
+ fh_set_field(fh_regs->reg_cfg, FH_FHCTLX_EN, 1);
+ }
+
+ spin_unlock_irqrestore(fh->lock, flags);
+
+ return ret;
+}
+
+const struct fhctl_ipi_ops ipi_ops = {
+ .ipi_init = mt_fh_ipi_init,
+};
+
+const struct clk_mt_fhctl_hal_ops mt_fhctl_hal_ops = {
+ .pll_init = clk_mt_fh_hw_pll_init,
+ .pll_unpause = clk_mt_fh_hw_pll_unpause,
+ .pll_pause = clk_mt_fh_hw_pll_pause,
+ .pll_ssc_disable = clk_mt_fh_hw_pll_ssc_disable,
+ .pll_ssc_enable = clk_mt_fh_hw_pll_ssc_enable,
+ .pll_hopping = clk_mt_fh_hw_pll_hopping,
+};
+
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-debug.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-debug.c
new file mode 100644
index 0000000..122ce0a
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-debug.c
@@ -0,0 +1,467 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Pierre Lee <pierre.lee@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/proc_fs.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
+#include "clk-fhctl.h"
+#include "clk-mtk.h"
+#include <mt-plat/aee.h>
+
+
+
+
+
+struct pll_status fh_log;
+static struct mtk_fhctl *g_p_fhctl;
+
+
+/*****************************************************************
+ * Global variable operation
+ ****************************************************************/
+static void __set_fhctl(struct mtk_fhctl *pfhctl)
+{
+ g_p_fhctl = pfhctl;
+}
+
+static struct mtk_fhctl *__get_fhctl(void)
+{
+ return g_p_fhctl;
+}
+
+
+enum FH_DEBUG_CMD_ID {
+ FH_DBG_CMD_ID = 0x1000,
+ FH_DBG_CMD_DVFS = 0x1001,
+ FH_DBG_CMD_DVFS_API = 0x1002,
+ FH_DBG_CMD_DVFS_SSC_ENABLE = 0x1003,
+ FH_DBG_CMD_SSC_ENABLE = 0x1004,
+ FH_DBG_CMD_SSC_DISABLE = 0x1005,
+ FH_DBG_CMD_TR_BEGIN_LOW = 0x2001,
+ FH_DBG_CMD_TR_BEGIN_HIGH = 0x2002,
+ FH_DBG_CMD_TR_END_LOW = 0x2003,
+ FH_DBG_CMD_TR_END_HIGH = 0x2004,
+ FH_DBG_CMD_TR_ID = 0x2005,
+ FH_DBG_CMD_TR_VAL = 0x2006,
+ FH_DBG_CMD_MAX
+};
+
+void mt_fhctl_exit_debugfs(struct mtk_fhctl *fhctl)
+{
+ debugfs_remove_recursive(fhctl->debugfs_root);
+}
+
+void mt_fh_dump_register(void)
+{
+ int pll_id;
+ struct mtk_fhctl *fhctl = __get_fhctl();
+ struct clk_mt_fhctl_regs *fh_regs;
+
+ if (fhctl == NULL){
+ WARN_ON(1);
+ pr_info("[Hopping] get NULL fhctl obj \n");
+ }
+
+
+ for (pll_id = 0 ; pll_id < fhctl->pll_num ; pll_id++) {
+
+ if (fhctl->fh_tbl[pll_id] == NULL || (fhctl->idmap[pll_id] == -1)){
+ continue;
+ }
+ fh_regs = fhctl->fh_tbl[pll_id]->fh_regs ;
+
+ pr_info("PLL_ID:%d HP_EN:%08x\n",pll_id, readl(fh_regs->reg_hp_en));
+ pr_info("P:%s CFG:%08x DVFS:%08x DDS:%08x MON:%08x CON_PCW:%08x\n",
+ fhctl->fh_tbl[pll_id]->pll_data->pll_name,
+ readl(fh_regs->reg_cfg),
+ readl(fh_regs->reg_dvfs),
+ readl(fh_regs->reg_dds),
+ readl(fh_regs->reg_mon),
+ readl(fh_regs->reg_con_pcw));
+
+ }
+}
+
+
+void mt_fhctl_log_b4_hopping (struct clk_mt_fhctl *fhctl, unsigned int target_dds, unsigned int tx_id, struct pll_status *fh_log){
+
+ unsigned int pll_id = fhctl->pll_data->pll_id;
+
+ //recording
+ fh_log->before_dds = readl(fhctl->fh_regs->reg_con_pcw) & (0x3FFFF);
+
+ fh_log->target_dds = target_dds;
+
+ fh_log->pll_id = pll_id;
+
+ fh_log->tx_id = tx_id;
+}
+
+
+void mt_fhctl_log_af_hopping (struct clk_mt_fhctl *fhctl, int ret_from_ipi, unsigned int ack_data, struct pll_status *fh_log, void (*ipi_get_data)(unsigned int), u64 time_ns){
+
+ unsigned int pll_id = fhctl->pll_data->pll_id;
+ unsigned int aft_dds = readl(fhctl->fh_regs->reg_con_pcw) & (0x3FFFFF);
+ struct mtk_fhctl *fh = __get_fhctl();
+
+ if ((aft_dds != fh_log->target_dds) || (fh_log->tx_id != ack_data) || (ret_from_ipi != 0)) {
+ pr_info("[Hopping] PLL_ID:%d TX_ID:%d ACK_DATA:%d", pll_id, fh_log->tx_id, ack_data);
+ pr_info("[Hopping] pll_id %d hopping fail, cfg %x, bef %x, aft %x, tgt %x, ret_from_ipi %d, time_ns %llx\n",
+ pll_id,
+ readl(fhctl->fh_regs->reg_cfg),
+ fh_log->before_dds,
+ aft_dds,
+ fh_log->target_dds,
+ ret_from_ipi,
+ time_ns);
+
+ fh_log->after_dds = aft_dds;
+
+ mt_fh_dump_register();
+
+ if (fh->reg_tr)
+ pr_info("[Hopping] reg_tr<%x>\n", readl(fh->reg_tr));
+
+ ipi_get_data(FH_DBG_CMD_TR_BEGIN_LOW);
+ ipi_get_data(FH_DBG_CMD_TR_BEGIN_HIGH);
+ ipi_get_data(FH_DBG_CMD_TR_END_LOW);
+ ipi_get_data(FH_DBG_CMD_TR_END_HIGH);
+ ipi_get_data(FH_DBG_CMD_TR_ID);
+ ipi_get_data(FH_DBG_CMD_TR_VAL);
+
+ aee_kernel_warning_api(__FILE__, __LINE__,
+ DB_OPT_DUMMY_DUMP | DB_OPT_FTRACE,
+ "[Hopping] IPI to CPUEB\n",
+ "IPI timeout");
+
+ //BUG();
+ }
+
+}
+
+
+static int __fh_ctrl_cmd_handler(struct clk_mt_fhctl *fh,
+ unsigned int cmd,
+ int pll_id,
+ unsigned int p1)
+
+{
+ int ret;
+
+ pr_info("pll_id:0x%x cmd: %x p1:%x", pll_id, cmd, p1);
+
+ if (fh == NULL) {
+ pr_info("Error: fh is null!");
+ return 0;
+ }
+
+ switch (cmd) {
+ case FH_DBG_CMD_SSC_ENABLE:
+ ret = fh->hal_ops->pll_ssc_enable(fh, p1);
+ break;
+ case FH_DBG_CMD_SSC_DISABLE:
+ ret = fh->hal_ops->pll_ssc_disable(fh);
+ break;
+ case FH_DBG_CMD_DVFS:
+ ret = fh->hal_ops->pll_hopping(fh, p1, -1);
+ break;
+ case FH_DBG_CMD_DVFS_API:
+ ret = !(mtk_fh_set_rate(pll_id, p1, -1));
+ break;
+ default:
+ pr_info(" Not Support CMD:%x\n", cmd);
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret)
+ pr_info(" Debug CMD fail err:%d\n", ret);
+
+ return ret;
+}
+
+
+/***************************************************************************
+ * FHCTL Debug CTRL OPS
+ ***************************************************************************/
+static ssize_t fh_ctrl_proc_write(struct file *file,
+ const char *buffer, size_t count, loff_t *data)
+{
+ int ret, n;
+ char kbuf[256];
+ int pll_id;
+ size_t len = 0;
+ unsigned int cmd, p1;
+ struct clk_mt_fhctl *fh;
+ struct mtk_fhctl *fhctl = file->f_inode->i_private;
+
+ len = min(count, (sizeof(kbuf) - 1));
+
+ pr_info("count: %ld", count);
+ if (count == 0)
+ return -1;
+
+ if (count > 255)
+ count = 255;
+
+ ret = copy_from_user(kbuf, buffer, count);
+ if (ret < 0)
+ return -1;
+
+ kbuf[count] = '\0';
+
+ n = sscanf(kbuf, "%x %x %x", &cmd, &pll_id, &p1);
+ if ((n != 3) && (n != 2)) {
+ pr_info("error input format\n");
+ return -EINVAL;
+ }
+
+ pr_info("pll:0x%x cmd:%x p1:%x", pll_id, cmd, p1);
+
+ if ((cmd < FH_DBG_CMD_ID) && (cmd > FH_DBG_CMD_MAX)) {
+ pr_info("cmd not support:%x", cmd);
+ return -EINVAL;
+ }
+
+ if (pll_id >= fhctl->pll_num) {
+ pr_info("pll_id is illegal:%d", pll_id);
+ return -EINVAL;
+ }
+
+ fh = mtk_fh_get_fh_obj_tbl(fhctl, pll_id);
+
+ __fh_ctrl_cmd_handler(fh, cmd, pll_id, p1);
+
+ pr_debug("reg_cfg:0x%08x", readl(fh->fh_regs->reg_cfg));
+ pr_debug("reg_updnlmt:0x%08x", readl(fh->fh_regs->reg_updnlmt));
+ pr_debug("reg_dds:0x%08x", readl(fh->fh_regs->reg_dds));
+ pr_debug("reg_dvfs:0x%08x", readl(fh->fh_regs->reg_dvfs));
+ pr_debug("reg_mon:0x%08x", readl(fh->fh_regs->reg_mon));
+ pr_debug("reg_con0:0x%08x", readl(fh->fh_regs->reg_con0));
+ pr_debug("reg_con_pcw:0x%08x", readl(fh->fh_regs->reg_con_pcw));
+
+ return count;
+}
+
+static int fh_ctrl_proc_read(struct seq_file *m, void *v)
+{
+ int i;
+ struct mtk_fhctl *fhctl = m->private;
+
+ seq_puts(m, "====== FHCTL CTRL Description ======\n");
+
+ seq_puts(m, "[PLL Name and ID Table]\n");
+ for (i = 0 ; i < fhctl->pll_num ; i++)
+ seq_printf(m, "PLL_ID:%d PLL_NAME: %s\n",
+ i, fhctl->fh_tbl[i]->pll_data->pll_name);
+
+ seq_puts(m, "\n[Command Description]\n");
+ seq_puts(m, " [SSC Enable]\n");
+ seq_puts(m, " /> echo '1004 <PLL-ID> <SSC-Rate>' > ctrl\n");
+ seq_puts(m, " Example: echo '1004 2 2' > ctrl\n");
+ seq_puts(m, " [SSC Disable]\n");
+ seq_puts(m, " /> echo '1005 <PLL-ID>' > ctrl\n");
+ seq_puts(m, " Example: echo '1005 2' > ctrl\n");
+ seq_puts(m, " [SSC Hopping]\n");
+ seq_puts(m, " /> echo '1001 <PLL-ID> <DDS>' > ctrl\n");
+ seq_puts(m, " Example: echo '1001 2 ec200' > ctrl\n");
+ seq_puts(m, " [CLK API Hopping]\n");
+ seq_puts(m, " /> echo '1002 <PLL-ID> <DDS>' > ctrl\n");
+ seq_puts(m, " Example: echo '1002 2 ec200' > ctrl\n");
+
+ return 0;
+}
+
+
+static int fh_ctrl_proc_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, fh_ctrl_proc_read, inode->i_private);
+}
+
+static const struct file_operations ctrl_fops = {
+ .owner = THIS_MODULE,
+ .open = fh_ctrl_proc_open,
+ .read = seq_read,
+ .write = fh_ctrl_proc_write,
+ .release = single_release,
+};
+
+static int __sample_period_dds(struct clk_mt_fhctl *fh)
+{
+ int i, ssc_rate = 0;
+ struct clk_mt_fhctl_regs *fh_regs;
+ unsigned int mon_dds;
+ unsigned int dds;
+
+ fh_regs = fh->fh_regs;
+
+ mon_dds = readl(fh_regs->reg_mon) & fh->pll_data->dds_mask;
+ dds = readl(fh_regs->reg_dds) & fh->pll_data->dds_mask;
+
+ fh->pll_data->dds_max = dds;
+ fh->pll_data->dds_min = mon_dds;
+
+
+ /* Sample 200*10us */
+ for (i = 0 ; i < 200 ; i++) {
+ mon_dds = readl(fh_regs->reg_mon) & fh->pll_data->dds_mask;
+
+ if (mon_dds > fh->pll_data->dds_max)
+ fh->pll_data->dds_max = mon_dds;
+
+ if (mon_dds < fh->pll_data->dds_min)
+ fh->pll_data->dds_min = mon_dds;
+
+ udelay(10);
+ }
+
+ if ((fh->pll_data->dds_max == 0) ||
+ (fh->pll_data->dds_min == 0))
+ ssc_rate = 0;
+ else {
+ int diff = (fh->pll_data->dds_max - fh->pll_data->dds_min);
+
+ ssc_rate = (diff * 1000) / fh->pll_data->dds_max;
+ }
+
+ return ssc_rate;
+}
+
+static int mt_fh_dumpregs_read(struct seq_file *m, void *data)
+{
+ struct mtk_fhctl *fhctl = dev_get_drvdata(m->private);
+ int i, ssc_rate;
+ struct clk_mt_fhctl *fh;
+ struct clk_mt_fhctl_regs *fh_regs;
+
+ if (fhctl == NULL) {
+ seq_puts(m, "Cannot Get FHCTL driver data\n");
+ return 0;
+ }
+
+ seq_puts(m, "FHCTL dumpregs Read\n");
+
+ for (i = 0; i < fhctl->pll_num ; i++) {
+ fh = mtk_fh_get_fh_obj_tbl(fhctl, i);
+ if (fh == NULL) {
+ pr_info(" fh:NULL pll_id:%d", i);
+ seq_printf(m, "ERROR PLL_ID:%d clk_mt_fhctl is NULL\r\n", i);
+ return 0;
+ }
+
+ if (fh->pll_data->pll_type == FH_PLL_TYPE_NOT_SUPPORT) {
+ pr_debug(" Not support: %s", fh->pll_data->pll_name);
+ continue;
+ }
+
+ fh_regs = fh->fh_regs;
+ if (fh_regs == NULL) {
+ pr_info("%s Not support dumpregs!",
+ fh->pll_data->pll_name);
+ seq_printf(m, "PLL_%d: %s Not support dumpregs!\n",
+ i, fh->pll_data->pll_name);
+ continue;
+ }
+
+ pr_debug("fh:0x%p fh_regs:0x%p", fh, fh_regs);
+
+ if (i == 0) {
+ seq_printf(m, "\r\nFHCTL_HP_EN:\r\n0x%08x\r\n",
+ readl(fh_regs->reg_hp_en));
+ seq_printf(m, "\r\nFHCTL_CLK_CON:\r\n0x%08x\r\n",
+ readl(fh_regs->reg_clk_con));
+ seq_printf(m, "\r\nFHCTL_SLOPE0:\r\n0x%08x\r\n",
+ readl(fh_regs->reg_slope0));
+ seq_printf(m, "\r\nFHCTL_SLOPE1:\r\n0x%08x\r\n\n",
+ readl(fh_regs->reg_slope1));
+ }
+
+ ssc_rate = __sample_period_dds(fh);
+
+ seq_printf(m, "PLL_ID:%d (%s) type:%d \r\n",
+ i, fh->pll_data->pll_name, fh->pll_data->pll_type);
+
+ seq_puts(m, "CFG, UPDNLMT, DDS, DVFS, MON\r\n");
+ seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\r\n",
+ readl(fh_regs->reg_cfg), readl(fh_regs->reg_updnlmt),
+ readl(fh_regs->reg_dds), readl(fh_regs->reg_dvfs),
+ readl(fh_regs->reg_mon));
+ seq_puts(m, "CON0, CON_PCW\r\n");
+ seq_printf(m, "0x%08x 0x%08x\r\n",
+ readl(fh_regs->reg_con0), readl(fh_regs->reg_con_pcw));
+
+ seq_printf(m,
+ "DDS max:0x%08x min:0x%08x ssc(1/1000):%d\r\n\r\n",
+ fh->pll_data->dds_max,
+ fh->pll_data->dds_min,
+ ssc_rate);
+
+
+ pr_debug("pll_id:%d", i);
+ pr_debug("pll_type:%d", fh->pll_data->pll_type);
+ pr_debug("reg_hp_en:0x%08x", readl(fh_regs->reg_hp_en));
+ pr_debug("reg_clk_con:0x%08x", readl(fh_regs->reg_clk_con));
+ pr_debug("reg_rst_con:0x%08x", readl(fh_regs->reg_rst_con));
+ pr_debug("reg_slope0:0x%08x", readl(fh_regs->reg_slope0));
+ pr_debug("reg_slope1:0x%08x", readl(fh_regs->reg_slope1));
+
+ pr_debug("reg_cfg:0x%08x", readl(fh_regs->reg_cfg));
+ pr_debug("reg_updnlmt:0x%08x", readl(fh_regs->reg_updnlmt));
+ pr_debug("reg_dds:0x%08x", readl(fh_regs->reg_dds));
+ pr_debug("reg_dvfs:0x%08x", readl(fh_regs->reg_dvfs));
+ pr_debug("reg_mon:0x%08x", readl(fh_regs->reg_mon));
+ pr_debug("reg_con0:0x%08x", readl(fh_regs->reg_con0));
+ pr_debug("reg_con_pcw:0x%08x", readl(fh_regs->reg_con_pcw));
+
+ }
+ return 0;
+}
+
+void mt_fhctl_init_debugfs(struct mtk_fhctl *fhctl)
+{
+ struct dentry *root;
+ struct dentry *fh_dumpregs_dir;
+ struct dentry *fh_ctrl_dir;
+ struct device *dev = fhctl->dev;
+
+ root = debugfs_create_dir("fhctl", NULL);
+ if (IS_ERR(root)) {
+ dev_info(dev, "create debugfs fail");
+ return;
+ }
+ __set_fhctl(fhctl);
+ fhctl->debugfs_root = root;
+
+ /* /sys/kernel/debug/fhctl/dumpregs */
+ fh_dumpregs_dir = debugfs_create_devm_seqfile(dev,
+ "dumpregs", root, mt_fh_dumpregs_read);
+ if (IS_ERR(fh_dumpregs_dir)) {
+ dev_info(dev, "failed to create dumpregs debugfs");
+ return;
+ }
+
+ /* /sys/kernel/debug/fhctl/ctrl */
+ fh_ctrl_dir = debugfs_create_file("ctrl", 0664,
+ root, fhctl, &ctrl_fops);
+ if (IS_ERR(fh_ctrl_dir)) {
+ dev_info(dev, "failed to create ctrl debugfs");
+ return;
+ }
+
+ dev_dbg(dev, "Create debugfs success!");
+}
+
+
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-debug.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-debug.h
new file mode 100644
index 0000000..34b9f0c
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-debug.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Pierre Lee <pierre.lee@mediatek.com>
+ */
+
+
+#ifndef __DRV_CLK_FHCTL_DEBUG_H
+#define __DRV_CLK_FHCTL_DEBUG_H
+
+#if defined(CONFIG_DEBUG_FS)
+void mt_fhctl_init_debugfs(struct mtk_fhctl *fhctl);
+void mt_fhctl_exit_debugfs(struct mtk_fhctl *fhctl);
+void mt_fhctl_log_b4_hopping(struct clk_mt_fhctl *fhctl, unsigned int target_dds, unsigned int tx_id, struct pll_status *fh_log);
+void mt_fhctl_log_af_hopping(struct clk_mt_fhctl *fhctl, int ret_from_ipi, unsigned int tx_id, struct pll_status *fh_log, void (*ipi_get_data)(unsigned int), u64 time_ns);
+void mt_fh_dump_register(void);
+
+#else
+static inline void mt_fhctl_init_debugfs(struct mtk_fhctl *fhctl)
+{
+}
+static inline void mt_fhctl_exit_debugfs(struct mtk_fhctl *fhctl)
+{
+}
+static inline void mt_fhctl_log_b4_hopping(struct clk_mt_fhctl *fhctl, unsigned int target_dds, unsigned int tx_id, struct pll_status *fh_log)
+{
+}
+static inline void mt_fhctl_log_af_hopping(struct clk_mt_fhctl *fhctl, int ret_from_ipi, unsigned int ack_data, struct pll_status *fh_log, void (*ipi_get_data)(unsigned int), u64 time_ns)
+{
+}
+static inline void mt_fh_dump_register(void)
+{
+}
+
+#endif
+
+#endif /* __DRV_CLK_FHCTL_DEBUG_H */
+
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-mcupm.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-mcupm.c
new file mode 100644
index 0000000..e9cde40
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-mcupm.c
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Pierre Lee <pierre.lee@mediatek.com>
+ */
+
+#include "clk-fhctl.h"
+#include <mtk_tinysys_ipi.h>
+#include "../../misc/mediatek/mcupm/mt6880/mcupm_ipi_id.h"
+#include "clk-fhctl-debug.h"
+
+#define FHCTL_D_LEN 9
+#define MAX_SSC_RATE 8
+
+unsigned int ack_data = 0;
+static DEFINE_SPINLOCK(fhctl_lock);
+
+/* mcupm IPI CMD. Should sync with mt_freqhopping.h in tinysys driver. */
+enum FH_DEVCTL_CMD_ID {
+ FH_DCTL_CMD_SSC_ENABLE = 0x1004,
+ FH_DCTL_CMD_SSC_DISABLE = 0x1005,
+ FH_DCTL_CMD_GENERAL_DFS = 0x1006,
+ FH_DCTL_CMD_ARM_DFS = 0x1007,
+ FH_DCTL_CMD_SSC_TBL_CONFIG = 0x100A,
+ FH_DCTL_CMD_PLL_PAUSE = 0x100E,
+ FH_DCTL_CMD_MAX
+};
+
+struct freqhopping_ioctl {
+ unsigned int pll_id;
+ struct freqhopping_ssc {
+ unsigned int idx_pattern; /* idx_pattern: Deprecated Field */
+ unsigned int dt;
+ unsigned int df;
+ unsigned int upbnd;
+ unsigned int lowbnd;
+ unsigned int dds; /* dds: Deprecated Field */
+ } ssc_setting; /* used only when user-define */
+ int result;
+};
+
+struct fhctl_ipi_data {
+ unsigned int cmd;
+ union {
+ struct freqhopping_ioctl fh_ctl;
+ unsigned int args[8];
+ } u;
+};
+
+static int mt_fh_ipi_init(void)
+{
+ int ret = 0;
+ ack_data = 0;
+ ret = mtk_ipi_register(&mcupm_ipidev, CH_S_FHCTL, NULL,
+ NULL, (void *)&ack_data);
+ if (ret) {
+ pr_err("[MCUPM] ipi_register fail, ret %d\n", ret);
+ return -1;
+ }
+ return 0;
+}
+
+static int fhctl_to_mcupm_command(unsigned int cmd,
+ struct fhctl_ipi_data *ipi_data)
+{
+ int ret = 0;
+ pr_debug("send ipi command %x", cmd);
+
+ switch (cmd) {
+ case FH_DCTL_CMD_SSC_ENABLE:
+ case FH_DCTL_CMD_SSC_DISABLE:
+ case FH_DCTL_CMD_GENERAL_DFS:
+ case FH_DCTL_CMD_ARM_DFS:
+ case FH_DCTL_CMD_SSC_TBL_CONFIG:
+ case FH_DCTL_CMD_PLL_PAUSE:
+ ipi_data->cmd = cmd;
+
+ ret = mtk_ipi_send_compl(&mcupm_ipidev, CH_S_FHCTL,
+ IPI_SEND_POLLING, ipi_data, FHCTL_D_LEN, 10);
+ if (ret != 0)
+ pr_info("mcupm_ipi_send_sync error(%d) ret:%d - %d",
+ cmd, ret, ack_data);
+ else if (ack_data < 0)
+ pr_info("cmd(%d) return error(%d)", cmd, ack_data);
+ break;
+ default:
+ pr_info("[Error]Undefined IPI command");
+ break;
+ } /* switch */
+
+ pr_debug("send ipi command %x, response: ack_data: %d",
+ cmd, ack_data);
+
+ return ret;
+}
+
+static int clk_mt_fh_mcupm_pll_init(struct clk_mt_fhctl *fh)
+{
+ struct fhctl_ipi_data ipi_data;
+ int pll_id;
+
+ pll_id = fh->pll_data->pll_id;
+
+ /* Check default enable SSC */
+ if (fh->pll_data->pll_default_ssc_rate > 0) {
+ /* Init mcupm g_pll_ssc_setting_tbl table */
+ ipi_data.u.fh_ctl.pll_id = pll_id;
+ ipi_data.u.fh_ctl.ssc_setting.dt = 0;
+ ipi_data.u.fh_ctl.ssc_setting.df = 0;
+ ipi_data.u.fh_ctl.ssc_setting.upbnd = 0;
+ ipi_data.u.fh_ctl.ssc_setting.lowbnd =
+ fh->pll_data->pll_default_ssc_rate;
+ fhctl_to_mcupm_command(FH_DCTL_CMD_SSC_TBL_CONFIG, &ipi_data);
+
+ pr_debug("Default Enable SSC PLL_ID:%d SSC_RATE:0~-%d",
+ pll_id, fh->pll_data->pll_default_ssc_rate);
+
+ /* Default Enable SSC to 0~-N%; */
+ fh->hal_ops->pll_ssc_enable(fh,
+ fh->pll_data->pll_default_ssc_rate);
+ }
+
+ return 0;
+}
+
+static int __clk_mt_fh_mcupm_pll_pause(struct clk_mt_fhctl *fh, bool pause)
+{
+ struct fhctl_ipi_data ipi_data;
+ int pll_id;
+
+ pll_id = fh->pll_data->pll_id;
+
+ /* Only for support pause in CPU PLL. */
+ if (fh->pll_data->pll_type != FH_PLL_TYPE_CPU)
+ return -EPERM;
+
+ ipi_data.u.args[0] = pll_id;
+ ipi_data.u.args[1] = (pause) ? 1 : 0;
+ fhctl_to_mcupm_command(FH_DCTL_CMD_PLL_PAUSE, &ipi_data);
+
+ return 0;
+}
+
+static int clk_mt_fh_mcupm_pll_unpause(struct clk_mt_fhctl *fh)
+{
+ return __clk_mt_fh_mcupm_pll_pause(fh, false);
+}
+
+static int clk_mt_fh_mcupm_pll_pause(struct clk_mt_fhctl *fh)
+{
+
+ return __clk_mt_fh_mcupm_pll_pause(fh, true);
+}
+
+static int clk_mt_fh_mcupm_pll_ssc_disable(struct clk_mt_fhctl *fh)
+{
+ struct freqhopping_ioctl fh_ctl;
+ struct fhctl_ipi_data ipi_data;
+ int pll_id;
+
+ pll_id = fh->pll_data->pll_id;
+
+ fh_ctl.pll_id = pll_id;
+ fh_ctl.result = 0;
+
+ memset(&ipi_data, 0, sizeof(struct fhctl_ipi_data));
+ memcpy(&ipi_data.u.fh_ctl, &fh_ctl,
+ sizeof(struct freqhopping_ioctl));
+
+ fhctl_to_mcupm_command(FH_DCTL_CMD_SSC_DISABLE, &ipi_data);
+
+ return 0;
+}
+
+
+static int clk_mt_fh_mcupm_pll_ssc_enable(struct clk_mt_fhctl *fh, int ssc_rate)
+{
+ struct freqhopping_ioctl fh_ctl;
+ struct fhctl_ipi_data ipi_data;
+ int pll_id;
+
+ pll_id = fh->pll_data->pll_id;
+ fh_ctl.pll_id = pll_id;
+ fh_ctl.result = 0;
+
+ if (fh->pll_data->pll_type == FH_PLL_TYPE_NOT_SUPPORT) {
+ pr_info("%s not support SSC.", fh->pll_data->pll_name);
+ return -EPERM;
+ }
+
+ if (ssc_rate > MAX_SSC_RATE) {
+ pr_info("[Error] ssc_rate:%d over spec!!!", ssc_rate);
+ return -EINVAL;
+ }
+
+ fh_ctl.ssc_setting.dt = 0; /* default setting */
+ fh_ctl.ssc_setting.df = 9; /* default setting */
+ fh_ctl.ssc_setting.upbnd = 0; /* default setting */
+ fh_ctl.ssc_setting.lowbnd = ssc_rate;
+
+ memset(&ipi_data, 0, sizeof(struct fhctl_ipi_data));
+ memcpy(&ipi_data.u.fh_ctl, &fh_ctl,
+ sizeof(struct freqhopping_ioctl));
+
+ fhctl_to_mcupm_command(FH_DCTL_CMD_SSC_ENABLE, &ipi_data);
+
+ pr_info("PLL:%d ssc rate change [O]:%d => [N]:%d ",
+ pll_id, fh->pll_data->pll_default_ssc_rate, ssc_rate);
+
+ /* Update clock ssc rate variable. */
+
+ fh->pll_data->pll_default_ssc_rate = ssc_rate;
+
+ return 0;
+}
+
+static void ipi_get_data(unsigned int cmd)
+{
+ struct fhctl_ipi_data ipi_data;
+ int ret;
+ pr_info("[Hopping] debug cmd<%x>\n", cmd);
+ memset(&ipi_data, 0, sizeof(struct fhctl_ipi_data));
+ ipi_data.cmd = cmd;
+ /* 3 sec for debug */
+ ret = mtk_ipi_send_compl(&mcupm_ipidev, CH_S_FHCTL,
+ IPI_SEND_POLLING, &ipi_data,
+ FHCTL_D_LEN, 3000);
+ pr_info("ret<%d>, ack_data<%x>\n",
+ ret, ack_data);
+}
+
+static int clk_mt_fh_mcupm_pll_hopping(struct clk_mt_fhctl *fh,
+ unsigned int new_dds,
+ int postdiv)
+{
+ struct fhctl_ipi_data ipi_data;
+ struct pll_status fh_log;
+ static unsigned int fh_txid;
+ int ret_from_ipi;
+ int pll_id, cmd_id;
+ unsigned long flags;
+ u64 time_ns;
+
+ pll_id = fh->pll_data->pll_id;
+
+ /* CPU is forbidden hopping in AP side. (clk driver owner reqest) */
+ if ((fh->pll_data->pll_type == FH_PLL_TYPE_NOT_SUPPORT) ||
+ (fh->pll_data->pll_type == FH_PLL_TYPE_CPU)) {
+ pr_info("%s not support hopping in AP side.",
+ fh->pll_data->pll_name);
+ return 0;
+ }
+
+ spin_lock_irqsave(&fhctl_lock, flags);
+
+ cmd_id = FH_DCTL_CMD_GENERAL_DFS;
+
+ memset(&ipi_data, 0, sizeof(struct fhctl_ipi_data));
+
+ fh_txid = (fh_txid + 1) % FH_LOG_MAX_IPI_IDX;
+
+ ipi_data.u.args[0] = pll_id;
+ ipi_data.u.args[1] = new_dds;
+ ipi_data.u.args[2] = postdiv;
+ ipi_data.u.args[7] = fh_txid;
+
+ mt_fhctl_log_b4_hopping(fh, new_dds, fh_txid, &fh_log); //get history log by kernel api dump
+ time_ns = ktime_to_ns(ktime_get());
+ ret_from_ipi = fhctl_to_mcupm_command(cmd_id, &ipi_data);
+
+ mt_fhctl_log_af_hopping(fh, ret_from_ipi, ack_data, &fh_log, ipi_get_data,time_ns);//get moment+get history log by kernel api dump
+
+ spin_unlock_irqrestore(&fhctl_lock, flags);
+
+ return 0;
+}
+
+const struct fhctl_ipi_ops ipi_ops = {
+ .ipi_init = mt_fh_ipi_init,
+};
+
+const struct clk_mt_fhctl_hal_ops mt_fhctl_hal_ops = {
+ .pll_init = clk_mt_fh_mcupm_pll_init,
+ .pll_unpause = clk_mt_fh_mcupm_pll_unpause,
+ .pll_pause = clk_mt_fh_mcupm_pll_pause,
+ .pll_ssc_disable = clk_mt_fh_mcupm_pll_ssc_disable,
+ .pll_ssc_enable = clk_mt_fh_mcupm_pll_ssc_enable,
+ .pll_hopping = clk_mt_fh_mcupm_pll_hopping,
+};
+
+
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-sspm.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-sspm.c
new file mode 100644
index 0000000..ac3b5c7
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl-sspm.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Pierre Lee <pierre.lee@mediatek.com>
+ */
+
+#include "clk-fhctl.h"
+#include "sspm_ipi.h"
+
+#define FHCTL_D_LEN 9
+#define MAX_SSC_RATE 8
+
+
+/* SSPM IPI CMD. Should sync with mt_freqhopping.h in tinysys driver. */
+enum FH_DEVCTL_CMD_ID {
+ FH_DCTL_CMD_SSC_ENABLE = 0x1004,
+ FH_DCTL_CMD_SSC_DISABLE = 0x1005,
+ FH_DCTL_CMD_GENERAL_DFS = 0x1006,
+ FH_DCTL_CMD_ARM_DFS = 0x1007,
+ FH_DCTL_CMD_SSC_TBL_CONFIG = 0x100A,
+ FH_DCTL_CMD_PLL_PAUSE = 0x100E,
+ FH_DCTL_CMD_MAX
+};
+
+struct freqhopping_ioctl {
+ unsigned int pll_id;
+ struct freqhopping_ssc {
+ unsigned int idx_pattern; /* idx_pattern: Deprecated Field */
+ unsigned int dt;
+ unsigned int df;
+ unsigned int upbnd;
+ unsigned int lowbnd;
+ unsigned int dds; /* dds: Deprecated Field */
+ } ssc_setting; /* used only when user-define */
+ int result;
+};
+
+struct fhctl_ipi_data {
+ unsigned int cmd;
+ union {
+ struct freqhopping_ioctl fh_ctl;
+ unsigned int args[8];
+ } u;
+};
+
+
+static int fhctl_to_sspm_command(unsigned int cmd,
+ struct fhctl_ipi_data *ipi_data)
+{
+ int ret = 0;
+ unsigned int ack_data = 0;
+
+ pr_debug("send ipi command %x", cmd);
+
+ switch (cmd) {
+ case FH_DCTL_CMD_SSC_ENABLE:
+ case FH_DCTL_CMD_SSC_DISABLE:
+ case FH_DCTL_CMD_GENERAL_DFS:
+ case FH_DCTL_CMD_ARM_DFS:
+ case FH_DCTL_CMD_SSC_TBL_CONFIG:
+ case FH_DCTL_CMD_PLL_PAUSE:
+ ipi_data->cmd = cmd;
+ ret = sspm_ipi_send_sync(IPI_ID_FHCTL, IPI_OPT_POLLING,
+ ipi_data, FHCTL_D_LEN, &ack_data, 1);
+ if (ret != 0)
+ pr_info("sspm_ipi_send_sync error(%d) ret:%d - %d",
+ cmd, ret, ack_data);
+ else if (ack_data < 0)
+ pr_info("cmd(%d) return error(%d)", cmd, ack_data);
+ break;
+ default:
+ pr_info("[Error]Undefined IPI command");
+ break;
+ } /* switch */
+
+ pr_debug("send ipi command %x, response: ack_data: %d",
+ cmd, ack_data);
+
+ return ack_data;
+}
+
+static int clk_mt_fh_sspm_pll_init(struct clk_mt_fhctl *fh)
+{
+ struct fhctl_ipi_data ipi_data;
+ int pll_id;
+
+ pll_id = fh->pll_data->pll_id;
+
+ /* Check default enable SSC */
+ if (fh->pll_data->pll_default_ssc_rate > 0) {
+ /* Init SSPM g_pll_ssc_setting_tbl table */
+ ipi_data.u.fh_ctl.pll_id = pll_id;
+ ipi_data.u.fh_ctl.ssc_setting.dt = 0;
+ ipi_data.u.fh_ctl.ssc_setting.df = 0;
+ ipi_data.u.fh_ctl.ssc_setting.upbnd = 0;
+ ipi_data.u.fh_ctl.ssc_setting.lowbnd =
+ fh->pll_data->pll_default_ssc_rate;
+ fhctl_to_sspm_command(FH_DCTL_CMD_SSC_TBL_CONFIG, &ipi_data);
+
+ pr_debug("Default Enable SSC PLL_ID:%d SSC_RATE:0~-%d",
+ pll_id, fh->pll_data->pll_default_ssc_rate);
+
+ /* Default Enable SSC to 0~-N%; */
+ fh->hal_ops->pll_ssc_enable(fh,
+ fh->pll_data->pll_default_ssc_rate);
+ }
+
+ return 0;
+}
+
+static int __clk_mt_fh_sspm_pll_pause(struct clk_mt_fhctl *fh, bool pause)
+{
+ struct fhctl_ipi_data ipi_data;
+ int pll_id;
+
+ pll_id = fh->pll_data->pll_id;
+
+ /* Only for support pause in CPU PLL. */
+ if (fh->pll_data->pll_type != FH_PLL_TYPE_CPU)
+ return -EPERM;
+
+ ipi_data.u.args[0] = pll_id;
+ ipi_data.u.args[1] = (pause) ? 1 : 0;
+ fhctl_to_sspm_command(FH_DCTL_CMD_PLL_PAUSE, &ipi_data);
+
+ return 0;
+}
+
+static int clk_mt_fh_sspm_pll_unpause(struct clk_mt_fhctl *fh)
+{
+ return __clk_mt_fh_sspm_pll_pause(fh, false);
+}
+
+static int clk_mt_fh_sspm_pll_pause(struct clk_mt_fhctl *fh)
+{
+
+ return __clk_mt_fh_sspm_pll_pause(fh, true);
+}
+
+static int clk_mt_fh_sspm_pll_ssc_disable(struct clk_mt_fhctl *fh)
+{
+ struct freqhopping_ioctl fh_ctl;
+ struct fhctl_ipi_data ipi_data;
+ int pll_id;
+
+ pll_id = fh->pll_data->pll_id;
+
+ fh_ctl.pll_id = pll_id;
+
+ memset(&ipi_data, 0, sizeof(struct fhctl_ipi_data));
+ memcpy(&ipi_data.u.fh_ctl, &fh_ctl,
+ sizeof(struct freqhopping_ioctl));
+
+ fhctl_to_sspm_command(FH_DCTL_CMD_SSC_DISABLE, &ipi_data);
+
+ return 0;
+}
+
+
+static int clk_mt_fh_sspm_pll_ssc_enable(struct clk_mt_fhctl *fh, int ssc_rate)
+{
+ struct freqhopping_ioctl fh_ctl;
+ struct fhctl_ipi_data ipi_data;
+ int pll_id;
+
+ pll_id = fh->pll_data->pll_id;
+ fh_ctl.pll_id = pll_id;
+
+ if (fh->pll_data->pll_type == FH_PLL_TYPE_NOT_SUPPORT) {
+ pr_info("%s not support SSC.", fh->pll_data->pll_name);
+ return -EPERM;
+ }
+
+ if (ssc_rate > MAX_SSC_RATE) {
+ pr_info("[Error] ssc_rate:%d over spec!!!", ssc_rate);
+ return -EINVAL;
+ }
+
+ fh_ctl.ssc_setting.dt = 0; /* default setting */
+ fh_ctl.ssc_setting.df = 9; /* default setting */
+ fh_ctl.ssc_setting.upbnd = 0; /* default setting */
+ fh_ctl.ssc_setting.lowbnd = ssc_rate;
+
+ memset(&ipi_data, 0, sizeof(struct fhctl_ipi_data));
+ memcpy(&ipi_data.u.fh_ctl, &fh_ctl,
+ sizeof(struct freqhopping_ioctl));
+
+ fhctl_to_sspm_command(FH_DCTL_CMD_SSC_ENABLE, &ipi_data);
+
+ pr_info("PLL:%d ssc rate change [O]:%d => [N]:%d ",
+ pll_id, fh->pll_data->pll_default_ssc_rate, ssc_rate);
+
+ /* Update clock ssc rate variable. */
+
+ fh->pll_data->pll_default_ssc_rate = ssc_rate;
+
+ return 0;
+}
+
+static int clk_mt_fh_sspm_pll_hopping(struct clk_mt_fhctl *fh,
+ unsigned int new_dds,
+ int postdiv)
+{
+ struct fhctl_ipi_data ipi_data;
+ int pll_id, cmd_id;
+
+
+ pll_id = fh->pll_data->pll_id;
+
+ /* CPU is forbidden hopping in AP side. (clk driver owner reqest) */
+ if ((fh->pll_data->pll_type == FH_PLL_TYPE_NOT_SUPPORT) ||
+ (fh->pll_data->pll_type == FH_PLL_TYPE_CPU)) {
+ pr_info("%s not support hopping in AP side.",
+ fh->pll_data->pll_name);
+ return 0;
+ }
+
+ cmd_id = FH_DCTL_CMD_GENERAL_DFS;
+
+ memset(&ipi_data, 0, sizeof(struct fhctl_ipi_data));
+ ipi_data.u.args[0] = pll_id;
+ ipi_data.u.args[1] = new_dds;
+ ipi_data.u.args[2] = postdiv;
+
+ fhctl_to_sspm_command(cmd_id, &ipi_data);
+
+ return 0;
+}
+
+const struct clk_mt_fhctl_hal_ops mt_fhctl_hal_ops = {
+ .pll_init = clk_mt_fh_sspm_pll_init,
+ .pll_unpause = clk_mt_fh_sspm_pll_unpause,
+ .pll_pause = clk_mt_fh_sspm_pll_pause,
+ .pll_ssc_disable = clk_mt_fh_sspm_pll_ssc_disable,
+ .pll_ssc_enable = clk_mt_fh_sspm_pll_ssc_enable,
+ .pll_hopping = clk_mt_fh_sspm_pll_hopping,
+};
+
+
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl.c
new file mode 100644
index 0000000..d1bdfa3
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl.c
@@ -0,0 +1,628 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Pierre Lee <pierre.lee@mediatek.com>
+ */
+
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include "clk-fhctl.h"
+#include "clk-fhctl-debug.h"
+#include "clk-mtk.h"
+
+
+/************************************************
+ ********** register base addr **********
+ ************************************************/
+#define REG_ADDR(base, x) (void __iomem *)((unsigned long)base + (x))
+
+/************************************************
+ ********** Variable **********
+ ************************************************/
+
+/* spinlock for fhctl */
+static DEFINE_SPINLOCK(fhctl_lock);
+static LIST_HEAD(clk_mt_fhctl_list);
+
+static struct mtk_fhctl *g_p_fhctl;
+
+/*****************************************************************
+ * Global variable operation
+ ****************************************************************/
+static void __set_fhctl(struct mtk_fhctl *pfhctl)
+{
+ g_p_fhctl = pfhctl;
+}
+
+static struct mtk_fhctl *__get_fhctl(void)
+{
+ return g_p_fhctl;
+}
+
+
+/*****************************************************************
+ * OF Info init
+ ****************************************************************/
+static int mtk_fhctl_parse_dt(struct mtk_fhctl *fhctl)
+{
+
+ unsigned int pll_num;
+ struct device *dev;
+ struct device_node *child;
+ struct device_node *node;
+
+ pll_num = fhctl->pll_num;
+ dev = fhctl->dev;
+ node = dev->of_node;
+
+ for_each_child_of_node(node, child) {
+ struct clk_mt_fhctl_pll_data *pll_data;
+ unsigned int id, pll_id, ssc;
+ int err, tbl_size;
+ bool ret;
+
+ /* search for fhctl id */
+ err = of_property_read_u32(child, "mediatek,fh-id", &id);
+ if (err) {
+ dev_info(dev, "miss fh-id property: %s", child->name);
+ return err;
+ }
+
+ if (id >= pll_num) {
+ dev_info(dev, "invalid %s fh-id:%d", child->name, id);
+ return -EINVAL;
+ }
+
+ pll_data = fhctl->fh_tbl[id]->pll_data;
+
+ /* Search for pll type */
+ pll_data->pll_type = FH_PLL_TYPE_FORCE;
+
+ /* Search for freqhopping table */
+ tbl_size = of_property_count_u32_elems(child,
+ "mediatek,fh-tbl");
+ if (tbl_size > 0) {
+ pll_data->hp_tbl_size = tbl_size;
+ pll_data->hp_tbl = devm_kzalloc(dev,
+ sizeof(u32)*tbl_size,
+ GFP_KERNEL);
+
+ if (!pll_data->hp_tbl)
+ return -ENOMEM;
+
+ err = of_property_read_u32_array(child,
+ "mediatek,fh-tbl",
+ pll_data->hp_tbl,
+ tbl_size);
+ if (err) {
+ dev_info(dev, "invalid fh-tbl property of %s",
+ child->name);
+ return err;
+ }
+
+ /* Parse successfully. Set pll type */
+ pll_data->pll_type = FH_PLL_TYPE_GENERAL;
+ }
+
+ /* Search for cpu pll type property */
+ ret = of_property_read_bool(child, "mediatek,fh-cpu-pll");
+ if (ret)
+ pll_data->pll_type = FH_PLL_TYPE_CPU;
+
+ /* Search for fh-pll-id */
+ err = of_property_read_u32(child, "mediatek,fh-pll-id",
+ &pll_id);
+ if (!err)
+ fhctl->idmap[id] = pll_id;
+
+ /* Search for default ssc rate */
+ err = of_property_read_u32(child, "mediatek,fh-ssc-rate",
+ &ssc);
+ if (!err)
+ pll_data->pll_default_ssc_rate = ssc;
+ }
+
+ return 0;
+}
+
+
+static int __add_fh_obj_tbl(struct mtk_fhctl *pfhctl, int posi,
+ struct clk_mt_fhctl *pfh)
+{
+ if (pfhctl == NULL) {
+ pr_info("Error: null pointer pfhctl");
+ return -EFAULT;
+ }
+
+ if (posi >= pfhctl->pll_num)
+ return -EINVAL;
+
+ pfhctl->fh_tbl[posi] = pfh;
+ return 0;
+}
+
+struct clk_mt_fhctl *mtk_fh_get_fh_obj_tbl(struct mtk_fhctl *pfhctl, int posi)
+{
+ int size;
+ struct clk_mt_fhctl *pfh;
+
+ if (pfhctl == NULL) {
+ pr_info("Error: null pointer pfhctl");
+ return ERR_PTR(-EFAULT);
+ }
+
+ size = pfhctl->pll_num;
+
+ if (posi >= size) {
+ dev_info(pfhctl->dev, "Error: size:%d posi:%d", size, posi);
+ return ERR_PTR(-EINVAL);
+ }
+
+ pfh = pfhctl->fh_tbl[posi];
+
+ dev_dbg(pfhctl->dev, "get fh:0x%p pll_id:%d", pfh, posi);
+
+ return pfh;
+}
+EXPORT_SYMBOL(mtk_fh_get_fh_obj_tbl);
+
+/*********************************************************
+ * For clock driver control
+ ********************************************************/
+bool _mtk_fh_set_rate(int pll_id, unsigned long dds, int postdiv)
+{
+ struct mtk_fhctl *fhctl;
+ struct clk_mt_fhctl *fh;
+ int fhctl_pll_id;
+
+ int i, tbl_size, ret;
+
+ pr_debug("check pll_id:0x%x dds:0x%lx", pll_id, dds);
+
+ fhctl = __get_fhctl();
+ if (fhctl == NULL) {
+ pr_info("ERROR: fhctl is not initialized");
+ return false;
+ }
+
+ /* Lookup table */
+ if (unlikely(pll_id < 0))
+ return false;
+
+ fhctl_pll_id = -1;
+ for (i = 0; i < fhctl->pll_num; i++)
+ if (fhctl->idmap[i] == pll_id) {
+ fhctl_pll_id = i;
+ break;
+ }
+
+ if (fhctl_pll_id == -1) {
+ pr_debug("pll not supportted by fhctl");
+ return false;
+ }
+
+ pr_debug("found fhctl_pll_id:%d", fhctl_pll_id);
+
+ fh = mtk_fh_get_fh_obj_tbl(fhctl, fhctl_pll_id);
+
+ if (IS_ERR_OR_NULL(fh))
+ return false;
+
+ if (fh->pll_data->pll_type == FH_PLL_TYPE_NOT_SUPPORT) {
+ pr_info("ERROR: pll not support");
+ return false;
+ }
+
+ if (fh->pll_data->pll_type == FH_PLL_TYPE_CPU) {
+ pr_info("ERROR: CPU hopping not support in AP side");
+ return false;
+ }
+
+ if (fh->pll_data->pll_type == FH_PLL_TYPE_FORCE) {
+ /* Force hopping by FHCTL. */
+ ret = fh->hal_ops->pll_hopping(fh, dds, postdiv);
+ return (ret == 0);
+ }
+
+ /* Look up hopping support table */
+ if (fh->pll_data->hp_tbl == NULL) {
+ pr_info("ERROR: fh->pll_data->hp_tbl NULL!");
+ return false;
+ }
+
+ tbl_size = fh->pll_data->hp_tbl_size;
+ for (i = 0; i < tbl_size; i++) {
+ if (fh->pll_data->hp_tbl[i] == dds) {
+ pr_debug("%s dds:0x%lx by fhctl hopping",
+ fh->pll_data->pll_name, dds);
+ ret = fh->hal_ops->pll_hopping(fh, dds, postdiv);
+ return (ret == 0);
+ }
+ }
+
+ return false;
+}
+
+/****************************************************
+ * CLK FHCTL reg init
+ ***************************************************/
+
+static struct clk_mt_fhctl_regs *__mt_fhctl_fh_regs_init(
+ struct mtk_fhctl *fhctl, unsigned int pll_id)
+{
+ struct clk_mt_fhctl_regs *fh_regs;
+ void *fhctl_base = fhctl->fhctl_base;
+ void *apmixed_base = fhctl->apmixed_base;
+ unsigned int reg_cfg_offs = fhctl->dev_comp->pll_regs[pll_id];
+ unsigned int reg_con0_offs = fhctl->dev_comp->pll_con0_regs[pll_id];
+ unsigned int reg_pcw_offs = fhctl->dev_comp->pll_apmix_pcw_offs;
+
+ fh_regs = devm_kmalloc(fhctl->dev, sizeof(struct clk_mt_fhctl_regs),
+ GFP_KERNEL);
+ if (!fh_regs)
+ return ERR_PTR(-ENOMEM);
+
+ /* fhctl common regs */
+ fh_regs->reg_unitslope_en = REG_ADDR(fhctl_base,
+ fhctl->dev_comp->common_regs[OFFSET_UNITSLOPE_EN]);
+ fh_regs->reg_hp_en = REG_ADDR(fhctl_base,
+ fhctl->dev_comp->common_regs[OFFSET_HP_EN]);
+ fh_regs->reg_clk_con = REG_ADDR(fhctl_base,
+ fhctl->dev_comp->common_regs[OFFSET_CLK_CON]);
+ fh_regs->reg_rst_con = REG_ADDR(fhctl_base,
+ fhctl->dev_comp->common_regs[OFFSET_RST_CON]);
+ fh_regs->reg_slope0 = REG_ADDR(fhctl_base,
+ fhctl->dev_comp->common_regs[OFFSET_SLOPE0]);
+ fh_regs->reg_slope1 = REG_ADDR(fhctl_base,
+ fhctl->dev_comp->common_regs[OFFSET_SLOPE1]);
+
+ /* fhctl PLL specific regs */
+ fh_regs->reg_cfg = REG_ADDR(fhctl_base, reg_cfg_offs);
+ fh_regs->reg_updnlmt = REG_ADDR(fhctl_base, reg_cfg_offs + 0x04);
+ fh_regs->reg_dds = REG_ADDR(fhctl_base, reg_cfg_offs + 0x08);
+ fh_regs->reg_dvfs = REG_ADDR(fhctl_base, reg_cfg_offs + 0xC);
+ fh_regs->reg_mon = REG_ADDR(fhctl_base, reg_cfg_offs + 0x10);
+
+ fh_regs->reg_con0 = REG_ADDR(apmixed_base, reg_con0_offs);
+ fh_regs->reg_con_pcw = REG_ADDR(apmixed_base, reg_con0_offs + reg_pcw_offs);
+
+ return fh_regs;
+}
+
+
+static struct clk_mt_fhctl *clk_register_fhctl_pll(
+ struct device *dev,
+ const struct clk_mt_fhctl_hal_ops *hal_ops,
+ struct clk_mt_fhctl_pll_data *pll_data,
+ struct clk_mt_fhctl_regs *fh_regs)
+{
+ struct clk_mt_fhctl *fh;
+
+ fh = devm_kmalloc(dev, sizeof(struct clk_mt_fhctl), GFP_KERNEL);
+ if (!fh)
+ return ERR_PTR(-ENOMEM);
+
+ fh->pll_data = pll_data;
+ fh->fh_regs = fh_regs;
+ fh->hal_ops = hal_ops;
+ fh->lock = &fhctl_lock;
+
+ return fh;
+}
+
+
+static int mt_fh_plt_drv_probe(struct platform_device *pdev)
+{
+ int i, err, pll_num;
+ int dds_mask_size;
+ struct mtk_fhctl *fhctl;
+ struct resource *res;
+ struct device_node *apmixed_node;
+
+ dev_info(&pdev->dev, "FHCTL driver probe start");
+
+ fhctl = devm_kmalloc(&pdev->dev, sizeof(*fhctl), GFP_KERNEL);
+ if (!fhctl)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ fhctl->fhctl_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(fhctl->fhctl_base))
+ return PTR_ERR(fhctl->fhctl_base);
+
+ /* Init APMIXED base address */
+ apmixed_node = of_parse_phandle(pdev->dev.of_node,
+ "mediatek,apmixed", 0);
+ if (!apmixed_node) {
+ dev_info(&pdev->dev, "fhctl: missing mediatek,apmixed node");
+ return -ENODEV;
+ }
+ fhctl->apmixed_base = of_iomap(apmixed_node, 0);
+
+
+ fhctl->dev = &pdev->dev;
+ fhctl->dev_comp = of_device_get_match_data(&pdev->dev);
+ fhctl->pll_num = fhctl->dev_comp->pll_num;
+ dds_mask_size = fhctl->dev_comp->pll_dds_reg_field_size;
+
+ pll_num = fhctl->pll_num;
+
+ fhctl->idmap = devm_kmalloc(&pdev->dev,
+ sizeof(int)*pll_num, GFP_KERNEL);
+ if (!fhctl->idmap)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, fhctl);
+
+ fhctl->fh_tbl = devm_kmalloc(&pdev->dev,
+ sizeof(struct clk_mt_fhctl *) * pll_num, GFP_KERNEL);
+ if (!fhctl->fh_tbl)
+ return -ENOMEM;
+
+ /* register all fhctl pll */
+ for (i = 0; i < pll_num; i++) {
+ struct clk_mt_fhctl *fh;
+ struct clk_mt_fhctl_pll_data *pll_data;
+ struct clk_mt_fhctl_regs *fh_regs;
+
+ pll_data = devm_kmalloc(&pdev->dev,
+ sizeof(struct clk_mt_fhctl_pll_data), GFP_KERNEL);
+ if (!pll_data)
+ return -ENOMEM;
+
+ fhctl->idmap[i] = -1;
+
+ /* Set pll data */
+ pll_data->pll_id = i;
+ pll_data->pll_name = fhctl->dev_comp->pll_names[i];
+ pll_data->pll_type = FH_PLL_TYPE_NOT_SUPPORT;
+ pll_data->dds_mask = GENMASK(dds_mask_size-1, 0);
+ pll_data->pll_default_ssc_rate = 0;
+ pll_data->slope0_value =
+ fhctl->dev_comp->pll_slope0_reg_setting;
+ pll_data->slope1_value =
+ fhctl->dev_comp->pll_slope1_reg_setting;
+ pll_data->hp_tbl = NULL;
+ pll_data->hp_tbl_size = 0;
+
+ /* Init fhctl PLL regs */
+ fh_regs = __mt_fhctl_fh_regs_init(fhctl, i);
+ if (IS_ERR_OR_NULL(fh_regs)) {
+ dev_info(&pdev->dev, "ERROR: init fh_regs fail.");
+ return PTR_ERR(fh_regs);
+ }
+
+ fh = clk_register_fhctl_pll(&pdev->dev, &mt_fhctl_hal_ops,
+ pll_data, fh_regs);
+ if (IS_ERR(fh)) {
+ dev_info(&pdev->dev,
+ "register clk fhctl failed: %s",
+ pll_data->pll_name);
+ return PTR_ERR(fh);
+ }
+
+ list_add(&fh->node, &clk_mt_fhctl_list);
+
+ /* Add fh object to table */
+ err = __add_fh_obj_tbl(fhctl, i, fh);
+ if (err)
+ dev_info(&pdev->dev,
+ "add fh object %d to table failed", i);
+
+ }
+
+ fhctl->ipi_ops_p = &ipi_ops;
+ err = fhctl->ipi_ops_p->ipi_init();
+ if (err){
+ dev_info(&pdev->dev, "ERROR fhctl->mt_fh_hal_init() fail");
+ return err;
+ }
+
+ /* Read fhctl setting by device tree */
+ err = mtk_fhctl_parse_dt(fhctl);
+ if (err) {
+ dev_info(&pdev->dev, "ERROR mtk_fhctl_parse_dt fail");
+ return err;
+ }
+
+ for (i = 0; i < pll_num ; i++)
+ fhctl->fh_tbl[i]->hal_ops->pll_init(fhctl->fh_tbl[i]);
+
+ __set_fhctl(fhctl);
+
+ mt_fhctl_init_debugfs(fhctl);
+
+ mtk_fh_set_rate = _mtk_fh_set_rate;
+
+ dev_info(&pdev->dev, "FHCTL Init Done");
+
+ for (i = 0; i < fhctl->pll_num; i++)
+ dev_info(&pdev->dev, "pllid_map[%d]=%d", i, fhctl->idmap[i]);
+
+ fhctl->reg_tr = fhctl->fhctl_base + (uintptr_t)FH_REG_TR;
+ /* show setting value */
+ dev_dbg(&pdev->dev, "pll_num:%d", fhctl->pll_num);
+ dev_dbg(&pdev->dev, "apmixed_base:0x%lx",
+ (unsigned long)fhctl->apmixed_base);
+ dev_dbg(&pdev->dev, "fhctl_base:0x%lx",
+ (unsigned long)fhctl->fhctl_base);
+ dev_dbg(&pdev->dev, "reg_tr:0x%lx",
+ (unsigned long)fhctl->reg_tr);
+ dev_dbg(&pdev->dev, "pll_dds_reg_field_size:%d",
+ fhctl->dev_comp->pll_dds_reg_field_size);
+ dev_dbg(&pdev->dev, "pll_reg_offs:0x%x",
+ fhctl->dev_comp->pll_regs[0]);
+ dev_dbg(&pdev->dev, "pll-type[0]:%d",
+ fhctl->fh_tbl[0]->pll_data->pll_type);
+ dev_dbg(&pdev->dev, "pll_default_enable_ssc[0]:%d",
+ fhctl->fh_tbl[0]->pll_data->pll_default_ssc_rate);
+ dev_dbg(&pdev->dev, "pll_con0_regs[0]:0x%x",
+ fhctl->dev_comp->pll_con0_regs[0]);
+ dev_dbg(&pdev->dev, "pll_slope0_reg_settings[0]:0x%x",
+ fhctl->dev_comp->pll_slope0_reg_setting);
+ dev_dbg(&pdev->dev, "pll_slope1_reg_settings[0]:0x%x",
+ fhctl->dev_comp->pll_slope1_reg_setting);
+ dev_dbg(&pdev->dev, "pll_names[0]:%s",
+ fhctl->fh_tbl[0]->pll_data->pll_name);
+
+ return 0;
+}
+
+static int mt_fh_plt_drv_remove(struct platform_device *pdev)
+{
+ struct mtk_fhctl *fhctl = platform_get_drvdata(pdev);
+
+ mtk_fh_set_rate = NULL;
+ mt_fhctl_exit_debugfs(fhctl);
+ return 0;
+}
+
+static void mt_fh_plt_drv_shutdown(struct platform_device *pdev)
+{
+ struct clk_mt_fhctl *fh;
+
+ dev_dbg(&pdev->dev, "%s!", __func__);
+
+ list_for_each_entry(fh, &clk_mt_fhctl_list, node) {
+ if (fh->pll_data->pll_default_ssc_rate > 0) {
+ dev_info(&pdev->dev, "Shutdown to Disable SSC => PLL:%s ",
+ fh->pll_data->pll_name);
+ fh->hal_ops->pll_ssc_disable(fh);
+ }
+ }
+ dev_dbg(&pdev->dev, "%s Done!", __func__);
+}
+
+
+static const u16 mt_fhctl_regs_v1[] = {
+ [OFFSET_HP_EN] = 0x0,
+ [OFFSET_CLK_CON] = 0x4,
+ [OFFSET_RST_CON] = 0x8,
+ [OFFSET_SLOPE0] = 0xc,
+ [OFFSET_SLOPE1] = 0x10,
+ [OFFSET_FHCTL_DSSC_CFG] = 0x14,
+};
+
+static const u16 mt_fhctl_regs_v2[] = {
+ [OFFSET_UNITSLOPE_EN] = 0x0,
+ [OFFSET_HP_EN] = 0x4,
+ [OFFSET_CLK_CON] = 0x8,
+ [OFFSET_RST_CON] = 0xc,
+ [OFFSET_SLOPE0] = 0x10,
+ [OFFSET_SLOPE1] = 0x14,
+ [OFFSET_FHCTL_DSSC_CFG] = 0x18,
+};
+
+static const u16 mt_fhctl_regs_v3[] = {
+ [OFFSET_UNITSLOPE_EN] = 0x4,
+ [OFFSET_HP_EN] = 0x0,
+ [OFFSET_CLK_CON] = 0x8,
+ [OFFSET_RST_CON] = 0xc,
+ [OFFSET_SLOPE0] = 0x10,
+ [OFFSET_SLOPE1] = 0x14,
+ [OFFSET_FHCTL_DSSC_CFG] = 0x18,
+};
+
+
+
+static const char * const mt6779_pll_names[] = {
+ "armpll_ll", "armpll_bl", "armpll_bb", "ccipll",
+ "mfgpll", "mpll", "mempll", "mainpll",
+ "msdcpll", "mmpll", "adsppll", "tvdpll"};
+
+
+static const u16 mt6779_pll_regs[] = {
+ 0x0038, 0x004C, 0xdead, 0x0074,
+ 0x088, 0x009C, 0x00B0, 0x00C4,
+ 0x00D8, 0x00EC, 0x0100, 0x0114};
+
+static const u16 mt6779_pll_con0_regs[] = {
+ 0x200, 0x210, 0x0220, 0x02A0,
+ 0x0250, 0x0290, 0xdead, 0x0230,
+ 0x0260, 0x0280, 0x02b0, 0x0270};
+
+
+static const struct mtk_fhctl_compatible mt6779_fhctl_compat = {
+ .common_regs = mt_fhctl_regs_v1,
+ .pll_num = 12,
+ .pll_names = mt6779_pll_names,
+ .pll_dds_reg_field_size = 22,
+ .pll_apmix_pcw_offs = CON1_OFFS,
+ .pll_regs = mt6779_pll_regs,
+ .pll_con0_regs = mt6779_pll_con0_regs,
+ .pll_slope0_reg_setting = 0x6003c97,
+ .pll_slope1_reg_setting = 0x6003c97,
+};
+
+
+static const char * const mt6880_pll_names[] = {
+ "armpll_ll", "mainpll", "mpll", "ccipll",
+ "msdcpll", "mfgpll", "mmpll", "net1pll",
+ "net2pll", "wedmcupll", "mempll"};
+
+
+static const u16 mt6880_pll_regs[] = {
+ 0x003C, 0x0050, 0x0064, 0x0078,
+ 0x008C, 0x00A0, 0x00B4, 0x00C8,
+ 0x00DC, 0x00F0, 0x0104};
+
+static const u16 mt6880_pll_con0_regs[] = {
+ 0x0204, 0x0404, 0x0604, 0x0218,
+ 0x022C, 0x0618, 0x042C, 0x0804,
+ 0x0818, 0x082C, 0xdead};
+
+
+static const struct mtk_fhctl_compatible mt6880_fhctl_compat = {
+ .common_regs = mt_fhctl_regs_v3,
+ .pll_num = 11,
+ .pll_names = mt6880_pll_names,
+ .pll_dds_reg_field_size = 22,
+ .pll_apmix_pcw_offs = CON2_OFFS,
+ .pll_regs = mt6880_pll_regs,
+ .pll_con0_regs = mt6880_pll_con0_regs,
+ .pll_slope0_reg_setting = 0x6003c97,
+ .pll_slope1_reg_setting = 0x6003c97,
+};
+
+
+static const struct of_device_id mtk_fhctl_of_match[] = {
+ { .compatible = "mediatek,mt6779-fhctl", .data = &mt6779_fhctl_compat },
+ { .compatible = "mediatek,mt6880-fhctl", .data = &mt6880_fhctl_compat },
+ {}
+};
+MODULE_DEVICE_TABLE(of, mtk_fhctl_of_match);
+
+
+static struct platform_driver fhctl_driver = {
+ .probe = mt_fh_plt_drv_probe,
+ .remove = mt_fh_plt_drv_remove,
+ .shutdown = mt_fh_plt_drv_shutdown,
+ .driver = {
+ .name = "mt-freqhopping",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(mtk_fhctl_of_match),
+ },
+};
+
+module_platform_driver(fhctl_driver);
+
+
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("MediaTek FHCTL Driver");
+MODULE_AUTHOR("Pierre Lee <pierre.lee@mediatek.com>");
+
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl.h
new file mode 100644
index 0000000..285dff8
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fhctl.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Pierre Lee <pierre.lee@mediatek.com>
+ */
+
+
+#ifndef __DRV_CLK_FHCTL_H
+#define __DRV_CLK_FHCTL_H
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/bitops.h>
+
+
+/************************************************
+ ********** register field **********
+ ************************************************/
+// REG_CFG mask
+#define MASK_FRDDSX_DYS GENMASK(23, 20)
+#define MASK_FRDDSX_DTS GENMASK(19, 16)
+#define FH_FHCTLX_CFG_PAUSE BIT(4)
+#define FH_SFSTRX_EN BIT(2)
+#define FH_FRDDSX_EN BIT(1)
+#define FH_FHCTLX_EN BIT(0)
+
+//REG_DDS mask
+#define FH_FHCTLX_PLL_TGL_ORG BIT(31)
+
+//FHCTLX_DVFS mask
+#define FH_FHCTLX_PLL_DVFS_TRI BIT(31)
+
+//XXPLL_CON1 mask (APMIXED)
+#define FH_XXPLL_CON_PCWCHG BIT(31)
+
+// Default DT/DF valude
+#define REG_CFG_DT_VAL 0x0
+#define REG_CFG_DF_VAL 0x9
+
+#define REG_HP_EN_APMIXEDSYS_CTR 0
+#define REG_HP_EN_FHCTL_CTR 1
+
+#define fh_set_field(reg, field, val) \
+do { \
+ unsigned int tv = readl(reg); \
+ tv &= ~(field); \
+ tv |= ((val) << (ffs(field) - 1)); \
+ writel(tv, reg); \
+} while (0)
+
+#define fh_get_field(reg, field, val) \
+do { \
+ unsigned int tv = readl(reg); \
+ val = ((tv & (field)) >> (ffs(field) - 1)); \
+} while (0)
+
+#define FH_REG_TR (void __iomem *)(0x104 +0x4)
+
+struct clk_mt_fhctl_regs {
+ /* Common reg */
+ void __iomem *reg_unitslope_en;
+ void __iomem *reg_hp_en;
+ void __iomem *reg_clk_con;
+ void __iomem *reg_rst_con;
+ void __iomem *reg_slope0;
+ void __iomem *reg_slope1;
+
+ /* For PLL specific */
+ void __iomem *reg_cfg;
+ void __iomem *reg_updnlmt;
+ void __iomem *reg_dds;
+ void __iomem *reg_dvfs;
+ void __iomem *reg_mon;
+ void __iomem *reg_con0;
+ void __iomem *reg_con_pcw;
+};
+
+struct clk_mt_fhctl_pll_data {
+ const char *pll_name;
+ int pll_id;
+ int pll_type;
+ int pll_default_ssc_rate;
+ unsigned int slope0_value;
+ unsigned int slope1_value;
+ unsigned int dds_mask;
+ unsigned int *hp_tbl;
+ unsigned int hp_tbl_size;
+ unsigned int dds_max; // for UT dds max value.
+ unsigned int dds_min; // for UT dds min value.
+};
+
+struct clk_mt_fhctl {
+ struct clk_mt_fhctl_pll_data *pll_data;
+ struct clk_mt_fhctl_regs *fh_regs;
+ const struct clk_mt_fhctl_hal_ops *hal_ops;
+ spinlock_t *lock;
+ struct list_head node;
+};
+
+struct clk_mt_fhctl_hal_ops {
+ int (*pll_init)(struct clk_mt_fhctl *fh);
+ int (*pll_unpause)(struct clk_mt_fhctl *fh);
+ int (*pll_pause)(struct clk_mt_fhctl *fh);
+ int (*pll_ssc_disable)(struct clk_mt_fhctl *fh);
+ int (*pll_ssc_enable)(struct clk_mt_fhctl *fh, int rate);
+ int (*pll_hopping)(struct clk_mt_fhctl *fh,
+ unsigned int new_dds, int postdiv);
+};
+
+struct fhctl_ipi_ops{
+ int (*ipi_init)(void);
+};
+
+struct mtk_fhctl {
+ struct device *dev;
+
+ /* set in fhctl probe */
+ void __iomem *fhctl_base;
+ void __iomem *apmixed_base;
+ void __iomem *reg_tr;
+ unsigned int pll_num;
+ int *idmap;
+
+ struct clk_mt_fhctl **fh_tbl;
+ const struct fhctl_ipi_ops *ipi_ops_p;
+ const struct mtk_fhctl_compatible *dev_comp;
+#if defined(CONFIG_DEBUG_FS)
+ struct dentry *debugfs_root;
+#endif
+};
+
+struct mtk_fhctl_compatible {
+ const u16 *common_regs;
+ const u16 *pll_regs;
+ const u16 *pll_con0_regs;
+ const char * const *pll_names;
+ unsigned int pll_apmix_pcw_offs;
+ unsigned int pll_num;
+ unsigned int pll_dds_reg_field_size;
+ unsigned int pll_slope0_reg_setting;
+ unsigned int pll_slope1_reg_setting;
+};
+
+enum FHCTL_PLL_PCW_OFFSET {
+ CON0_OFFS = 0x00,
+ CON1_OFFS = 0x04,
+ CON2_OFFS = 0x08,
+};
+
+enum FHCTL_COMMON_REGS_OFFSET {
+ OFFSET_UNITSLOPE_EN,
+ OFFSET_HP_EN,
+ OFFSET_CLK_CON,
+ OFFSET_RST_CON,
+ OFFSET_SLOPE0,
+ OFFSET_SLOPE1,
+ OFFSET_FHCTL_DSSC_CFG,
+};
+
+enum FHCTL_PLL_REGS_OFFSET {
+ OFFSET_CFG,
+ OFFSET_UPDNLMT,
+ OFFSET_DDS,
+ OFFSET_DVFS,
+ OFFSET_MON,
+ OFFSET_CON0,
+ OFFSET_CON1,
+};
+
+enum FHCTL_PLL_TYPE {
+ FH_PLL_TYPE_NOT_SUPPORT,
+ FH_PLL_TYPE_GENERAL,
+ FH_PLL_TYPE_CPU,
+ FH_PLL_TYPE_FORCE,
+};
+
+
+struct pll_status {
+ unsigned int pll_id;
+ unsigned int tx_id;
+ unsigned int target_dds;
+ unsigned int before_dds;
+ unsigned int after_dds;
+};
+
+
+#define FH_LOG_MAX_IPI_IDX 128 //max size
+
+struct clk_mt_fhctl *mtk_fh_get_fh_obj_tbl(struct mtk_fhctl *fhctl, int posi);
+extern const struct clk_mt_fhctl_hal_ops mt_fhctl_hal_ops;
+extern const struct fhctl_ipi_ops ipi_ops;
+extern struct mtk_ipi_device mcupm_ipidev;
+
+
+
+#endif /* __DRV_CLK_FHCTL_H */
+
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fixup-div.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fixup-div.c
new file mode 100644
index 0000000..936d2fa
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fixup-div.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include "clk-mtk.h"
+#include "clk-fixup-div.h"
+
+#define div_mask(d) ((1 << (d)) - 1)
+
+static unsigned long clk_fixup_div_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
+ unsigned int val;
+
+ val = readl(fixup_div->reg_fixup) >> fixup_div->divider.shift;
+ val &= div_mask(fixup_div->divider.width);
+ pr_debug("%s: val = %x\n", __func__, val);
+
+ return divider_recalc_rate(hw, parent_rate, val,
+ fixup_div->clk_div_table,
+ fixup_div->divider.flags,
+ fixup_div->divider.width);
+}
+
+static long clk_fixup_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
+
+ pr_debug("%s: rate = %lu, prate = %lu\n", __func__, rate, *prate);
+
+ return divider_round_rate(hw, rate, prate, fixup_div->clk_div_table,
+ fixup_div->divider.width,
+ fixup_div->divider.flags);
+}
+
+static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
+ struct clk_divider *div = to_clk_divider(hw);
+ unsigned long flags = 0;
+ int val, value;
+
+ value = divider_get_val(rate, parent_rate, div->table,
+ div->width, div->flags);
+ if (value < 0)
+ return value;
+
+ spin_lock_irqsave(div->lock, flags);
+
+ val = readl(fixup_div->reg_fixup);
+ val &= ~(div_mask(div->width) << div->shift);
+ val |= (u32)value << div->shift;
+
+ writel(val, div->reg);
+ writel(val, fixup_div->reg_fixup);
+
+ pr_debug("%s: %s: reg_fixup = %x\n",
+ __func__, clk_hw_get_name(hw), readl(fixup_div->reg_fixup));
+
+ spin_unlock_irqrestore(div->lock, flags);
+
+ return 0;
+}
+
+static const struct clk_ops clk_fixup_div_ops = {
+ .recalc_rate = clk_fixup_div_recalc_rate,
+ .round_rate = clk_fixup_div_round_rate,
+ .set_rate = clk_fixup_div_set_rate,
+};
+
+struct clk *mtk_clk_fixup_divider(const char *name, const char *parent,
+ unsigned long flags, void __iomem *reg,
+ void __iomem *reg_fixup, u8 shift, u8 width,
+ u8 clk_divider_flags, spinlock_t *lock)
+{
+ struct clk_fixup_div *fixup_div;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ fixup_div = kzalloc(sizeof(*fixup_div), GFP_KERNEL);
+ if (!fixup_div)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &clk_fixup_div_ops;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = parent ? &parent : NULL;
+ init.num_parents = parent ? 1 : 0;
+
+ fixup_div->reg_fixup = reg_fixup;
+ fixup_div->divider.reg = reg;
+ fixup_div->divider.flags = clk_divider_flags;
+ fixup_div->divider.shift = shift;
+ fixup_div->divider.width = width;
+ fixup_div->divider.lock = lock;
+ fixup_div->divider.hw.init = &init;
+ fixup_div->ops = &clk_divider_ops;
+
+ clk = clk_register(NULL, &fixup_div->divider.hw);
+ if (IS_ERR(clk))
+ kfree(fixup_div);
+
+ return clk;
+}
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fixup-div.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fixup-div.h
new file mode 100644
index 0000000..5d52afd
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-fixup-div.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __DRV_CLK_FIXUP_DIV_H
+#define __DRV_CLK_FIXUP_DIV_H
+
+#include <linux/clk-provider.h>
+
+struct clk;
+
+struct clk_fixup_div {
+ int id;
+ const char *name;
+ const char *parent_name;
+
+ void __iomem *reg_fixup;
+ const struct clk_div_table *clk_div_table;
+
+ struct clk_divider divider;
+ const struct clk_ops *ops;
+
+};
+
+static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+
+ return container_of(divider, struct clk_fixup_div, divider);
+}
+
+struct clk *mtk_clk_fixup_divider(
+ const char *name,
+ const char *parent,
+ unsigned long flags,
+ void __iomem *reg,
+ void __iomem *reg_fixup,
+ u8 shift,
+ u8 width,
+ u8 clk_divider_flags,
+ spinlock_t *lock);
+
+#endif /* __DRV_CLK_FIXUP_DIV_H */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-gate.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-gate.c
new file mode 100644
index 0000000..75d5845
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-gate.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/clkdev.h>
+#include "clk-mtk.h"
+#include "clk-gate.h"
+#define INV_OFS -1
+static int is_subsys_pwr_on(struct mtk_clk_gate *cg)
+{
+ struct pwr_status *pwr = cg->pwr_stat;
+ u32 val = 0, val2 = 0;
+ if (pwr != NULL && cg->pwr_regmap != NULL) {
+ if (pwr->pwr_ofs != INV_OFS && pwr->pwr2_ofs != INV_OFS) {
+ regmap_read(cg->pwr_regmap, pwr->pwr_ofs, &val);
+ regmap_read(cg->pwr_regmap, pwr->pwr2_ofs, &val2);
+ if ((val & pwr->mask) != pwr->val &&
+ (val2 & pwr->mask) != pwr->val)
+ return false;
+ } else if (pwr->other_ofs != INV_OFS) {
+ regmap_read(cg->pwr_regmap, pwr->other_ofs, &val);
+ if ((val & pwr->mask) != pwr->val)
+ return false;
+ }
+ }
+ return true;
+}
+static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ u32 val;
+ regmap_read(cg->regmap, cg->sta_ofs, &val);
+ val &= BIT(cg->bit);
+ return val == 0;
+}
+static int mtk_cg_bit_is_set(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ u32 val;
+ regmap_read(cg->regmap, cg->sta_ofs, &val);
+ val &= BIT(cg->bit);
+ return val != 0;
+}
+static int mtk_cg_is_enabled(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ struct clk_hw *p_hw = clk_hw_get_parent(hw);
+ struct clk_hw *mux_hw = clk_hw_get_parent(p_hw);
+ const char *c_n = clk_hw_get_name(hw);
+ const char *mux_n = clk_hw_get_name(mux_hw);
+ pr_notice("%s: c(%s), p(%s) is %s\n", __func__, c_n, mux_n,
+ clk_hw_is_enabled(mux_hw) ? "enabled" : "disabled");
+ if (!clk_hw_is_enabled(mux_hw))
+ return 0;
+ if (!is_subsys_pwr_on(cg))
+ return 0;
+ return mtk_cg_bit_is_cleared(hw);
+}
+static int mtk_en_is_enabled(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ struct clk_hw *p_hw = clk_hw_get_parent(hw);
+ struct clk_hw *mux_hw = clk_hw_get_parent(p_hw);
+ const char *c_n = clk_hw_get_name(hw);
+ const char *mux_n = clk_hw_get_name(mux_hw);
+ pr_notice("%s: c(%s), p(%s) is %s\n", __func__, c_n, mux_n,
+ clk_hw_is_enabled(mux_hw) ? "enabled" : "disabled");
+ if (!clk_hw_is_enabled(mux_hw))
+ return 0;
+ if (!is_subsys_pwr_on(cg))
+ return 0;
+ return mtk_cg_bit_is_set(hw);
+}
+static void mtk_cg_set_bit(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+#ifdef CONFIG_MACH_MT6853
+ int val = 0;
+ int i = 0;
+#endif
+ regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
+#ifdef CONFIG_MACH_MT6853
+ regmap_read(cg->regmap, cg->sta_ofs, &val);
+ while ((val & BIT(cg->bit)) != BIT(cg->bit)) {
+ regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
+ regmap_read(cg->regmap, cg->sta_ofs, &val);
+ if (i > 5)
+ break;
+ i++;
+ }
+#endif
+}
+static void mtk_cg_clr_bit(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+#ifdef CONFIG_MACH_MT6853
+ int val = 0;
+ int i = 0;
+#endif
+ regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
+#ifdef CONFIG_MACH_MT6853
+ regmap_read(cg->regmap, cg->sta_ofs, &val);
+ while ((val & BIT(cg->bit)) != 0) {
+ regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
+ regmap_read(cg->regmap, cg->sta_ofs, &val);
+ if (i > 5)
+ break;
+ i++;
+ }
+#endif
+}
+static void mtk_cg_set_bit_unused(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ const char *c_n = clk_hw_get_name(hw);
+ pr_notice("disable_unused - %s\n", c_n);
+ regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
+}
+static void mtk_cg_clr_bit_unused(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ const char *c_n = clk_hw_get_name(hw);
+ pr_notice("disable_unused - %s\n", c_n);
+ regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
+}
+static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ u32 cgbit = BIT(cg->bit);
+ regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, cgbit);
+}
+static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ u32 cgbit = BIT(cg->bit);
+ regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, 0);
+}
+static int mtk_cg_enable(struct clk_hw *hw)
+{
+ mtk_cg_clr_bit(hw);
+ return 0;
+}
+static void mtk_cg_disable(struct clk_hw *hw)
+{
+ mtk_cg_set_bit(hw);
+}
+static void mtk_cg_disable_unused(struct clk_hw *hw)
+{
+ mtk_cg_set_bit_unused(hw);
+}
+static int mtk_cg_enable_inv(struct clk_hw *hw)
+{
+ mtk_cg_set_bit(hw);
+ return 0;
+}
+static void mtk_cg_disable_inv(struct clk_hw *hw)
+{
+ mtk_cg_clr_bit(hw);
+}
+static void mtk_cg_disable_inv_unused(struct clk_hw *hw)
+{
+ mtk_cg_clr_bit_unused(hw);
+}
+static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
+{
+ mtk_cg_clr_bit_no_setclr(hw);
+ return 0;
+}
+static void mtk_cg_disable_no_setclr(struct clk_hw *hw)
+{
+ mtk_cg_set_bit_no_setclr(hw);
+}
+static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw)
+{
+ mtk_cg_set_bit_no_setclr(hw);
+ return 0;
+}
+static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)
+{
+ mtk_cg_clr_bit_no_setclr(hw);
+}
+const struct clk_ops mtk_clk_gate_ops_setclr = {
+ .is_enabled = mtk_cg_is_enabled,
+ .enable = mtk_cg_enable,
+ .disable = mtk_cg_disable,
+ .disable_unused = mtk_cg_disable_unused,
+};
+const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
+ .is_enabled = mtk_en_is_enabled,
+ .enable = mtk_cg_enable_inv,
+ .disable = mtk_cg_disable_inv,
+ .disable_unused = mtk_cg_disable_inv_unused,
+};
+const struct clk_ops mtk_clk_gate_ops_no_setclr = {
+ .is_enabled = mtk_cg_is_enabled,
+ .enable = mtk_cg_enable_no_setclr,
+ .disable = mtk_cg_disable_no_setclr,
+};
+const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
+ .is_enabled = mtk_en_is_enabled,
+ .enable = mtk_cg_enable_inv_no_setclr,
+ .disable = mtk_cg_disable_inv_no_setclr,
+};
+struct clk *mtk_clk_register_gate(
+ const char *name,
+ const char *parent_name,
+ struct regmap *regmap,
+ int set_ofs,
+ int clr_ofs,
+ int sta_ofs,
+ u8 bit,
+ const struct clk_ops *ops,
+ unsigned long flags,
+ struct pwr_status *pwr_stat,
+ struct regmap *pwr_regmap)
+{
+ struct mtk_clk_gate *cg;
+ struct clk *clk;
+ struct clk_init_data init = {};
+ cg = kzalloc(sizeof(*cg), GFP_KERNEL);
+ if (!cg)
+ return ERR_PTR(-ENOMEM);
+ init.name = name;
+ init.flags = flags | CLK_SET_RATE_PARENT;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.ops = ops;
+ cg->regmap = regmap;
+ cg->set_ofs = set_ofs;
+ cg->clr_ofs = clr_ofs;
+ cg->sta_ofs = sta_ofs;
+ cg->bit = bit;
+ cg->pwr_stat = pwr_stat;
+ cg->pwr_regmap = pwr_regmap;
+ cg->hw.init = &init;
+ clk = clk_register(NULL, &cg->hw);
+ if (IS_ERR(clk))
+ kfree(cg);
+ return clk;
+}
\ No newline at end of file
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-gate.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-gate.h
new file mode 100644
index 0000000..98a9850
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-gate.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DRV_CLK_GATE_H
+#define __DRV_CLK_GATE_H
+#include <linux/regmap.h>
+#include <linux/clk-provider.h>
+struct clk;
+/*
+ * define pwr status information.
+ * including offsets/mask.
+ */
+struct pwr_status {
+ s32 pwr_ofs;
+ s32 pwr2_ofs;
+ s32 other_ofs;
+ u32 mask;
+ u32 val;
+};
+struct mtk_clk_gate {
+ struct clk_hw hw;
+ struct regmap *regmap;
+ int set_ofs;
+ int clr_ofs;
+ int sta_ofs;
+ u8 bit;
+ struct pwr_status *pwr_stat;
+ struct regmap *pwr_regmap;
+};
+static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
+{
+ return container_of(hw, struct mtk_clk_gate, hw);
+}
+extern const struct clk_ops mtk_clk_gate_ops_setclr;
+extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
+extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
+extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
+struct clk *mtk_clk_register_gate(
+ const char *name,
+ const char *parent_name,
+ struct regmap *regmap,
+ int set_ofs,
+ int clr_ofs,
+ int sta_ofs,
+ u8 bit,
+ const struct clk_ops *ops,
+ unsigned long flags,
+ struct pwr_status *pwr_stat,
+ struct regmap *pwr_regmap);
+#define GATE_PWR_STAT(_pwr_ofs, _pwr2_ofs, _other_ofs, _mask, _val) { \
+ .pwr_ofs = _pwr_ofs, \
+ .pwr2_ofs = _pwr2_ofs, \
+ .other_ofs = _other_ofs, \
+ .mask = _mask, \
+ .val = _val, \
+}
+#endif /* __DRV_CLK_GATE_H */
\ No newline at end of file
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-aud.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-aud.c
new file mode 100644
index 0000000..e66896a
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-aud.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2701-clk.h>
+
+#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audio0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audio1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_AUDIO2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audio2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_AUDIO3(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audio3_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+static const struct mtk_gate_regs audio0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs audio1_cg_regs = {
+ .set_ofs = 0x10,
+ .clr_ofs = 0x10,
+ .sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs audio2_cg_regs = {
+ .set_ofs = 0x14,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x14,
+};
+
+static const struct mtk_gate_regs audio3_cg_regs = {
+ .set_ofs = 0x634,
+ .clr_ofs = 0x634,
+ .sta_ofs = 0x634,
+};
+
+static const struct mtk_gate audio_clks[] = {
+ /* AUDIO0 */
+ GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
+ GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
+ GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
+ GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
+ GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
+ /* AUDIO1 */
+ GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
+ GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
+ GATE_AUDIO1(CLK_AUD_I2SIN3, "audio_i2sin3", "aud_mux1_sel", 2),
+ GATE_AUDIO1(CLK_AUD_I2SIN4, "audio_i2sin4", "aud_mux1_sel", 3),
+ GATE_AUDIO1(CLK_AUD_I2SIN5, "audio_i2sin5", "aud_mux1_sel", 4),
+ GATE_AUDIO1(CLK_AUD_I2SIN6, "audio_i2sin6", "aud_mux1_sel", 5),
+ GATE_AUDIO1(CLK_AUD_I2SO1, "audio_i2so1", "aud_mux1_sel", 6),
+ GATE_AUDIO1(CLK_AUD_I2SO2, "audio_i2so2", "aud_mux1_sel", 7),
+ GATE_AUDIO1(CLK_AUD_I2SO3, "audio_i2so3", "aud_mux1_sel", 8),
+ GATE_AUDIO1(CLK_AUD_I2SO4, "audio_i2so4", "aud_mux1_sel", 9),
+ GATE_AUDIO1(CLK_AUD_I2SO5, "audio_i2so5", "aud_mux1_sel", 10),
+ GATE_AUDIO1(CLK_AUD_I2SO6, "audio_i2so6", "aud_mux1_sel", 11),
+ GATE_AUDIO1(CLK_AUD_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
+ GATE_AUDIO1(CLK_AUD_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
+ GATE_AUDIO1(CLK_AUD_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
+ GATE_AUDIO1(CLK_AUD_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
+ GATE_AUDIO1(CLK_AUD_INTDIR, "audio_intdir", "intdir_sel", 20),
+ GATE_AUDIO1(CLK_AUD_A1SYS, "audio_a1sys", "aud_mux1_sel", 21),
+ GATE_AUDIO1(CLK_AUD_A2SYS, "audio_a2sys", "aud_mux2_sel", 22),
+ GATE_AUDIO1(CLK_AUD_AFE_CONN, "audio_afe_conn", "aud_mux1_sel", 23),
+ GATE_AUDIO1(CLK_AUD_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
+ /* AUDIO2 */
+ GATE_AUDIO2(CLK_AUD_MMIF_UL1, "audio_ul1", "aud_mux1_sel", 0),
+ GATE_AUDIO2(CLK_AUD_MMIF_UL2, "audio_ul2", "aud_mux1_sel", 1),
+ GATE_AUDIO2(CLK_AUD_MMIF_UL3, "audio_ul3", "aud_mux1_sel", 2),
+ GATE_AUDIO2(CLK_AUD_MMIF_UL4, "audio_ul4", "aud_mux1_sel", 3),
+ GATE_AUDIO2(CLK_AUD_MMIF_UL5, "audio_ul5", "aud_mux1_sel", 4),
+ GATE_AUDIO2(CLK_AUD_MMIF_UL6, "audio_ul6", "aud_mux1_sel", 5),
+ GATE_AUDIO2(CLK_AUD_MMIF_DL1, "audio_dl1", "aud_mux1_sel", 6),
+ GATE_AUDIO2(CLK_AUD_MMIF_DL2, "audio_dl2", "aud_mux1_sel", 7),
+ GATE_AUDIO2(CLK_AUD_MMIF_DL3, "audio_dl3", "aud_mux1_sel", 8),
+ GATE_AUDIO2(CLK_AUD_MMIF_DL4, "audio_dl4", "aud_mux1_sel", 9),
+ GATE_AUDIO2(CLK_AUD_MMIF_DL5, "audio_dl5", "aud_mux1_sel", 10),
+ GATE_AUDIO2(CLK_AUD_MMIF_DL6, "audio_dl6", "aud_mux1_sel", 11),
+ GATE_AUDIO2(CLK_AUD_MMIF_DLMCH, "audio_dlmch", "aud_mux1_sel", 12),
+ GATE_AUDIO2(CLK_AUD_MMIF_ARB1, "audio_arb1", "aud_mux1_sel", 13),
+ GATE_AUDIO2(CLK_AUD_MMIF_AWB1, "audio_awb", "aud_mux1_sel", 14),
+ GATE_AUDIO2(CLK_AUD_MMIF_AWB2, "audio_awb2", "aud_mux1_sel", 15),
+ GATE_AUDIO2(CLK_AUD_MMIF_DAI, "audio_dai", "aud_mux1_sel", 16),
+ /* AUDIO3 */
+ GATE_AUDIO3(CLK_AUD_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
+ GATE_AUDIO3(CLK_AUD_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
+ GATE_AUDIO3(CLK_AUD_ASRCI5, "audio_asrci5", "asm_h_sel", 4),
+ GATE_AUDIO3(CLK_AUD_ASRCI6, "audio_asrci6", "asm_h_sel", 5),
+ GATE_AUDIO3(CLK_AUD_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
+ GATE_AUDIO3(CLK_AUD_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
+ GATE_AUDIO3(CLK_AUD_ASRCO5, "audio_asrco5", "asm_h_sel", 8),
+ GATE_AUDIO3(CLK_AUD_ASRCO6, "audio_asrco6", "asm_h_sel", 9),
+ GATE_AUDIO3(CLK_AUD_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
+ GATE_AUDIO3(CLK_AUD_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
+ GATE_AUDIO3(CLK_AUD_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
+ GATE_AUDIO3(CLK_AUD_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
+ GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
+};
+
+static const struct of_device_id of_match_clk_mt2701_aud[] = {
+ { .compatible = "mediatek,mt2701-audsys", },
+ {}
+};
+
+static int clk_mt2701_aud_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
+
+ mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r) {
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ goto err_clk_provider;
+ }
+
+ r = devm_of_platform_populate(&pdev->dev);
+ if (r)
+ goto err_plat_populate;
+
+ return 0;
+
+err_plat_populate:
+ of_clk_del_provider(node);
+err_clk_provider:
+ return r;
+}
+
+static struct platform_driver clk_mt2701_aud_drv = {
+ .probe = clk_mt2701_aud_probe,
+ .driver = {
+ .name = "clk-mt2701-aud",
+ .of_match_table = of_match_clk_mt2701_aud,
+ },
+};
+
+builtin_platform_driver(clk_mt2701_aud_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-bdp.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-bdp.c
new file mode 100644
index 0000000..fe4964d
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-bdp.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang <shunli.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2701-clk.h>
+
+static const struct mtk_gate_regs bdp0_cg_regs = {
+ .set_ofs = 0x0104,
+ .clr_ofs = 0x0108,
+ .sta_ofs = 0x0100,
+};
+
+static const struct mtk_gate_regs bdp1_cg_regs = {
+ .set_ofs = 0x0114,
+ .clr_ofs = 0x0118,
+ .sta_ofs = 0x0110,
+};
+
+#define GATE_BDP0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &bdp0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_BDP1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &bdp1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate bdp_clks[] = {
+ GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
+ GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
+ GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),
+ GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3),
+ GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4),
+ GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5),
+ GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6),
+ GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi1_sel", 7),
+ GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8),
+ GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9),
+ GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10),
+ GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11),
+ GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12),
+ GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13),
+ GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14),
+ GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15),
+ GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16),
+ GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17),
+ GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18),
+ GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19),
+ GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20),
+ GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21),
+ GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22),
+ GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23),
+ GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24),
+ GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25),
+ GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26),
+ GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27),
+ GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28),
+ GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29),
+ GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30),
+ GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31),
+ GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0),
+ GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1),
+ GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2),
+ GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3),
+ GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4),
+ GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5),
+ GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6),
+ GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7),
+ GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8),
+ GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9),
+ GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10),
+ GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11),
+ GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
+ GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
+ GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
+ GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
+ GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16),
+};
+
+static const struct of_device_id of_match_clk_mt2701_bdp[] = {
+ { .compatible = "mediatek,mt2701-bdpsys", },
+ {}
+};
+
+static int clk_mt2701_bdp_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
+
+ mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt2701_bdp_drv = {
+ .probe = clk_mt2701_bdp_probe,
+ .driver = {
+ .name = "clk-mt2701-bdp",
+ .of_match_table = of_match_clk_mt2701_bdp,
+ },
+};
+
+builtin_platform_driver(clk_mt2701_bdp_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-eth.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-eth.c
new file mode 100644
index 0000000..9251a65
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang <shunli.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2701-clk.h>
+
+static const struct mtk_gate_regs eth_cg_regs = {
+ .sta_ofs = 0x0030,
+};
+
+#define GATE_ETH(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = ð_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate eth_clks[] = {
+ GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
+ GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
+ GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
+ GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
+ GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
+ GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
+ GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
+ GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
+};
+
+static const struct of_device_id of_match_clk_mt2701_eth[] = {
+ { .compatible = "mediatek,mt2701-ethsys", },
+ {}
+};
+
+static int clk_mt2701_eth_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
+
+ mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ mtk_register_reset_controller(node, 1, 0x34);
+
+ return r;
+}
+
+static struct platform_driver clk_mt2701_eth_drv = {
+ .probe = clk_mt2701_eth_probe,
+ .driver = {
+ .name = "clk-mt2701-eth",
+ .of_match_table = of_match_clk_mt2701_eth,
+ },
+};
+
+builtin_platform_driver(clk_mt2701_eth_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-g3d.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-g3d.c
new file mode 100644
index 0000000..1328c11
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Sean Wang <sean.wang@mediatek.com>
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2701-clk.h>
+
+#define GATE_G3D(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &g3d_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate_regs g3d_cg_regs = {
+ .sta_ofs = 0x0,
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+};
+
+static const struct mtk_gate g3d_clks[] = {
+ GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
+};
+
+static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
+
+ mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ mtk_register_reset_controller(node, 1, 0xc);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt2701_g3d[] = {
+ {
+ .compatible = "mediatek,mt2701-g3dsys",
+ .data = clk_mt2701_g3dsys_init,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt2701_g3d_probe(struct platform_device *pdev)
+{
+ int (*clk_init)(struct platform_device *);
+ int r;
+
+ clk_init = of_device_get_match_data(&pdev->dev);
+ if (!clk_init)
+ return -EINVAL;
+
+ r = clk_init(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt2701_g3d_drv = {
+ .probe = clk_mt2701_g3d_probe,
+ .driver = {
+ .name = "clk-mt2701-g3d",
+ .of_match_table = of_match_clk_mt2701_g3d,
+ },
+};
+
+builtin_platform_driver(clk_mt2701_g3d_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-hif.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-hif.c
new file mode 100644
index 0000000..18f3723
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang <shunli.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2701-clk.h>
+
+static const struct mtk_gate_regs hif_cg_regs = {
+ .sta_ofs = 0x0030,
+};
+
+#define GATE_HIF(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &hif_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate hif_clks[] = {
+ GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
+ GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
+ GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
+ GATE_HIF(CLK_HIFSYS_PCIE1, "pcie1_clk", "ethpll_500m_ck", 25),
+ GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
+};
+
+static const struct of_device_id of_match_clk_mt2701_hif[] = {
+ { .compatible = "mediatek,mt2701-hifsys", },
+ {}
+};
+
+static int clk_mt2701_hif_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
+
+ mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r) {
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+ return r;
+ }
+
+ mtk_register_reset_controller(node, 1, 0x34);
+
+ return 0;
+}
+
+static struct platform_driver clk_mt2701_hif_drv = {
+ .probe = clk_mt2701_hif_probe,
+ .driver = {
+ .name = "clk-mt2701-hif",
+ .of_match_table = of_match_clk_mt2701_hif,
+ },
+};
+
+builtin_platform_driver(clk_mt2701_hif_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-img.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-img.c
new file mode 100644
index 0000000..b7441c9
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-img.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang <shunli.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2701-clk.h>
+
+static const struct mtk_gate_regs img_cg_regs = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_IMG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &img_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate img_clks[] = {
+ GATE_IMG(CLK_IMG_SMI_COMM, "img_smi_comm", "mm_sel", 0),
+ GATE_IMG(CLK_IMG_RESZ, "img_resz", "mm_sel", 1),
+ GATE_IMG(CLK_IMG_JPGDEC_SMI, "img_jpgdec_smi", "mm_sel", 5),
+ GATE_IMG(CLK_IMG_JPGDEC, "img_jpgdec", "mm_sel", 6),
+ GATE_IMG(CLK_IMG_VENC_LT, "img_venc_lt", "mm_sel", 8),
+ GATE_IMG(CLK_IMG_VENC, "img_venc", "mm_sel", 9),
+};
+
+static const struct of_device_id of_match_clk_mt2701_img[] = {
+ { .compatible = "mediatek,mt2701-imgsys", },
+ {}
+};
+
+static int clk_mt2701_img_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
+
+ mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt2701_img_drv = {
+ .probe = clk_mt2701_img_probe,
+ .driver = {
+ .name = "clk-mt2701-img",
+ .of_match_table = of_match_clk_mt2701_img,
+ },
+};
+
+builtin_platform_driver(clk_mt2701_img_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-mm.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-mm.c
new file mode 100644
index 0000000..fe1f850
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-mm.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang <shunli.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2701-clk.h>
+
+static const struct mtk_gate_regs disp0_cg_regs = {
+ .set_ofs = 0x0104,
+ .clr_ofs = 0x0108,
+ .sta_ofs = 0x0100,
+};
+
+static const struct mtk_gate_regs disp1_cg_regs = {
+ .set_ofs = 0x0114,
+ .clr_ofs = 0x0118,
+ .sta_ofs = 0x0110,
+};
+
+#define GATE_DISP0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &disp0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_DISP1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &disp1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate mm_clks[] = {
+ GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0),
+ GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
+ GATE_DISP0(CLK_MM_CMDQ, "mm_cmdq", "mm_sel", 2),
+ GATE_DISP0(CLK_MM_MUTEX, "mm_mutex", "mm_sel", 3),
+ GATE_DISP0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 4),
+ GATE_DISP0(CLK_MM_DISP_BLS, "mm_disp_bls", "mm_sel", 5),
+ GATE_DISP0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "mm_sel", 6),
+ GATE_DISP0(CLK_MM_DISP_RDMA, "mm_disp_rdma", "mm_sel", 7),
+ GATE_DISP0(CLK_MM_DISP_OVL, "mm_disp_ovl", "mm_sel", 8),
+ GATE_DISP0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
+ GATE_DISP0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "mm_sel", 10),
+ GATE_DISP0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
+ GATE_DISP0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 12),
+ GATE_DISP0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 13),
+ GATE_DISP0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "mm_sel", 14),
+ GATE_DISP0(CLK_MM_MDP_BLS_26M, "mm_mdp_bls_26m", "pwm_sel", 15),
+ GATE_DISP0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 16),
+ GATE_DISP0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 17),
+ GATE_DISP0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 18),
+ GATE_DISP0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
+ GATE_DISP0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 20),
+ GATE_DISP1(CLK_MM_DSI_ENGINE, "mm_dsi_eng", "mm_sel", 0),
+ GATE_DISP1(CLK_MM_DSI_DIG, "mm_dsi_dig", "dsi0_lntc_dsi", 1),
+ GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2),
+ GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3),
+ GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4),
+ GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5),
+ GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6),
+ GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7),
+ GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8),
+ GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9),
+ GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10),
+ GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11),
+ GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14),
+};
+
+static const struct of_device_id of_match_clk_mt2701_mm[] = {
+ { .compatible = "mediatek,mt2701-mmsys", },
+ {}
+};
+
+static int clk_mt2701_mm_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_MM_NR);
+
+ mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt2701_mm_drv = {
+ .probe = clk_mt2701_mm_probe,
+ .driver = {
+ .name = "clk-mt2701-mm",
+ .of_match_table = of_match_clk_mt2701_mm,
+ },
+};
+
+builtin_platform_driver(clk_mt2701_mm_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-vdec.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-vdec.c
new file mode 100644
index 0000000..d3c0fc9
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701-vdec.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang <shunli.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2701-clk.h>
+
+static const struct mtk_gate_regs vdec0_cg_regs = {
+ .set_ofs = 0x0000,
+ .clr_ofs = 0x0004,
+ .sta_ofs = 0x0000,
+};
+
+static const struct mtk_gate_regs vdec1_cg_regs = {
+ .set_ofs = 0x0008,
+ .clr_ofs = 0x000c,
+ .sta_ofs = 0x0008,
+};
+
+#define GATE_VDEC0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vdec0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VDEC1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vdec1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate vdec_clks[] = {
+ GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0),
+ GATE_VDEC1(CLK_VDEC_LARB, "vdec_larb_cken", "mm_sel", 0),
+};
+
+static const struct of_device_id of_match_clk_mt2701_vdec[] = {
+ { .compatible = "mediatek,mt2701-vdecsys", },
+ {}
+};
+
+static int clk_mt2701_vdec_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
+
+ mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt2701_vdec_drv = {
+ .probe = clk_mt2701_vdec_probe,
+ .driver = {
+ .name = "clk-mt2701-vdec",
+ .of_match_table = of_match_clk_mt2701_vdec,
+ },
+};
+
+builtin_platform_driver(clk_mt2701_vdec_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701.c
new file mode 100644
index 0000000..4dda898
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2701.c
@@ -0,0 +1,1048 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang <shunli.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+#include "clk-cpumux.h"
+
+#include <dt-bindings/clock/mt2701-clk.h>
+
+/*
+ * For some clocks, we don't care what their actual rates are. And these
+ * clocks may change their rate on different products or different scenarios.
+ * So we model these clocks' rate as 0, to denote it's not an actual rate.
+ */
+#define DUMMY_RATE 0
+
+static DEFINE_SPINLOCK(mt2701_clk_lock);
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m",
+ 108 * MHZ),
+ FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m",
+ 400 * MHZ),
+ FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m",
+ 295750000),
+ FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m",
+ 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m",
+ 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
+ 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
+ 27 * MHZ),
+ FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
+ 416 * MHZ),
+ FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m",
+ 143 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m",
+ 27 * MHZ),
+ FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m",
+ DUMMY_RATE),
+ FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m",
+ DUMMY_RATE),
+ FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m",
+ DUMMY_RATE),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
+ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
+ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
+ FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
+ FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
+ FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
+ FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
+ FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
+
+ FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
+ FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
+ FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
+ FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
+ FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
+ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
+ FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
+ FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
+ FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
+
+ FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
+ FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
+ FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
+
+ FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
+ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
+
+ FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
+ FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
+ FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
+
+ FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
+ FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
+ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
+
+ FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
+ FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
+ FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
+
+ FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
+ FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
+ FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
+
+ FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
+ FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
+ FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
+
+ FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
+
+ FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
+ FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
+ FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
+ FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
+ FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
+
+ FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
+ FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
+ FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
+ FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
+ FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
+ FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
+ FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
+ FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
+ FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
+};
+
+static const char * const axi_parents[] = {
+ "clk26m",
+ "syspll1_d2",
+ "syspll_d5",
+ "syspll1_d4",
+ "univpll_d5",
+ "univpll2_d2",
+ "mmpll_d2",
+ "dmpll_d2"
+};
+
+static const char * const mem_parents[] = {
+ "clk26m",
+ "dmpll_ck"
+};
+
+static const char * const ddrphycfg_parents[] = {
+ "clk26m",
+ "syspll1_d8"
+};
+
+static const char * const mm_parents[] = {
+ "clk26m",
+ "vencpll_ck",
+ "syspll1_d2",
+ "syspll1_d4",
+ "univpll_d5",
+ "univpll1_d2",
+ "univpll2_d2",
+ "dmpll_ck"
+};
+
+static const char * const pwm_parents[] = {
+ "clk26m",
+ "univpll2_d4",
+ "univpll3_d2",
+ "univpll1_d4",
+};
+
+static const char * const vdec_parents[] = {
+ "clk26m",
+ "vdecpll_ck",
+ "syspll_d5",
+ "syspll1_d4",
+ "univpll_d5",
+ "univpll2_d2",
+ "vencpll_ck",
+ "msdcpll_d2",
+ "mmpll_d2"
+};
+
+static const char * const mfg_parents[] = {
+ "clk26m",
+ "mmpll_ck",
+ "dmpll_x2_ck",
+ "msdcpll_ck",
+ "clk26m",
+ "syspll_d3",
+ "univpll_d3",
+ "univpll1_d2"
+};
+
+static const char * const camtg_parents[] = {
+ "clk26m",
+ "univpll_d26",
+ "univpll2_d2",
+ "syspll3_d2",
+ "syspll3_d4",
+ "msdcpll_d2",
+ "mmpll_d2"
+};
+
+static const char * const uart_parents[] = {
+ "clk26m",
+ "univpll2_d8"
+};
+
+static const char * const spi_parents[] = {
+ "clk26m",
+ "syspll3_d2",
+ "syspll4_d2",
+ "univpll2_d4",
+ "univpll1_d8"
+};
+
+static const char * const usb20_parents[] = {
+ "clk26m",
+ "univpll1_d8",
+ "univpll3_d4"
+};
+
+static const char * const msdc30_parents[] = {
+ "clk26m",
+ "msdcpll_d2",
+ "syspll2_d2",
+ "syspll1_d4",
+ "univpll1_d4",
+ "univpll2_d4"
+};
+
+static const char * const audio_parents[] = {
+ "clk26m",
+ "syspll1_d16"
+};
+
+static const char * const aud_intbus_parents[] = {
+ "clk26m",
+ "syspll1_d4",
+ "syspll3_d2",
+ "syspll4_d2",
+ "univpll3_d2",
+ "univpll2_d4"
+};
+
+static const char * const pmicspi_parents[] = {
+ "clk26m",
+ "syspll1_d8",
+ "syspll2_d4",
+ "syspll4_d2",
+ "syspll3_d4",
+ "syspll2_d8",
+ "syspll1_d16",
+ "univpll3_d4",
+ "univpll_d26",
+ "dmpll_d2",
+ "dmpll_d4"
+};
+
+static const char * const scp_parents[] = {
+ "clk26m",
+ "syspll1_d8",
+ "dmpll_d2",
+ "dmpll_d4"
+};
+
+static const char * const dpi0_parents[] = {
+ "clk26m",
+ "mipipll",
+ "mipipll_d2",
+ "mipipll_d4",
+ "clk26m",
+ "tvdpll_ck",
+ "tvdpll_d2",
+ "tvdpll_d4"
+};
+
+static const char * const dpi1_parents[] = {
+ "clk26m",
+ "tvdpll_ck",
+ "tvdpll_d2",
+ "tvdpll_d4"
+};
+
+static const char * const tve_parents[] = {
+ "clk26m",
+ "mipipll",
+ "mipipll_d2",
+ "mipipll_d4",
+ "clk26m",
+ "tvdpll_ck",
+ "tvdpll_d2",
+ "tvdpll_d4"
+};
+
+static const char * const hdmi_parents[] = {
+ "clk26m",
+ "hdmipll_ck",
+ "hdmipll_d2",
+ "hdmipll_d3"
+};
+
+static const char * const apll_parents[] = {
+ "clk26m",
+ "audpll",
+ "audpll_d4",
+ "audpll_d8",
+ "audpll_d16",
+ "audpll_d24",
+ "clk26m",
+ "clk26m"
+};
+
+static const char * const rtc_parents[] = {
+ "32k_internal",
+ "32k_external",
+ "clk26m",
+ "univpll3_d8"
+};
+
+static const char * const nfi2x_parents[] = {
+ "clk26m",
+ "syspll2_d2",
+ "syspll_d7",
+ "univpll3_d2",
+ "syspll2_d4",
+ "univpll3_d4",
+ "syspll4_d4",
+ "clk26m"
+};
+
+static const char * const emmc_hclk_parents[] = {
+ "clk26m",
+ "syspll1_d2",
+ "syspll1_d4",
+ "syspll2_d2"
+};
+
+static const char * const flash_parents[] = {
+ "clk26m_d8",
+ "clk26m",
+ "syspll2_d8",
+ "syspll3_d4",
+ "univpll3_d4",
+ "syspll4_d2",
+ "syspll2_d4",
+ "univpll2_d4"
+};
+
+static const char * const di_parents[] = {
+ "clk26m",
+ "tvd2pll_ck",
+ "tvd2pll_d2",
+ "clk26m"
+};
+
+static const char * const nr_osd_parents[] = {
+ "clk26m",
+ "vencpll_ck",
+ "syspll1_d2",
+ "syspll1_d4",
+ "univpll_d5",
+ "univpll1_d2",
+ "univpll2_d2",
+ "dmpll_ck"
+};
+
+static const char * const hdmirx_bist_parents[] = {
+ "clk26m",
+ "syspll_d3",
+ "clk26m",
+ "syspll1_d16",
+ "syspll4_d2",
+ "syspll1_d4",
+ "vencpll_ck",
+ "clk26m"
+};
+
+static const char * const intdir_parents[] = {
+ "clk26m",
+ "mmpll_ck",
+ "syspll_d2",
+ "univpll_d2"
+};
+
+static const char * const asm_parents[] = {
+ "clk26m",
+ "univpll2_d4",
+ "univpll2_d2",
+ "syspll_d5"
+};
+
+static const char * const ms_card_parents[] = {
+ "clk26m",
+ "univpll3_d8",
+ "syspll4_d4"
+};
+
+static const char * const ethif_parents[] = {
+ "clk26m",
+ "syspll1_d2",
+ "syspll_d5",
+ "syspll1_d4",
+ "univpll_d5",
+ "univpll1_d2",
+ "dmpll_ck",
+ "dmpll_d2"
+};
+
+static const char * const hdmirx_parents[] = {
+ "clk26m",
+ "univpll_d52"
+};
+
+static const char * const cmsys_parents[] = {
+ "clk26m",
+ "syspll1_d2",
+ "univpll1_d2",
+ "univpll_d5",
+ "syspll_d5",
+ "syspll2_d2",
+ "syspll1_d4",
+ "syspll3_d2",
+ "syspll2_d4",
+ "syspll1_d8",
+ "clk26m",
+ "clk26m",
+ "clk26m",
+ "clk26m",
+ "clk26m"
+};
+
+static const char * const clk_8bdac_parents[] = {
+ "32k_internal",
+ "8bdac_ck",
+ "clk26m",
+ "clk26m"
+};
+
+static const char * const aud2dvd_parents[] = {
+ "a1sys_hp_ck",
+ "a2sys_hp_ck"
+};
+
+static const char * const padmclk_parents[] = {
+ "clk26m",
+ "univpll_d26",
+ "univpll_d52",
+ "univpll_d108",
+ "univpll2_d8",
+ "univpll2_d16",
+ "univpll2_d32"
+};
+
+static const char * const aud_mux_parents[] = {
+ "clk26m",
+ "aud1pll_98m_ck",
+ "aud2pll_90m_ck",
+ "hadds2pll_98m",
+ "audio_ext1_ck",
+ "audio_ext2_ck"
+};
+
+static const char * const aud_src_parents[] = {
+ "aud_mux1_sel",
+ "aud_mux2_sel"
+};
+
+static const char * const cpu_parents[] = {
+ "clk26m",
+ "armpll",
+ "mainpll",
+ "mmpll"
+};
+
+static const struct mtk_composite cpu_muxes[] __initconst = {
+ MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
+};
+
+static const struct mtk_composite top_muxes[] = {
+ MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
+ 0x0040, 0, 3, 7, CLK_IS_CRITICAL),
+ MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
+ 0x0040, 8, 1, 15, CLK_IS_CRITICAL),
+ MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
+ ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
+ MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
+ 0x0040, 24, 3, 31),
+
+ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
+ 0x0050, 0, 2, 7),
+ MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
+ 0x0050, 8, 4, 15),
+ MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
+ 0x0050, 16, 3, 23),
+ MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
+ 0x0050, 24, 3, 31),
+ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
+ 0x0060, 0, 1, 7),
+
+ MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
+ 0x0060, 8, 3, 15),
+ MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,
+ 0x0060, 16, 2, 23),
+ MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
+ 0x0060, 24, 3, 31),
+
+ MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
+ 0x0070, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,
+ 0x0070, 8, 3, 15),
+ MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents,
+ 0x0070, 16, 1, 23),
+ MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
+ 0x0070, 24, 3, 31),
+
+ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
+ 0x0080, 0, 4, 7),
+ MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
+ 0x0080, 8, 2, 15),
+ MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
+ 0x0080, 16, 3, 23),
+ MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
+ 0x0080, 24, 2, 31),
+
+ MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
+ 0x0090, 0, 3, 7),
+ MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents,
+ 0x0090, 8, 2, 15),
+ MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
+ 0x0090, 16, 3, 23),
+
+ MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents,
+ 0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
+ MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
+ 0x00A0, 8, 3, 15),
+ MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents,
+ 0x00A0, 24, 2, 31),
+
+ MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
+ 0x00B0, 0, 3, 7),
+ MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
+ 0x00B0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
+ 0x00B0, 16, 3, 23),
+ MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents,
+ 0x00B0, 24, 3, 31),
+
+ MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel",
+ hdmirx_bist_parents, 0x00C0, 0, 3, 7),
+ MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
+ 0x00C0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents,
+ 0x00C0, 16, 2, 23),
+ MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents,
+ 0x00C0, 24, 3, 31),
+
+ MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents,
+ 0x00D0, 0, 2, 7),
+ MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents,
+ 0x00D0, 16, 2, 23),
+ MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents,
+ 0x00D0, 24, 3, 31),
+
+ MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents,
+ 0x00E0, 0, 1, 7),
+ MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
+ 0x00E0, 8, 3, 15),
+ MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents,
+ 0x00E0, 16, 4, 23),
+
+ MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
+ 0x00E0, 24, 3, 31),
+ MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
+ 0x00F0, 0, 3, 7),
+ MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents,
+ 0x00F0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents,
+ 0x00F0, 16, 1, 23),
+
+ MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents,
+ 0x0100, 0, 3),
+
+ MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents,
+ 0x012c, 0, 3),
+ MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents,
+ 0x012c, 3, 3),
+ MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents,
+ 0x012c, 6, 3),
+ MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents,
+ 0x012c, 15, 1, 23),
+ MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents,
+ 0x012c, 16, 1, 24),
+ MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents,
+ 0x012c, 17, 1, 25),
+ MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents,
+ 0x012c, 18, 1, 26),
+ MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents,
+ 0x012c, 19, 1, 27),
+ MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents,
+ 0x012c, 20, 1, 28),
+};
+
+static const struct mtk_clk_divider top_adj_divs[] = {
+ DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1",
+ 0x0120, 0, 8),
+ DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2",
+ 0x0120, 8, 8),
+ DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel",
+ 0x0120, 16, 8),
+ DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel",
+ 0x0120, 24, 8),
+ DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel",
+ 0x0124, 0, 8),
+ DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel",
+ 0x0124, 8, 8),
+ DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel",
+ 0x0124, 16, 8),
+ DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel",
+ 0x0124, 24, 8),
+ DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel",
+ 0x0128, 0, 8),
+ DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel",
+ 0x0128, 8, 8),
+};
+
+static const struct mtk_gate_regs top_aud_cg_regs = {
+ .sta_ofs = 0x012C,
+};
+
+#define GATE_TOP_AUD(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &top_aud_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div",
+ 21),
+ GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div",
+ 22),
+ GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div",
+ 23),
+ GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div",
+ 24),
+ GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div",
+ 25),
+ GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div",
+ 26),
+ GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div",
+ 27),
+ GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div",
+ 28),
+};
+
+static int mtk_topckgen_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ void __iomem *base;
+ struct device_node *node = pdev->dev.of_node;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
+
+ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ clk_data);
+
+ mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
+ clk_data);
+
+ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
+ base, &mt2701_clk_lock, clk_data);
+
+ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ base, &mt2701_clk_lock, clk_data);
+
+ mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct mtk_gate_regs infra_cg_regs = {
+ .set_ofs = 0x0040,
+ .clr_ofs = 0x0044,
+ .sta_ofs = 0x0048,
+};
+
+#define GATE_ICG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate infra_clks[] = {
+ GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
+ GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
+ GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
+ GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4),
+ GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5),
+ GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
+ GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
+ GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
+ GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
+ GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
+ GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
+ GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
+ GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
+ GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
+ GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
+ GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
+ GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
+ GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
+};
+
+static const struct mtk_fixed_factor infra_fixed_divs[] = {
+ FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
+};
+
+static struct clk_onecell_data *infra_clk_data;
+
+static void __init mtk_infrasys_init_early(struct device_node *node)
+{
+ int r, i;
+
+ if (!infra_clk_data) {
+ infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
+
+ for (i = 0; i < CLK_INFRA_NR; i++)
+ infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
+ }
+
+ mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
+ infra_clk_data);
+
+ mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+ infra_clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
+ mtk_infrasys_init_early);
+
+static int mtk_infrasys_init(struct platform_device *pdev)
+{
+ int r, i;
+ struct device_node *node = pdev->dev.of_node;
+
+ if (!infra_clk_data) {
+ infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
+ } else {
+ for (i = 0; i < CLK_INFRA_NR; i++) {
+ if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
+ infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
+ }
+ }
+
+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+ infra_clk_data);
+ mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
+ infra_clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
+ if (r)
+ return r;
+
+ mtk_register_reset_controller(node, 2, 0x30);
+
+ return 0;
+}
+
+static const struct mtk_gate_regs peri0_cg_regs = {
+ .set_ofs = 0x0008,
+ .clr_ofs = 0x0010,
+ .sta_ofs = 0x0018,
+};
+
+static const struct mtk_gate_regs peri1_cg_regs = {
+ .set_ofs = 0x000c,
+ .clr_ofs = 0x0014,
+ .sta_ofs = 0x001c,
+};
+
+#define GATE_PERI0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_PERI1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate peri_clks[] = {
+ GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
+ GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
+ GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
+ GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
+ GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
+ GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
+ GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
+ GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
+ GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
+ GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
+ GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
+ GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
+ GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
+ GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
+ GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
+ GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
+ GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
+ GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
+ GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
+ GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
+ GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
+ GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
+ GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
+ GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
+ GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
+ GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
+ GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
+ GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
+ GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
+ GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
+ GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
+ GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
+
+ GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11),
+ GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
+ GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
+ GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
+ GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
+ GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
+ GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
+ GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4),
+ GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3),
+ GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
+ GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
+ GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
+};
+
+static const char * const uart_ck_sel_parents[] = {
+ "clk26m",
+ "uart_sel",
+};
+
+static const struct mtk_composite peri_muxs[] = {
+ MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents,
+ 0x40c, 0, 1),
+ MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents,
+ 0x40c, 1, 1),
+ MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents,
+ 0x40c, 2, 1),
+ MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents,
+ 0x40c, 3, 1),
+};
+
+static int mtk_pericfg_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ void __iomem *base;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
+
+ mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+ clk_data);
+
+ mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
+ &mt2701_clk_lock, clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ return r;
+
+ mtk_register_reset_controller(node, 2, 0x0);
+
+ return 0;
+}
+
+#define MT8590_PLL_FMAX (2000 * MHZ)
+#define CON0_MT8590_RST_BAR BIT(27)
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .flags = _flags, \
+ .rst_bar_mask = CON0_MT8590_RST_BAR, \
+ .fmax = MT8590_PLL_FMAX, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,
+ PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
+ HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
+ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
+ HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
+ 21, 0x230, 4, 0x0, 0x234, 0),
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
+ 21, 0x240, 4, 0x0, 0x244, 0),
+ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
+ 21, 0x250, 4, 0x0, 0x254, 0),
+ PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
+ 31, 0x270, 4, 0x0, 0x274, 0),
+ PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
+ 31, 0x280, 4, 0x0, 0x284, 0),
+ PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
+ 31, 0x290, 4, 0x0, 0x294, 0),
+ PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
+ 31, 0x2a0, 4, 0x0, 0x2a4, 0),
+ PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
+ 31, 0x2b0, 4, 0x0, 0x2b4, 0),
+ PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
+ 31, 0x2c0, 4, 0x0, 0x2c4, 0),
+ PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
+ 21, 0x2d0, 4, 0x0, 0x2d4, 0),
+};
+
+static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
+ FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1),
+};
+
+static int mtk_apmixedsys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
+ if (!clk_data)
+ return -ENOMEM;
+
+ mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
+ clk_data);
+ mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt2701[] = {
+ {
+ .compatible = "mediatek,mt2701-topckgen",
+ .data = mtk_topckgen_init,
+ }, {
+ .compatible = "mediatek,mt2701-infracfg",
+ .data = mtk_infrasys_init,
+ }, {
+ .compatible = "mediatek,mt2701-pericfg",
+ .data = mtk_pericfg_init,
+ }, {
+ .compatible = "mediatek,mt2701-apmixedsys",
+ .data = mtk_apmixedsys_init,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt2701_probe(struct platform_device *pdev)
+{
+ int (*clk_init)(struct platform_device *);
+ int r;
+
+ clk_init = of_device_get_match_data(&pdev->dev);
+ if (!clk_init)
+ return -EINVAL;
+
+ r = clk_init(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt2701_drv = {
+ .probe = clk_mt2701_probe,
+ .driver = {
+ .name = "clk-mt2701",
+ .of_match_table = of_match_clk_mt2701,
+ },
+};
+
+static int __init clk_mt2701_init(void)
+{
+ return platform_driver_register(&clk_mt2701_drv);
+}
+
+arch_initcall(clk_mt2701_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-bdp.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-bdp.c
new file mode 100644
index 0000000..5fe4728
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-bdp.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2712-clk.h>
+
+static const struct mtk_gate_regs bdp_cg_regs = {
+ .set_ofs = 0x100,
+ .clr_ofs = 0x100,
+ .sta_ofs = 0x100,
+};
+
+#define GATE_BDP(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &bdp_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+static const struct mtk_gate bdp_clks[] = {
+ GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
+ GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
+ GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
+ GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
+ GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
+ GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
+ GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
+ GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
+ GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
+ GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
+ GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
+ GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
+ GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
+ GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
+ GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
+ GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
+ GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
+ GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
+ GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
+ GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
+ GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
+ GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
+ GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
+ GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
+ GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
+ GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
+ GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
+ GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
+};
+
+static int clk_mt2712_bdp_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
+
+ mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r != 0)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt2712_bdp[] = {
+ { .compatible = "mediatek,mt2712-bdpsys", },
+ {}
+};
+
+static struct platform_driver clk_mt2712_bdp_drv = {
+ .probe = clk_mt2712_bdp_probe,
+ .driver = {
+ .name = "clk-mt2712-bdp",
+ .of_match_table = of_match_clk_mt2712_bdp,
+ },
+};
+
+builtin_platform_driver(clk_mt2712_bdp_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-img.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-img.c
new file mode 100644
index 0000000..139ff55
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-img.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2712-clk.h>
+
+static const struct mtk_gate_regs img_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &img_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+static const struct mtk_gate img_clks[] = {
+ GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0),
+ GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3),
+ GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8),
+ GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9),
+ GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10),
+ GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11),
+};
+
+static int clk_mt2712_img_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
+
+ mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r != 0)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt2712_img[] = {
+ { .compatible = "mediatek,mt2712-imgsys", },
+ {}
+};
+
+static struct platform_driver clk_mt2712_img_drv = {
+ .probe = clk_mt2712_img_probe,
+ .driver = {
+ .name = "clk-mt2712-img",
+ .of_match_table = of_match_clk_mt2712_img,
+ },
+};
+
+builtin_platform_driver(clk_mt2712_img_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-jpgdec.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-jpgdec.c
new file mode 100644
index 0000000..c7d4aad
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-jpgdec.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2712-clk.h>
+
+static const struct mtk_gate_regs jpgdec_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_JPGDEC(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &jpgdec_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate jpgdec_clks[] = {
+ GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0),
+ GATE_JPGDEC(CLK_JPGDEC_JPGDEC, "jpgdec_jpgdec", "jpgdec_sel", 4),
+};
+
+static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_JPGDEC_NR_CLK);
+
+ mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r != 0)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt2712_jpgdec[] = {
+ { .compatible = "mediatek,mt2712-jpgdecsys", },
+ {}
+};
+
+static struct platform_driver clk_mt2712_jpgdec_drv = {
+ .probe = clk_mt2712_jpgdec_probe,
+ .driver = {
+ .name = "clk-mt2712-jpgdec",
+ .of_match_table = of_match_clk_mt2712_jpgdec,
+ },
+};
+
+builtin_platform_driver(clk_mt2712_jpgdec_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-mfg.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-mfg.c
new file mode 100644
index 0000000..570f72d
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-mfg.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2712-clk.h>
+
+static const struct mtk_gate_regs mfg_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_MFG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mfg_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate mfg_clks[] = {
+ GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
+};
+
+static int clk_mt2712_mfg_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
+
+ mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r != 0)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt2712_mfg[] = {
+ { .compatible = "mediatek,mt2712-mfgcfg", },
+ {}
+};
+
+static struct platform_driver clk_mt2712_mfg_drv = {
+ .probe = clk_mt2712_mfg_probe,
+ .driver = {
+ .name = "clk-mt2712-mfg",
+ .of_match_table = of_match_clk_mt2712_mfg,
+ },
+};
+
+builtin_platform_driver(clk_mt2712_mfg_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-mm.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-mm.c
new file mode 100644
index 0000000..7a5679b
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-mm.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2712-clk.h>
+
+static const struct mtk_gate_regs mm0_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mm1_cg_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs mm2_cg_regs = {
+ .set_ofs = 0x224,
+ .clr_ofs = 0x228,
+ .sta_ofs = 0x220,
+};
+
+#define GATE_MM0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_MM1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_MM2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate mm_clks[] = {
+ /* MM0 */
+ GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
+ GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
+ GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
+ GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
+ GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
+ GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
+ GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
+ GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
+ GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
+ GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
+ GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),
+ GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
+ GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
+ GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
+ GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
+ GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),
+ GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
+ GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
+ GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
+ GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
+ GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
+ GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
+ GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
+ GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
+ GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
+ GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
+ GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
+ GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
+ GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
+ GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
+ /* MM1 */
+ GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
+ GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1),
+ GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2),
+ GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3),
+ GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
+ GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5),
+ GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
+ GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7),
+ GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8),
+ GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
+ GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10),
+ GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
+ GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16),
+ GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17),
+ GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
+ GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21),
+ GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22),
+ GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23),
+ GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24),
+ GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25),
+ GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26),
+ GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27),
+ GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28),
+ GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29),
+ GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30),
+ GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31),
+ /* MM2 */
+ GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0),
+ GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1),
+ GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2),
+ GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3),
+ GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4),
+ GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5),
+ GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6),
+ GATE_MM2(CLK_MM_DISP_PWM2_MM, "mm_pwm2_mm", "mm_sel", 7),
+ GATE_MM2(CLK_MM_DISP_PWM2_26M, "mm_pwm2_26m", "pwm_sel", 8),
+};
+
+static int clk_mt2712_mm_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+
+ mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r != 0)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt2712_mm[] = {
+ { .compatible = "mediatek,mt2712-mmsys", },
+ {}
+};
+
+static struct platform_driver clk_mt2712_mm_drv = {
+ .probe = clk_mt2712_mm_probe,
+ .driver = {
+ .name = "clk-mt2712-mm",
+ .of_match_table = of_match_clk_mt2712_mm,
+ },
+};
+
+builtin_platform_driver(clk_mt2712_mm_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-vdec.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-vdec.c
new file mode 100644
index 0000000..55c64ee
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-vdec.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2712-clk.h>
+
+static const struct mtk_gate_regs vdec0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs vdec1_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0x8,
+};
+
+#define GATE_VDEC0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vdec0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VDEC1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vdec1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate vdec_clks[] = {
+ /* VDEC0 */
+ GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
+ /* VDEC1 */
+ GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
+ GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
+};
+
+static int clk_mt2712_vdec_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
+
+ mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r != 0)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt2712_vdec[] = {
+ { .compatible = "mediatek,mt2712-vdecsys", },
+ {}
+};
+
+static struct platform_driver clk_mt2712_vdec_drv = {
+ .probe = clk_mt2712_vdec_probe,
+ .driver = {
+ .name = "clk-mt2712-vdec",
+ .of_match_table = of_match_clk_mt2712_vdec,
+ },
+};
+
+builtin_platform_driver(clk_mt2712_vdec_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-venc.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-venc.c
new file mode 100644
index 0000000..ccbfe98
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712-venc.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2712-clk.h>
+
+static const struct mtk_gate_regs venc_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_VENC(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &venc_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate venc_clks[] = {
+ GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0),
+ GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
+ GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12),
+};
+
+static int clk_mt2712_venc_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
+
+ mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r != 0)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt2712_venc[] = {
+ { .compatible = "mediatek,mt2712-vencsys", },
+ {}
+};
+
+static struct platform_driver clk_mt2712_venc_drv = {
+ .probe = clk_mt2712_venc_probe,
+ .driver = {
+ .name = "clk-mt2712-venc",
+ .of_match_table = of_match_clk_mt2712_venc,
+ },
+};
+
+builtin_platform_driver(clk_mt2712_venc_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712.c
new file mode 100644
index 0000000..e36f4aa
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt2712.c
@@ -0,0 +1,1480 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2712-clk.h>
+
+static DEFINE_SPINLOCK(mt2712_clk_lock);
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000),
+ FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000),
+ FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000),
+ FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
+ FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000),
+ FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000),
+ FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000),
+ FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000),
+ FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768),
+ FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747),
+ FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000),
+ FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000),
+};
+
+static const struct mtk_fixed_factor top_early_divs[] = {
+ FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
+ 1),
+ FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
+ 2),
+};
+
+static const struct mtk_fixed_factor top_divs[] = {
+ FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
+ 1),
+ FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
+ 3),
+ FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
+ 1),
+ FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
+ 1),
+ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
+ 2),
+ FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
+ 4),
+ FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
+ 8),
+ FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
+ 16),
+ FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
+ 3),
+ FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
+ 2),
+ FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
+ 4),
+ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
+ 5),
+ FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
+ 2),
+ FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
+ 4),
+ FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
+ 7),
+ FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
+ 2),
+ FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
+ 1),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
+ 7),
+ FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
+ 26),
+ FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
+ 52),
+ FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
+ 104),
+ FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
+ 208),
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
+ 8),
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
+ 3),
+ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
+ 8),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
+ 5),
+ FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
+ 8),
+ FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
+ 1),
+ FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
+ 1),
+ FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
+ 1),
+ FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
+ 1),
+ FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
+ 1),
+ FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
+ 1),
+ FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
+ 1),
+ FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
+ 4),
+ FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
+ 8),
+ FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
+ 16),
+ FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
+ 1),
+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
+ 4),
+ FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
+ 8),
+ FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
+ 16),
+ FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
+ 1),
+ FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
+ 4),
+ FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
+ 8),
+ FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
+ 1),
+ FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
+ 4),
+ FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
+ 8),
+ FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
+ 1),
+ FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
+ 1),
+ FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
+ 1),
+ FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
+ 2),
+ FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
+ 1),
+ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
+ 1),
+ FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
+ 1),
+ FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
+ 1),
+ FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
+ 4),
+ FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
+ 8),
+ FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
+ 1),
+ FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
+ 2),
+ FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
+ 4),
+ FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
+ 1),
+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
+ 4),
+ FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
+ 1),
+ FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
+ 4),
+ FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
+ 4),
+ FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
+ 3),
+ FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,
+ 3),
+};
+
+static const char * const axi_parents[] = {
+ "clk26m",
+ "syspll1_d2",
+ "syspll_d5",
+ "syspll1_d4",
+ "univpll_d5",
+ "univpll2_d2",
+ "msdcpll2_ck"
+};
+
+static const char * const mem_parents[] = {
+ "clk26m",
+ "dmpll_ck"
+};
+
+static const char * const mm_parents[] = {
+ "clk26m",
+ "vencpll_ck",
+ "syspll_d3",
+ "syspll1_d2",
+ "syspll_d5",
+ "syspll1_d4",
+ "univpll1_d2",
+ "univpll2_d2"
+};
+
+static const char * const pwm_parents[] = {
+ "clk26m",
+ "univpll2_d4",
+ "univpll3_d2",
+ "univpll1_d4"
+};
+
+static const char * const vdec_parents[] = {
+ "clk26m",
+ "vcodecpll_ck",
+ "tvdpll_429m",
+ "univpll_d3",
+ "vencpll_ck",
+ "syspll_d3",
+ "univpll1_d2",
+ "mmpll_d2",
+ "syspll3_d2",
+ "tvdpll_ck"
+};
+
+static const char * const venc_parents[] = {
+ "clk26m",
+ "univpll1_d2",
+ "mmpll_d2",
+ "tvdpll_d2",
+ "syspll1_d2",
+ "univpll_d5",
+ "vcodecpll_d2",
+ "univpll2_d2",
+ "syspll3_d2"
+};
+
+static const char * const mfg_parents[] = {
+ "clk26m",
+ "mmpll_ck",
+ "univpll_d3",
+ "clk26m",
+ "clk26m",
+ "clk26m",
+ "clk26m",
+ "clk26m",
+ "clk26m",
+ "syspll_d3",
+ "syspll1_d2",
+ "syspll_d5",
+ "univpll_d3",
+ "univpll1_d2",
+ "univpll_d5",
+ "univpll2_d2"
+};
+
+static const char * const camtg_parents[] = {
+ "clk26m",
+ "univpll_d52",
+ "univpll_d208",
+ "univpll_d104",
+ "clk26m_d2",
+ "univpll_d26",
+ "univpll2_d8",
+ "syspll3_d4",
+ "syspll3_d2",
+ "univpll1_d4",
+ "univpll2_d2"
+};
+
+static const char * const uart_parents[] = {
+ "clk26m",
+ "univpll2_d8"
+};
+
+static const char * const spi_parents[] = {
+ "clk26m",
+ "univpll2_d4",
+ "univpll1_d4",
+ "univpll2_d2",
+ "univpll3_d2",
+ "univpll1_d8"
+};
+
+static const char * const usb20_parents[] = {
+ "clk26m",
+ "univpll1_d8",
+ "univpll3_d4"
+};
+
+static const char * const usb30_parents[] = {
+ "clk26m",
+ "univpll3_d2",
+ "univpll3_d4",
+ "univpll2_d4"
+};
+
+static const char * const msdc50_0_h_parents[] = {
+ "clk26m",
+ "syspll1_d2",
+ "syspll2_d2",
+ "syspll4_d2",
+ "univpll_d5",
+ "univpll1_d4"
+};
+
+static const char * const msdc50_0_parents[] = {
+ "clk26m",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "univpll1_d4",
+ "syspll2_d2",
+ "msdcpll_d4",
+ "vencpll_d2",
+ "univpll1_d2",
+ "msdcpll2_ck",
+ "msdcpll2_d2",
+ "msdcpll2_d4"
+};
+
+static const char * const msdc30_1_parents[] = {
+ "clk26m",
+ "univpll2_d2",
+ "msdcpll_d2",
+ "univpll1_d4",
+ "syspll2_d2",
+ "univpll_d7",
+ "vencpll_d2"
+};
+
+static const char * const msdc30_3_parents[] = {
+ "clk26m",
+ "msdcpll2_ck",
+ "msdcpll2_d2",
+ "univpll2_d2",
+ "msdcpll2_d4",
+ "univpll1_d4",
+ "syspll2_d2",
+ "syspll_d7",
+ "univpll_d7",
+ "vencpll_d2",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "msdcpll_d4"
+};
+
+static const char * const audio_parents[] = {
+ "clk26m",
+ "syspll3_d4",
+ "syspll4_d4",
+ "syspll1_d16"
+};
+
+static const char * const aud_intbus_parents[] = {
+ "clk26m",
+ "syspll1_d4",
+ "syspll4_d2",
+ "univpll3_d2",
+ "univpll2_d8",
+ "syspll3_d2",
+ "syspll3_d4"
+};
+
+static const char * const pmicspi_parents[] = {
+ "clk26m",
+ "syspll1_d8",
+ "syspll3_d4",
+ "syspll1_d16",
+ "univpll3_d4",
+ "univpll_d26",
+ "syspll3_d4"
+};
+
+static const char * const dpilvds1_parents[] = {
+ "clk26m",
+ "lvdspll2_ck",
+ "lvdspll2_d2",
+ "lvdspll2_d4",
+ "lvdspll2_d8",
+ "clkfpc"
+};
+
+static const char * const atb_parents[] = {
+ "clk26m",
+ "syspll1_d2",
+ "univpll_d5",
+ "syspll_d5"
+};
+
+static const char * const nr_parents[] = {
+ "clk26m",
+ "univpll1_d4",
+ "syspll2_d2",
+ "syspll1_d4",
+ "univpll1_d8",
+ "univpll3_d2",
+ "univpll2_d2",
+ "syspll_d5"
+};
+
+static const char * const nfi2x_parents[] = {
+ "clk26m",
+ "syspll4_d4",
+ "univpll3_d4",
+ "univpll1_d8",
+ "syspll2_d4",
+ "univpll3_d2",
+ "syspll_d7",
+ "syspll2_d2",
+ "univpll2_d2",
+ "syspll_d5",
+ "syspll1_d2"
+};
+
+static const char * const irda_parents[] = {
+ "clk26m",
+ "univpll2_d4",
+ "syspll2_d4",
+ "univpll2_d8"
+};
+
+static const char * const cci400_parents[] = {
+ "clk26m",
+ "vencpll_ck",
+ "armca35pll_600m",
+ "armca35pll_400m",
+ "univpll_d2",
+ "syspll_d2",
+ "msdcpll_ck",
+ "univpll_d3"
+};
+
+static const char * const aud_1_parents[] = {
+ "clk26m",
+ "apll1_ck",
+ "univpll2_d4",
+ "univpll2_d8"
+};
+
+static const char * const aud_2_parents[] = {
+ "clk26m",
+ "apll2_ck",
+ "univpll2_d4",
+ "univpll2_d8"
+};
+
+static const char * const mem_mfg_parents[] = {
+ "clk26m",
+ "mmpll_ck",
+ "univpll_d3"
+};
+
+static const char * const axi_mfg_parents[] = {
+ "clk26m",
+ "axi_sel",
+ "univpll_d5"
+};
+
+static const char * const scam_parents[] = {
+ "clk26m",
+ "syspll3_d2",
+ "univpll2_d4",
+ "syspll2_d4"
+};
+
+static const char * const nfiecc_parents[] = {
+ "clk26m",
+ "nfi2x_sel",
+ "syspll_d7",
+ "syspll2_d2",
+ "univpll2_d2",
+ "univpll_d5",
+ "syspll1_d2"
+};
+
+static const char * const pe2_mac_p0_parents[] = {
+ "clk26m",
+ "syspll1_d8",
+ "syspll4_d2",
+ "syspll2_d4",
+ "univpll2_d4",
+ "syspll3_d2"
+};
+
+static const char * const dpilvds_parents[] = {
+ "clk26m",
+ "lvdspll_ck",
+ "lvdspll_d2",
+ "lvdspll_d4",
+ "lvdspll_d8",
+ "clkfpc"
+};
+
+static const char * const hdcp_parents[] = {
+ "clk26m",
+ "syspll4_d2",
+ "syspll3_d4",
+ "univpll2_d4"
+};
+
+static const char * const hdcp_24m_parents[] = {
+ "clk26m",
+ "univpll_d26",
+ "univpll_d52",
+ "univpll2_d8"
+};
+
+static const char * const rtc_parents[] = {
+ "clkrtc_int",
+ "clkrtc_ext",
+ "clk26m",
+ "univpll3_d8"
+};
+
+static const char * const spinor_parents[] = {
+ "clk26m",
+ "clk26m_d2",
+ "syspll4_d4",
+ "univpll2_d8",
+ "univpll3_d4",
+ "syspll4_d2",
+ "syspll2_d4",
+ "univpll2_d4",
+ "etherpll_125m",
+ "syspll1_d4"
+};
+
+static const char * const apll_parents[] = {
+ "clk26m",
+ "apll1_ck",
+ "apll1_d2",
+ "apll1_d4",
+ "apll1_d8",
+ "apll1_d16",
+ "apll2_ck",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8",
+ "apll2_d16",
+ "clk26m",
+ "clk26m"
+};
+
+static const char * const a1sys_hp_parents[] = {
+ "clk26m",
+ "apll1_ck",
+ "apll1_d2",
+ "apll1_d4",
+ "apll1_d8",
+ "apll1_d3"
+};
+
+static const char * const a2sys_hp_parents[] = {
+ "clk26m",
+ "apll2_ck",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8",
+ "apll2_d3"
+};
+
+static const char * const asm_l_parents[] = {
+ "clk26m",
+ "univpll2_d4",
+ "univpll2_d2",
+ "syspll_d5"
+};
+
+static const char * const i2so1_parents[] = {
+ "clk26m",
+ "apll1_ck",
+ "apll2_ck"
+};
+
+static const char * const ether_125m_parents[] = {
+ "clk26m",
+ "etherpll_125m",
+ "univpll3_d2"
+};
+
+static const char * const ether_50m_parents[] = {
+ "clk26m",
+ "etherpll_50m",
+ "apll1_d3",
+ "univpll3_d4"
+};
+
+static const char * const jpgdec_parents[] = {
+ "clk26m",
+ "univpll_d3",
+ "tvdpll_429m",
+ "vencpll_ck",
+ "syspll_d3",
+ "vcodecpll_ck",
+ "univpll1_d2",
+ "armca35pll_400m",
+ "tvdpll_429m_d2",
+ "tvdpll_429m_d4"
+};
+
+static const char * const spislv_parents[] = {
+ "clk26m",
+ "univpll2_d4",
+ "univpll1_d4",
+ "univpll2_d2",
+ "univpll3_d2",
+ "univpll1_d8",
+ "univpll1_d2",
+ "univpll_d5"
+};
+
+static const char * const ether_parents[] = {
+ "clk26m",
+ "etherpll_50m",
+ "univpll_d26"
+};
+
+static const char * const di_parents[] = {
+ "clk26m",
+ "tvdpll_d2",
+ "tvdpll_d4",
+ "tvdpll_d8",
+ "vencpll_ck",
+ "vencpll_d2",
+ "cvbs",
+ "cvbs_d2"
+};
+
+static const char * const tvd_parents[] = {
+ "clk26m",
+ "cvbs_d2",
+ "univpll2_d8"
+};
+
+static const char * const i2c_parents[] = {
+ "clk26m",
+ "univpll_d26",
+ "univpll2_d4",
+ "univpll3_d2",
+ "univpll1_d4"
+};
+
+static const char * const msdc0p_aes_parents[] = {
+ "clk26m",
+ "syspll_d2",
+ "univpll_d3",
+ "vcodecpll_ck"
+};
+
+static const char * const cmsys_parents[] = {
+ "clk26m",
+ "univpll_d3",
+ "syspll_d3",
+ "syspll1_d2",
+ "syspll2_d2"
+};
+
+static const char * const gcpu_parents[] = {
+ "clk26m",
+ "syspll_d3",
+ "syspll1_d2",
+ "univpll1_d2",
+ "univpll_d5",
+ "univpll3_d2",
+ "univpll_d3"
+};
+
+static const char * const aud_apll1_parents[] = {
+ "apll1",
+ "clkaud_ext_i_1"
+};
+
+static const char * const aud_apll2_parents[] = {
+ "apll2",
+ "clkaud_ext_i_2"
+};
+
+static const char * const apll1_ref_parents[] = {
+ "clkaud_ext_i_2",
+ "clkaud_ext_i_1",
+ "clki2si0_mck_i",
+ "clki2si1_mck_i",
+ "clki2si2_mck_i",
+ "clktdmin_mclk_i",
+ "clki2si2_mck_i",
+ "clktdmin_mclk_i"
+};
+
+static const char * const audull_vtx_parents[] = {
+ "d2a_ulclk_6p5m",
+ "clkaud_ext_i_0"
+};
+
+static struct mtk_composite top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
+ 7, CLK_IS_CRITICAL),
+ MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
+ 15, CLK_IS_CRITICAL),
+ MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
+ mm_parents, 0x040, 24, 3, 31),
+ /* CLK_CFG_1 */
+ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
+ pwm_parents, 0x050, 0, 2, 7),
+ MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
+ vdec_parents, 0x050, 8, 4, 15),
+ MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
+ venc_parents, 0x050, 16, 4, 23),
+ MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
+ mfg_parents, 0x050, 24, 4, 31),
+ /* CLK_CFG_2 */
+ MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
+ camtg_parents, 0x060, 0, 4, 7),
+ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
+ uart_parents, 0x060, 8, 1, 15),
+ MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
+ spi_parents, 0x060, 16, 3, 23),
+ MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",
+ usb20_parents, 0x060, 24, 2, 31),
+ /* CLK_CFG_3 */
+ MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",
+ usb30_parents, 0x070, 0, 2, 7),
+ MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
+ msdc50_0_h_parents, 0x070, 8, 3, 15),
+ MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
+ msdc50_0_parents, 0x070, 16, 4, 23),
+ MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
+ msdc30_1_parents, 0x070, 24, 3, 31),
+ /* CLK_CFG_4 */
+ MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
+ msdc30_1_parents, 0x080, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",
+ msdc30_3_parents, 0x080, 8, 4, 15),
+ MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel",
+ audio_parents, 0x080, 16, 2, 23),
+ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
+ aud_intbus_parents, 0x080, 24, 3, 31),
+ /* CLK_CFG_5 */
+ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel",
+ pmicspi_parents, 0x090, 0, 3, 7),
+ MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel",
+ dpilvds1_parents, 0x090, 8, 3, 15),
+ MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
+ atb_parents, 0x090, 16, 2, 23),
+ MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
+ nr_parents, 0x090, 24, 3, 31),
+ /* CLK_CFG_6 */
+ MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",
+ nfi2x_parents, 0x0a0, 0, 4, 7),
+ MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel",
+ irda_parents, 0x0a0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
+ cci400_parents, 0x0a0, 16, 3, 23),
+ MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
+ aud_1_parents, 0x0a0, 24, 2, 31),
+ /* CLK_CFG_7 */
+ MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
+ aud_2_parents, 0x0b0, 0, 2, 7),
+ MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel",
+ mem_mfg_parents, 0x0b0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel",
+ axi_mfg_parents, 0x0b0, 16, 2, 23),
+ MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel",
+ scam_parents, 0x0b0, 24, 2, 31),
+ /* CLK_CFG_8 */
+ MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel",
+ nfiecc_parents, 0x0c0, 0, 3, 7),
+ MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
+ pe2_mac_p0_parents, 0x0c0, 8, 3, 15),
+ MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",
+ pe2_mac_p0_parents, 0x0c0, 16, 3, 23),
+ MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel",
+ dpilvds_parents, 0x0c0, 24, 3, 31),
+ /* CLK_CFG_9 */
+ MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel",
+ msdc50_0_h_parents, 0x0d0, 0, 3, 7),
+ MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",
+ hdcp_parents, 0x0d0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
+ hdcp_24m_parents, 0x0d0, 16, 2, 23),
+ MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2,
+ 31, CLK_IS_CRITICAL),
+ /* CLK_CFG_10 */
+ MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel",
+ spinor_parents, 0x500, 0, 4, 7),
+ MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",
+ apll_parents, 0x500, 8, 4, 15),
+ MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel",
+ apll_parents, 0x500, 16, 4, 23),
+ MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
+ a1sys_hp_parents, 0x500, 24, 3, 31),
+ /* CLK_CFG_11 */
+ MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel",
+ a2sys_hp_parents, 0x510, 0, 3, 7),
+ MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel",
+ asm_l_parents, 0x510, 8, 2, 15),
+ MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel",
+ asm_l_parents, 0x510, 16, 2, 23),
+ MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel",
+ asm_l_parents, 0x510, 24, 2, 31),
+ /* CLK_CFG_12 */
+ MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel",
+ i2so1_parents, 0x520, 0, 2, 7),
+ MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel",
+ i2so1_parents, 0x520, 8, 2, 15),
+ MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel",
+ i2so1_parents, 0x520, 16, 2, 23),
+ MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel",
+ i2so1_parents, 0x520, 24, 2, 31),
+ /* CLK_CFG_13 */
+ MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel",
+ i2so1_parents, 0x530, 0, 2, 7),
+ MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel",
+ i2so1_parents, 0x530, 8, 2, 15),
+ MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel",
+ i2so1_parents, 0x530, 16, 2, 23),
+ MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel",
+ i2so1_parents, 0x530, 24, 2, 31),
+ /* CLK_CFG_14 */
+ MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel",
+ ether_125m_parents, 0x540, 0, 2, 7),
+ MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel",
+ ether_50m_parents, 0x540, 8, 2, 15),
+ MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel",
+ jpgdec_parents, 0x540, 16, 4, 23),
+ MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
+ spislv_parents, 0x540, 24, 3, 31),
+ /* CLK_CFG_15 */
+ MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel",
+ ether_parents, 0x550, 0, 2, 7),
+ MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel",
+ camtg_parents, 0x550, 8, 4, 15),
+ MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
+ di_parents, 0x550, 16, 3, 23),
+ MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
+ tvd_parents, 0x550, 24, 2, 31),
+ /* CLK_CFG_16 */
+ MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel",
+ i2c_parents, 0x560, 0, 3, 7),
+ MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel",
+ pwm_parents, 0x560, 8, 2, 15),
+ MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",
+ msdc0p_aes_parents, 0x560, 16, 2, 23),
+ MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel",
+ cmsys_parents, 0x560, 24, 3, 31),
+ /* CLK_CFG_17 */
+ MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel",
+ gcpu_parents, 0x570, 0, 3, 7),
+ /* CLK_AUDDIV_4 */
+ MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel",
+ aud_apll1_parents, 0x134, 0, 1),
+ MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
+ aud_apll2_parents, 0x134, 1, 1),
+ MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
+ audull_vtx_parents, 0x134, 31, 1),
+ MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel",
+ apll1_ref_parents, 0x134, 4, 3),
+ MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel",
+ apll1_ref_parents, 0x134, 7, 3),
+};
+
+static const char * const mcu_mp0_parents[] = {
+ "clk26m",
+ "armca35pll_ck",
+ "f_mp0_pll1_ck",
+ "f_mp0_pll2_ck"
+};
+
+static const char * const mcu_mp2_parents[] = {
+ "clk26m",
+ "armca72pll_ck",
+ "f_big_pll1_ck",
+ "f_big_pll2_ck"
+};
+
+static const char * const mcu_bus_parents[] = {
+ "clk26m",
+ "cci400_sel",
+ "f_bus_pll1_ck",
+ "f_bus_pll2_ck"
+};
+
+static struct mtk_composite mcu_muxes[] = {
+ /* mp0_pll_divider_cfg */
+ MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
+ 9, 2, -1, CLK_IS_CRITICAL),
+ /* mp2_pll_divider_cfg */
+ MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8,
+ 9, 2, -1, CLK_IS_CRITICAL),
+ /* bus_pll_divider_cfg */
+ MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
+ 9, 2, -1, CLK_IS_CRITICAL),
+};
+
+static const struct mtk_clk_divider top_adj_divs[] = {
+ DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),
+ DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8),
+ DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8),
+ DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8),
+ DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),
+ DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8),
+ DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8),
+ DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x120,
+ .clr_ofs = 0x120,
+ .sta_ofs = 0x120,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x424,
+ .clr_ofs = 0x424,
+ .sta_ofs = 0x424,
+};
+
+#define GATE_TOP0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_TOP1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
+ /* TOP1 */
+ GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0),
+ GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1),
+ GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2),
+};
+
+static const struct mtk_gate_regs infra_cg_regs = {
+ .set_ofs = 0x40,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x48,
+};
+
+#define GATE_INFRA(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate infra_clks[] = {
+ GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
+ GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
+ GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
+ GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
+ GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24),
+ GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25),
+ GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26),
+};
+
+static const struct mtk_gate_regs peri0_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x10,
+ .sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs peri1_cg_regs = {
+ .set_ofs = 0xc,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x1c,
+};
+
+static const struct mtk_gate_regs peri2_cg_regs = {
+ .set_ofs = 0x42c,
+ .clr_ofs = 0x42c,
+ .sta_ofs = 0x42c,
+};
+
+#define GATE_PERI0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_PERI1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_PERI2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate peri_clks[] = {
+ /* PERI0 */
+ GATE_PERI0(CLK_PERI_NFI, "per_nfi",
+ "axi_sel", 0),
+ GATE_PERI0(CLK_PERI_THERM, "per_therm",
+ "axi_sel", 1),
+ GATE_PERI0(CLK_PERI_PWM0, "per_pwm0",
+ "pwm_sel", 2),
+ GATE_PERI0(CLK_PERI_PWM1, "per_pwm1",
+ "pwm_sel", 3),
+ GATE_PERI0(CLK_PERI_PWM2, "per_pwm2",
+ "pwm_sel", 4),
+ GATE_PERI0(CLK_PERI_PWM3, "per_pwm3",
+ "pwm_sel", 5),
+ GATE_PERI0(CLK_PERI_PWM4, "per_pwm4",
+ "pwm_sel", 6),
+ GATE_PERI0(CLK_PERI_PWM5, "per_pwm5",
+ "pwm_sel", 7),
+ GATE_PERI0(CLK_PERI_PWM6, "per_pwm6",
+ "pwm_sel", 8),
+ GATE_PERI0(CLK_PERI_PWM7, "per_pwm7",
+ "pwm_sel", 9),
+ GATE_PERI0(CLK_PERI_PWM, "per_pwm",
+ "pwm_sel", 10),
+ GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma",
+ "axi_sel", 13),
+ GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0",
+ "msdc50_0_sel", 14),
+ GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1",
+ "msdc30_1_sel", 15),
+ GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2",
+ "msdc30_2_sel", 16),
+ GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3",
+ "msdc30_3_sel", 17),
+ GATE_PERI0(CLK_PERI_UART0, "per_uart0",
+ "uart_sel", 20),
+ GATE_PERI0(CLK_PERI_UART1, "per_uart1",
+ "uart_sel", 21),
+ GATE_PERI0(CLK_PERI_UART2, "per_uart2",
+ "uart_sel", 22),
+ GATE_PERI0(CLK_PERI_UART3, "per_uart3",
+ "uart_sel", 23),
+ GATE_PERI0(CLK_PERI_I2C0, "per_i2c0",
+ "axi_sel", 24),
+ GATE_PERI0(CLK_PERI_I2C1, "per_i2c1",
+ "axi_sel", 25),
+ GATE_PERI0(CLK_PERI_I2C2, "per_i2c2",
+ "axi_sel", 26),
+ GATE_PERI0(CLK_PERI_I2C3, "per_i2c3",
+ "axi_sel", 27),
+ GATE_PERI0(CLK_PERI_I2C4, "per_i2c4",
+ "axi_sel", 28),
+ GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc",
+ "ltepll_fs26m", 29),
+ GATE_PERI0(CLK_PERI_SPI0, "per_spi0",
+ "spi_sel", 30),
+ /* PERI1 */
+ GATE_PERI1(CLK_PERI_SPI, "per_spi",
+ "spinor_sel", 1),
+ GATE_PERI1(CLK_PERI_I2C5, "per_i2c5",
+ "axi_sel", 3),
+ GATE_PERI1(CLK_PERI_SPI2, "per_spi2",
+ "spi_sel", 5),
+ GATE_PERI1(CLK_PERI_SPI3, "per_spi3",
+ "spi_sel", 6),
+ GATE_PERI1(CLK_PERI_SPI5, "per_spi5",
+ "spi_sel", 8),
+ GATE_PERI1(CLK_PERI_UART4, "per_uart4",
+ "uart_sel", 9),
+ GATE_PERI1(CLK_PERI_SFLASH, "per_sflash",
+ "uart_sel", 11),
+ GATE_PERI1(CLK_PERI_GMAC, "per_gmac",
+ "uart_sel", 12),
+ GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0",
+ "uart_sel", 14),
+ GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1",
+ "uart_sel", 15),
+ GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk",
+ "uart_sel", 16),
+ /* PERI2 */
+ GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en",
+ "msdc50_0_sel", 0),
+ GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en",
+ "msdc30_1_sel", 1),
+ GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en",
+ "msdc30_2_sel", 2),
+ GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en",
+ "msdc30_3_sel", 3),
+ GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h",
+ "msdc50_0_h_sel", 4),
+ GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h",
+ "msdc50_3_h_sel", 5),
+ GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q",
+ "axi_sel", 6),
+ GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q",
+ "mem_sel", 7),
+};
+
+#define MT2712_PLL_FMAX (3000UL * MHZ)
+
+#define CON0_MT2712_RST_BAR BIT(24)
+
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
+ _tuner_en_bit, _pcw_reg, _pcw_shift, \
+ _div_table) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .flags = _flags, \
+ .rst_bar_mask = CON0_MT2712_RST_BAR, \
+ .fmax = MT2712_PLL_FMAX, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .tuner_en_reg = _tuner_en_reg, \
+ .tuner_en_bit = _tuner_en_bit, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .div_table = _div_table, \
+ }
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
+ _tuner_en_bit, _pcw_reg, _pcw_shift) \
+ PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
+ _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \
+ _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
+ _pcw_shift, NULL)
+
+static const struct mtk_pll_div_table armca35pll_div_table[] = {
+ { .div = 0, .freq = MT2712_PLL_FMAX },
+ { .div = 1, .freq = 1202500000 },
+ { .div = 2, .freq = 500500000 },
+ { .div = 3, .freq = 315250000 },
+ { .div = 4, .freq = 157625000 },
+ { } /* sentinel */
+};
+
+static const struct mtk_pll_div_table armca72pll_div_table[] = {
+ { .div = 0, .freq = MT2712_PLL_FMAX },
+ { .div = 1, .freq = 994500000 },
+ { .div = 2, .freq = 520000000 },
+ { .div = 3, .freq = 315250000 },
+ { .div = 4, .freq = 157625000 },
+ { } /* sentinel */
+};
+
+static const struct mtk_pll_div_table mmpll_div_table[] = {
+ { .div = 0, .freq = MT2712_PLL_FMAX },
+ { .div = 1, .freq = 1001000000 },
+ { .div = 2, .freq = 601250000 },
+ { .div = 3, .freq = 250250000 },
+ { .div = 4, .freq = 125125000 },
+ { } /* sentinel */
+};
+
+static const struct mtk_pll_data plls[] = {
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
+ HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
+ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
+ HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
+ PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
+ 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
+ PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
+ 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
+ PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
+ 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
+ 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
+ PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
+ 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
+ PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
+ 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
+ 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
+ PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
+ 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
+ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
+ 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
+ PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
+ 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
+ mmpll_div_table),
+ PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
+ HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
+ armca35pll_div_table),
+ PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
+ 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
+ armca72pll_div_table),
+ PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
+ 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
+};
+
+static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r != 0)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static struct clk_onecell_data *top_clk_data;
+
+static void clk_mt2712_top_init_early(struct device_node *node)
+{
+ int r, i;
+
+ if (!top_clk_data) {
+ top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+ for (i = 0; i < CLK_TOP_NR_CLK; i++)
+ top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
+ }
+
+ mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
+ top_clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+
+CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
+ clk_mt2712_top_init_early);
+
+static int clk_mt2712_top_probe(struct platform_device *pdev)
+{
+ int r, i;
+ struct device_node *node = pdev->dev.of_node;
+ void __iomem *base;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base)) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return PTR_ERR(base);
+ }
+
+ if (!top_clk_data) {
+ top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+ } else {
+ for (i = 0; i < CLK_TOP_NR_CLK; i++) {
+ if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
+ top_clk_data->clks[i] = ERR_PTR(-ENOENT);
+ }
+ }
+
+ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ top_clk_data);
+ mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
+ top_clk_data);
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
+ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
+ &mt2712_clk_lock, top_clk_data);
+ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
+ &mt2712_clk_lock, top_clk_data);
+ mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+ top_clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
+
+ if (r != 0)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static int clk_mt2712_infra_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+
+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r != 0)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ mtk_register_reset_controller(node, 2, 0x30);
+
+ return r;
+}
+
+static int clk_mt2712_peri_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+ mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r != 0)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ mtk_register_reset_controller(node, 2, 0);
+
+ return r;
+}
+
+static int clk_mt2712_mcu_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+ void __iomem *base;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base)) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return PTR_ERR(base);
+ }
+
+ clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
+
+ mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
+ &mt2712_clk_lock, clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r != 0)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt2712[] = {
+ {
+ .compatible = "mediatek,mt2712-apmixedsys",
+ .data = clk_mt2712_apmixed_probe,
+ }, {
+ .compatible = "mediatek,mt2712-topckgen",
+ .data = clk_mt2712_top_probe,
+ }, {
+ .compatible = "mediatek,mt2712-infracfg",
+ .data = clk_mt2712_infra_probe,
+ }, {
+ .compatible = "mediatek,mt2712-pericfg",
+ .data = clk_mt2712_peri_probe,
+ }, {
+ .compatible = "mediatek,mt2712-mcucfg",
+ .data = clk_mt2712_mcu_probe,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt2712_probe(struct platform_device *pdev)
+{
+ int (*clk_probe)(struct platform_device *);
+ int r;
+
+ clk_probe = of_device_get_match_data(&pdev->dev);
+ if (!clk_probe)
+ return -EINVAL;
+
+ r = clk_probe(pdev);
+ if (r != 0)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt2712_drv = {
+ .probe = clk_mt2712_probe,
+ .driver = {
+ .name = "clk-mt2712",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_clk_mt2712,
+ },
+};
+
+static int __init clk_mt2712_init(void)
+{
+ return platform_driver_register(&clk_mt2712_drv);
+}
+
+arch_initcall(clk_mt2712_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-apu0.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-apu0.c
new file mode 100644
index 0000000..49739b1
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-apu0.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mt6779-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs apu0_cg_regs = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_APU0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &apu0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate apu0_clks[] = {
+ GATE_APU0(CLK_APU0_APU, "apu0_apu", "dsp1_sel", 0),
+ GATE_APU0(CLK_APU0_AXI_M, "apu0_axi", "dsp1_sel", 1),
+ GATE_APU0(CLK_APU0_JTAG, "apu0_jtag", "dsp1_sel", 2),
+};
+
+static const struct of_device_id of_match_clk_mt6779_apu0[] = {
+ { .compatible = "mediatek,mt6779-apu0", },
+ {}
+};
+
+static int clk_mt6779_apu0_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APU0_NR_CLK);
+
+ mtk_clk_register_gates(node, apu0_clks, ARRAY_SIZE(apu0_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static struct platform_driver clk_mt6779_apu0_drv = {
+ .probe = clk_mt6779_apu0_probe,
+ .driver = {
+ .name = "clk-mt6779-apu0",
+ .of_match_table = of_match_clk_mt6779_apu0,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_apu0_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-apu1.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-apu1.c
new file mode 100644
index 0000000..59372ea
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-apu1.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mt6779-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs apu1_cg_regs = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_APU1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &apu1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate apu1_clks[] = {
+ GATE_APU1(CLK_APU1_APU, "apu1_apu", "dsp2_sel", 0),
+ GATE_APU1(CLK_APU1_AXI_M, "apu1_axi", "dsp2_sel", 1),
+ GATE_APU1(CLK_APU1_JTAG, "apu1_jtag", "dsp2_sel", 2),
+};
+
+static const struct of_device_id of_match_clk_mt6779_apu1[] = {
+ { .compatible = "mediatek,mt6779-apu1", },
+ {}
+};
+
+static int clk_mt6779_apu1_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APU1_NR_CLK);
+
+ mtk_clk_register_gates(node, apu1_clks, ARRAY_SIZE(apu1_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static struct platform_driver clk_mt6779_apu1_drv = {
+ .probe = clk_mt6779_apu1_probe,
+ .driver = {
+ .name = "clk-mt6779-apu1",
+ .of_match_table = of_match_clk_mt6779_apu1,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_apu1_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-apuconn.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-apuconn.c
new file mode 100644
index 0000000..c62f937
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-apuconn.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mt6779-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs apuconn_cg_regs = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_APU_CONN(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &apuconn_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate apuconn_clks[] = {
+ GATE_APU_CONN(CLK_APU_CONN_APU, "apu_conn_apu", "dsp1_sel", 0),
+ GATE_APU_CONN(CLK_APU_CONN_AHB, "apu_conn_ahb", "dsp_sel", 1),
+ GATE_APU_CONN(CLK_APU_CONN_AXI, "apu_conn_axi", "dsp_sel", 2),
+ GATE_APU_CONN(CLK_APU_CONN_ISP, "apu_conn_isp", "dsp_sel", 3),
+ GATE_APU_CONN(CLK_APU_CONN_CAM_ADL, "apu_conn_cam_adl",
+ "dsp_sel", 4),
+ GATE_APU_CONN(CLK_APU_CONN_IMG_ADL, "apu_conn_img_adl",
+ "dsp_sel", 5),
+ GATE_APU_CONN(CLK_APU_CONN_EMI_26M, "apu_conn_emi_26m",
+ "dsp_sel", 6),
+ GATE_APU_CONN(CLK_APU_CONN_VPU_UDI, "apu_conn_vpu_udi",
+ "dsp_sel", 7),
+};
+
+static const struct of_device_id of_match_clk_mt6779_apuconn[] = {
+ { .compatible = "mediatek,mt6779-apu_conn", },
+ {}
+};
+
+static int clk_mt6779_apuconn_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APU_CONN_NR_CLK);
+
+ mtk_clk_register_gates(node, apuconn_clks, ARRAY_SIZE(apuconn_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static struct platform_driver clk_mt6779_apuconn_drv = {
+ .probe = clk_mt6779_apuconn_probe,
+ .driver = {
+ .name = "clk-mt6779-apu_conn",
+ .of_match_table = of_match_clk_mt6779_apuconn,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_apuconn_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-apuvcore.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-apuvcore.c
new file mode 100644
index 0000000..eaeb43d
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-apuvcore.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mt6779-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs apuvcore_cg_regs = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_APU_VCORE(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &apuvcore_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate apuvcore_clks[] = {
+ GATE_APU_VCORE(CLK_APU_VCORE_AHB, "apu_vcore_ahb", "ipu_if_sel", 0),
+ GATE_APU_VCORE(CLK_APU_VCORE_AXI, "apu_vcore_axi", "ipu_if_sel", 1),
+ GATE_APU_VCORE(CLK_APU_VCORE_ADL, "apu_vcore_adl", "ipu_if_sel", 2),
+ GATE_APU_VCORE(CLK_APU_VCORE_QOS, "apu_vcore_qos", "ipu_if_sel", 3),
+};
+
+static const struct of_device_id of_match_clk_mt6779_apuvcore[] = {
+ { .compatible = "mediatek,mt6779-apu_vcore", },
+ {}
+};
+
+static int clk_mt6779_apuvcore_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APU_VCORE_NR_CLK);
+
+ mtk_clk_register_gates(node, apuvcore_clks, ARRAY_SIZE(apuvcore_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static struct platform_driver clk_mt6779_apuvcore_drv = {
+ .probe = clk_mt6779_apuvcore_probe,
+ .driver = {
+ .name = "clk-mt6779-apu_vcore",
+ .of_match_table = of_match_clk_mt6779_apuvcore,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_apuvcore_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-aud.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-aud.c
new file mode 100644
index 0000000..6bbc58e
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-aud.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6779-clk.h>
+
+#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audio0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audio1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+
+
+static const struct mtk_gate_regs audio0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs audio1_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x4,
+};
+
+static const struct mtk_gate audio_clks[] = {
+ /* AUDIO0 */
+ GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel",
+ 2),
+ GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel",
+ 8),
+ GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel",
+ 9),
+ GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "aud_eng2_sel",
+ 18),
+ GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "aud_eng1_sel",
+ 19),
+ GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel",
+ 20),
+ GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel",
+ 24),
+ GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel",
+ 25),
+ GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "audio_sel",
+ 26),
+ GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel",
+ 27),
+ GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel",
+ 28),
+ /* AUDIO1: hf_faudio_ck/hf_faud_engen1_ck/hf_faud_engen2_ck */
+ GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk", "audio_sel",
+ 4),
+ GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk", "audio_sel",
+ 5),
+ GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk", "audio_sel",
+ 6),
+ GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk", "audio_sel",
+ 7),
+ GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk", "audio_sel",
+ 8),
+
+ GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s", "audio_sel",
+ 12),
+ GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1", "audio_sel",
+ 13),
+ GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2", "audio_sel",
+ 14),
+ GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel",
+ 15),
+ GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel",
+ 16),
+ GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "audio_h_sel",
+ 17),
+
+ GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc", "audio_sel",
+ 20),
+ GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
+ "audio_h_sel",
+ 21),
+ GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
+ 28),
+ GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "audio_sel",
+ 29),
+ GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "audio_sel",
+ 30),
+ GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "audio_h_sel",
+ 31),
+};
+
+static const struct of_device_id of_match_clk_mt6779_aud[] = {
+ { .compatible = "mediatek,mt6779-audio", },
+ {}
+};
+
+static int clk_mt6779_aud_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
+
+ mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static struct platform_driver clk_mt6779_aud_drv = {
+ .probe = clk_mt6779_aud_probe,
+ .driver = {
+ .name = "clk-mt6779-aud",
+ .of_match_table = of_match_clk_mt6779_aud,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_aud_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-cam.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-cam.c
new file mode 100644
index 0000000..99736ce
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-cam.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mt6779-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs cam_cg_regs = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_CAM(_id, _name, _parent, _shift) \
+ GATE_CAM_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_CAM_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cam_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ .flags = _flags, \
+ }
+
+static const struct mtk_gate cam_clks[] = {
+ GATE_CAM(CLK_CAM_LARB10, "camsys_larb10", "cam_sel", 0),
+ GATE_CAM(CLK_CAM_DFP_VAD, "camsys_dfp_vad", "cam_sel", 1),
+ GATE_CAM(CLK_CAM_LARB11, "camsys_larb11", "cam_sel", 2),
+ GATE_CAM(CLK_CAM_LARB9, "camsys_larb9", "cam_sel", 3),
+ GATE_CAM(CLK_CAM_CAM, "camsys_cam", "cam_sel", 6),
+ GATE_CAM(CLK_CAM_CAMTG, "camsys_camtg", "cam_sel", 7),
+ GATE_CAM(CLK_CAM_SENINF, "camsys_seninf", "cam_sel", 8),
+ GATE_CAM(CLK_CAM_CAMSV0, "camsys_camsv0", "cam_sel", 9),
+ GATE_CAM(CLK_CAM_CAMSV1, "camsys_camsv1", "cam_sel", 10),
+ GATE_CAM(CLK_CAM_CAMSV2, "camsys_camsv2", "cam_sel", 11),
+ GATE_CAM(CLK_CAM_CAMSV3, "camsys_camsv3", "cam_sel", 12),
+ GATE_CAM(CLK_CAM_CCU, "camsys_ccu", "cam_sel", 13),
+ GATE_CAM(CLK_CAM_FAKE_ENG, "camsys_fake_eng", "cam_sel", 14),
+};
+
+static const struct of_device_id of_match_clk_mt6779_cam[] = {
+ { .compatible = "mediatek,mt6779-camsys", },
+ {}
+};
+
+static int clk_mt6779_cam_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
+
+ mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static struct platform_driver clk_mt6779_cam_drv = {
+ .probe = clk_mt6779_cam_probe,
+ .driver = {
+ .name = "clk-mt6779-cam",
+ .of_match_table = of_match_clk_mt6779_cam,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_cam_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-img.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-img.c
new file mode 100644
index 0000000..60d55c4
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-img.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mt6779-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs img_cg_regs = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_IMG(_id, _name, _parent, _shift) \
+ GATE_IMG_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_IMG_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &img_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ .flags = _flags, \
+ }
+
+static const struct mtk_gate img_clks[] = {
+ GATE_IMG(CLK_IMG_LARB5, "imgsys_larb5", "img_sel", 0),
+ GATE_IMG(CLK_IMG_LARB6, "imgsys_larb6", "img_sel", 1),
+ GATE_IMG(CLK_IMG_DIP, "imgsys_dip", "img_sel", 2),
+ GATE_IMG(CLK_IMG_MFB, "imgsys_mfb", "img_sel", 6),
+ GATE_IMG(CLK_IMG_WPE_A, "imgsys_wpe_a", "img_sel", 7),
+};
+
+static const struct of_device_id of_match_clk_mt6779_img[] = {
+ { .compatible = "mediatek,mt6779-imgsys", },
+ {}
+};
+
+static int clk_mt6779_img_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
+
+ mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static struct platform_driver clk_mt6779_img_drv = {
+ .probe = clk_mt6779_img_probe,
+ .driver = {
+ .name = "clk-mt6779-img",
+ .of_match_table = of_match_clk_mt6779_img,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_img_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-ipe.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-ipe.c
new file mode 100644
index 0000000..dc84a6e
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-ipe.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mt6779-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs ipe_cg_regs = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_IPE(_id, _name, _parent, _shift) \
+ GATE_IPE_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_IPE_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ipe_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ .flags = _flags, \
+ }
+
+static const struct mtk_gate ipe_clks[] = {
+ GATE_IPE(CLK_IPE_LARB7, "ipe_larb7", "ipe_sel", 0),
+ GATE_IPE(CLK_IPE_LARB8, "ipe_larb8", "ipe_sel", 1),
+ GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
+ GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
+ GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
+ GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
+ GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
+};
+
+static const struct of_device_id of_match_clk_mt6779_ipe[] = {
+ { .compatible = "mediatek,mt6779-ipesys", },
+ {}
+};
+
+static int clk_mt6779_ipe_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_IPE_NR_CLK);
+
+ mtk_clk_register_gates(node, ipe_clks, ARRAY_SIZE(ipe_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static struct platform_driver clk_mt6779_ipe_drv = {
+ .probe = clk_mt6779_ipe_probe,
+ .driver = {
+ .name = "clk-mt6779-ipe",
+ .of_match_table = of_match_clk_mt6779_ipe,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_ipe_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-mdla.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-mdla.c
new file mode 100644
index 0000000..dd8eb37
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-mdla.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mt6779-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs apumdla_cg_regs = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_APU_MDLA(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &apumdla_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate apumdla_clks[] = {
+ GATE_APU_MDLA(CLK_APU_MDLA_B0, "mdla_b0", "dsp3_sel", 0),
+ GATE_APU_MDLA(CLK_APU_MDLA_B1, "mdla_b1", "dsp3_sel", 1),
+ GATE_APU_MDLA(CLK_APU_MDLA_B2, "mdla_b2", "dsp3_sel", 2),
+ GATE_APU_MDLA(CLK_APU_MDLA_B3, "mdla_b3", "dsp3_sel", 3),
+ GATE_APU_MDLA(CLK_APU_MDLA_B4, "mdla_b4", "dsp3_sel", 4),
+ GATE_APU_MDLA(CLK_APU_MDLA_B5, "mdla_b5", "dsp3_sel", 5),
+ GATE_APU_MDLA(CLK_APU_MDLA_B6, "mdla_b6", "dsp3_sel", 6),
+ GATE_APU_MDLA(CLK_APU_MDLA_B7, "mdla_b7", "dsp3_sel", 7),
+ GATE_APU_MDLA(CLK_APU_MDLA_B8, "mdla_b8", "dsp3_sel", 8),
+ GATE_APU_MDLA(CLK_APU_MDLA_B9, "mdla_b9", "dsp3_sel", 9),
+ GATE_APU_MDLA(CLK_APU_MDLA_B10, "mdla_b10", "dsp3_sel", 10),
+ GATE_APU_MDLA(CLK_APU_MDLA_B11, "mdla_b11", "dsp3_sel", 11),
+ GATE_APU_MDLA(CLK_APU_MDLA_B12, "mdla_b12", "dsp3_sel", 12),
+ GATE_APU_MDLA(CLK_APU_MDLA_APB, "mdla_apb", "dsp3_sel", 13),
+};
+
+static const struct of_device_id of_match_clk_mt6779_apumdla[] = {
+ { .compatible = "mediatek,mt6779-apu_mdla", },
+ {}
+};
+
+static int clk_mt6779_apumdla_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APU_MDLA_NR_CLK);
+
+ mtk_clk_register_gates(node, apumdla_clks, ARRAY_SIZE(apumdla_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static struct platform_driver clk_mt6779_apumdla_drv = {
+ .probe = clk_mt6779_apumdla_probe,
+ .driver = {
+ .name = "clk-mt6779-apu_mdla",
+ .of_match_table = of_match_clk_mt6779_apumdla,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_apumdla_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-mfg.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-mfg.c
new file mode 100644
index 0000000..f9e589e
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-mfg.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6779-clk.h>
+
+static const struct mtk_gate_regs mfg_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_MFG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mfg_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate mfg_clks[] = {
+ GATE_MFG(CLK_MFGCFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
+};
+
+static int clk_mt6779_mfg_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
+
+ mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt6779_mfg[] = {
+ { .compatible = "mediatek,mt6779-mfgcfg", },
+ {}
+};
+
+static struct platform_driver clk_mt6779_mfg_drv = {
+ .probe = clk_mt6779_mfg_probe,
+ .driver = {
+ .name = "clk-mt6779-mfg",
+ .of_match_table = of_match_clk_mt6779_mfg,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_mfg_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-mm.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-mm.c
new file mode 100644
index 0000000..e3da13b
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-mm.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mt6779-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs mm0_cg_regs = {
+ .set_ofs = 0x0104,
+ .clr_ofs = 0x0108,
+ .sta_ofs = 0x0100,
+};
+
+static const struct mtk_gate_regs mm1_cg_regs = {
+ .set_ofs = 0x0114,
+ .clr_ofs = 0x0118,
+ .sta_ofs = 0x0110,
+};
+
+#define GATE_MM0(_id, _name, _parent, _shift) \
+ GATE_MM0_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_MM0_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ .flags = _flags, \
+}
+
+#define GATE_MM1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+}
+
+static const struct mtk_gate mm_clks[] = {
+ GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
+ GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
+ GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
+ GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
+ GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
+
+ GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
+ GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
+ GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
+
+ GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
+ GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
+ GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
+ GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
+ GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
+ GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
+ GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
+ GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
+ GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
+ GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
+ GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 18),
+
+ GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
+ GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
+ GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
+ GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
+ GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
+ GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
+ GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
+ GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
+ GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
+ GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
+ GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
+ GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
+ GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
+ /* MM1 */
+ GATE_MM1(CLK_MM_DSI0_MM_CK, "mm_dsi0_mmck", "mm_sel", 0),
+ GATE_MM1(CLK_MM_DSI0_IF_CK, "mm_dsi0_ifck", "mm_sel", 1),
+ GATE_MM1(CLK_MM_DPI_MM_CK, "mm_dpi_mmck", "mm_sel", 2),
+ GATE_MM1(CLK_MM_DPI_IF_CK, "mm_dpi_ifck", "dpi0_sel", 3),
+ GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
+ GATE_MM1(CLK_MM_MDP_DL_RX_CK, "mm_mdp_dl_rxck", "mm_sel", 5),
+ GATE_MM1(CLK_MM_IPU_DL_RX_CK, "mm_ipu_dl_rxck", "mm_sel", 6),
+ GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
+ GATE_MM1(CLK_MM_MM_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
+ GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
+ GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
+ GATE_MM1(CLK_MM_MDP_HDR, "mm_mdp_hdr", "mm_sel", 11),
+ GATE_MM1(CLK_MM_DBI_MM_CK, "mm_dbi_mmck", "mm_sel", 12),
+ GATE_MM1(CLK_MM_DBI_IF_CK, "mm_dbi_ifck", "dpi0_sel", 13),
+
+ GATE_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_pm0", "mm_sel", 14),
+ GATE_MM1(CLK_MM_DISP_HRT_BW, "mm_disp_hrt_bw", "mm_sel", 15),
+ GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16),
+};
+
+static const struct of_device_id of_match_clk_mt6779_mm[] = {
+ { .compatible = "mediatek,mt6779-mmsys", },
+ {}
+};
+
+static int clk_mt6779_mm_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_MM_CONFIG_NR_CLK);
+
+ mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static struct platform_driver clk_mt6779_mm_drv = {
+ .probe = clk_mt6779_mm_probe,
+ .driver = {
+ .name = "clk-mt6779-mm",
+ .of_match_table = of_match_clk_mt6779_mm,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_mm_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-vdec.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-vdec.c
new file mode 100644
index 0000000..12e324d
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-vdec.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6779-clk.h>
+
+static const struct mtk_gate_regs vdec0_cg_regs = {
+ .set_ofs = 0x0000,
+ .clr_ofs = 0x0004,
+ .sta_ofs = 0x0000,
+};
+
+static const struct mtk_gate_regs vdec1_cg_regs = {
+ .set_ofs = 0x0008,
+ .clr_ofs = 0x000c,
+ .sta_ofs = 0x0008,
+};
+
+#define GATE_VDEC0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vdec0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+}
+
+#define GATE_VDEC1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vdec1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+}
+
+static const struct mtk_gate vdec_clks[] = {
+ GATE_VDEC0(CLK_VDEC_VDEC, "vdec_cken", "vdec_sel", 0),
+ GATE_VDEC1(CLK_VDEC_LARB1, "vdec_larb1_cken", "vdec_sel", 0),
+};
+
+static const struct of_device_id of_match_clk_mt6779_vdec[] = {
+ { .compatible = "mediatek,mt6779-vdecsys", },
+ {}
+};
+
+static int clk_mt6779_vdec_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_VDEC_GCON_NR_CLK);
+
+ mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static struct platform_driver clk_mt6779_vdec_drv = {
+ .probe = clk_mt6779_vdec_probe,
+ .driver = {
+ .name = "clk-mt6779-vdec",
+ .of_match_table = of_match_clk_mt6779_vdec,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_vdec_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-venc.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-venc.c
new file mode 100644
index 0000000..8d63b7a
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779-venc.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6779-clk.h>
+
+static const struct mtk_gate_regs venc_cg_regs = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_VENC(_id, _name, _parent, _shift) \
+ GATE_VENC_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_VENC_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &venc_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate venc_clks[] = {
+ GATE_VENC(CLK_VENC_GCON_LARB, "venc_larb", "venc_sel", 0),
+ GATE_VENC(CLK_VENC_GCON_VENC, "venc_venc", "venc_sel", 4),
+ GATE_VENC(CLK_VENC_GCON_JPGENC, "venc_jpgenc", "venc_sel", 8),
+ GATE_VENC(CLK_VENC_GCON_GALS, "venc_gals", "venc_sel", 28),
+};
+
+static const struct of_device_id of_match_clk_mt6779_venc[] = {
+ { .compatible = "mediatek,mt6779-vencsys", },
+ {}
+};
+
+static int clk_mt6779_venc_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_VENC_GCON_NR_CLK);
+
+ mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static struct platform_driver clk_mt6779_venc_drv = {
+ .probe = clk_mt6779_venc_probe,
+ .driver = {
+ .name = "clk-mt6779-venc",
+ .of_match_table = of_match_clk_mt6779_venc,
+ },
+};
+
+builtin_platform_driver(clk_mt6779_venc_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779.c
new file mode 100644
index 0000000..fbd0752
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6779.c
@@ -0,0 +1,1654 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Wendell Lin <wendell.lin@mediatek.com>
+ */
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6779-clk.h>
+
+static DEFINE_SPINLOCK(mt6779_clk_lock);
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
+};
+
+static const struct mtk_fixed_factor top_divs[] = {
+ FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1,
+ 2),
+ FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
+ 2),
+ FACTOR(CLK_TOP_MAINPLL_CK, "mainpll_ck", "mainpll", 1,
+ 1),
+ FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1,
+ 2),
+ FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1,
+ 4),
+ FACTOR(CLK_TOP_MAINPLL_D2_D8, "mainpll_d2_d8", "mainpll_d2", 1,
+ 8),
+ FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1,
+ 16),
+
+ FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1,
+ 3),
+ FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1,
+ 2),
+ FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1,
+ 4),
+ FACTOR(CLK_TOP_MAINPLL_D3_D8, "mainpll_d3_d8", "mainpll_d3", 1,
+ 8),
+
+ FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1,
+ 5),
+ FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1,
+ 2),
+ FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1,
+ 4),
+
+ FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1,
+ 7),
+ FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1,
+ 2),
+ FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1,
+ 4),
+
+ FACTOR(CLK_TOP_UNIVPLL_CK, "univpll", "univ2pll", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1,
+ 8),
+
+
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1,
+ 3),
+ FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1,
+ 8),
+ FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1,
+ 16),
+
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1,
+ 5),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1,
+ 8),
+
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1,
+ 7),
+
+ FACTOR(CLK_TOP_UNIVP_192M_CK, "univpll_192m_ck", "univ2pll", 1,
+ 13),
+ FACTOR(CLK_TOP_UNIVP_192M_D2, "univpll_192m_d2", "univpll_192m_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVP_192M_D4, "univpll_192m_d4", "univpll_192m_ck", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVP_192M_D8, "univpll_192m_d8", "univpll_192m_ck", 1,
+ 8),
+ FACTOR(CLK_TOP_UNIVP_192M_D16, "univpll_192m_d16", "univpll_192m_ck", 1,
+ 16),
+ FACTOR(CLK_TOP_UNIVP_192M_D32, "univpll_192m_d32", "univpll_192m_ck", 1,
+ 32),
+
+ FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1,
+ 1),
+ FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1,
+ 2),
+ FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1,
+ 4),
+ FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1,
+ 8),
+ FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1,
+ 1),
+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1,
+ 2),
+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1,
+ 4),
+ FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1,
+ 8),
+ FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1,
+ 1),
+ FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1,
+ 4),
+ FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1,
+ 8),
+ FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1,
+ 16),
+
+ FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1,
+ 1),
+ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1,
+ 4),
+ FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1,
+ 2),
+ FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1,
+ 4),
+ FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1,
+ 5),
+ FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1,
+ 2),
+ FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1,
+ 4),
+ FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1,
+ 6),
+ FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1,
+ 7),
+
+ FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1,
+ 1),
+ FACTOR(CLK_TOP_ADSPPLL_CK, "adsppll_ck", "adsppll", 1,
+ 1),
+ FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1,
+ 4),
+ FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1,
+ 5),
+ FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1,
+ 6),
+
+ FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1,
+ 1),
+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1,
+ 2),
+ FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1,
+ 4),
+ FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1,
+ 8),
+ FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1,
+ 16),
+ FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1,
+ 1),
+ FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1,
+ 2),
+ FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1,
+ 4),
+ FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1,
+ 8),
+ FACTOR(CLK_TOP_OSC_D10, "osc_d10", "osc", 1,
+ 10),
+ FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1,
+ 16),
+ FACTOR(CLK_TOP_AD_OSC2_CK, "ad_osc2_ck", "osc2", 1,
+ 1),
+ FACTOR(CLK_TOP_OSC2_D2, "osc2_d2", "osc2", 1,
+ 2),
+ FACTOR(CLK_TOP_OSC2_D3, "osc2_d3", "osc2", 1,
+ 3),
+
+ FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2_CK, "tvdpll_mainpll_d2_ck",
+ "tvdpll", 1, 1),
+
+ FACTOR(CLK_TOP_FMEM_466M_CK, "fmem_466m_ck", "fmem", 1,
+ 1),
+};
+
+static const char * const axi_parents[] = {
+ "clk26m",
+ "mainpll_d2_d4",
+ "mainpll_d7",
+ "osc_d4"
+};
+
+static const char * const mm_parents[] = {
+ "clk26m",
+ "tvdpll_mainpll_d2_ck",
+ "mmpll_d7",
+ "mmpll_d5_d2",
+ "mainpll_d2_d2",
+ "mainpll_d3_d2"
+};
+
+static const char * const scp_parents[] = {
+ "clk26m",
+ "univpll_d2_d8",
+ "mainpll_d2_d4",
+ "mainpll_d3",
+ "univpll_d3",
+ "ad_osc2_ck",
+ "osc2_d2",
+ "osc2_d3"
+};
+
+static const char * const img_parents[] = {
+ "clk26m",
+ "mainpll_d2",
+ "mainpll_d2",
+ "univpll_d3",
+ "mainpll_d3",
+ "mmpll_d5_d2",
+ "tvdpll_mainpll_d2_ck",
+ "mainpll_d5"
+};
+
+static const char * const ipe_parents[] = {
+ "clk26m",
+ "mainpll_d2",
+ "mmpll_d7",
+ "univpll_d3",
+ "mainpll_d3",
+ "mmpll_d5_d2",
+ "mainpll_d2_d2",
+ "mainpll_d5"
+};
+
+static const char * const dpe_parents[] = {
+ "clk26m",
+ "mainpll_d2",
+ "mmpll_d7",
+ "univpll_d3",
+ "mainpll_d3",
+ "mmpll_d5_d2",
+ "mainpll_d2_d2",
+ "mainpll_d5"
+};
+
+static const char * const cam_parents[] = {
+ "clk26m",
+ "mainpll_d2",
+ "mmpll_d6",
+ "mainpll_d3",
+ "mmpll_d7",
+ "univpll_d3",
+ "mmpll_d5_d2",
+ "adsppll_d5",
+ "tvdpll_mainpll_d2_ck",
+ "univpll_d3_d2"
+};
+
+static const char * const ccu_parents[] = {
+ "clk26m",
+ "mainpll_d2",
+ "mmpll_d6",
+ "mainpll_d3",
+ "mmpll_d7",
+ "univpll_d3",
+ "mmpll_d5_d2",
+ "mainpll_d2_d2",
+ "adsppll_d5",
+ "univpll_d3_d2"
+};
+
+static const char * const dsp_parents[] = {
+ "clk26m",
+ "univpll_d3_d8",
+ "univpll_d3_d4",
+ "mainpll_d2_d4",
+ "univpll_d3_d2",
+ "mainpll_d2_d2",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "univpll_d3",
+ "mmpll_d7",
+ "mmpll_d6",
+ "adsppll_d5",
+ "tvdpll_ck",
+ "tvdpll_mainpll_d2_ck",
+ "univpll_d2",
+ "adsppll_d4"
+};
+
+static const char * const dsp1_parents[] = {
+ "clk26m",
+ "univpll_d3_d8",
+ "univpll_d3_d4",
+ "mainpll_d2_d4",
+ "univpll_d3_d2",
+ "mainpll_d2_d2",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "univpll_d3",
+ "mmpll_d7",
+ "mmpll_d6",
+ "adsppll_d5",
+ "tvdpll_ck",
+ "tvdpll_mainpll_d2_ck",
+ "univpll_d2",
+ "adsppll_d4"
+};
+
+static const char * const dsp2_parents[] = {
+ "clk26m",
+ "univpll_d3_d8",
+ "univpll_d3_d4",
+ "mainpll_d2_d4",
+ "univpll_d3_d2",
+ "mainpll_d2_d2",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "univpll_d3",
+ "mmpll_d7",
+ "mmpll_d6",
+ "adsppll_d5",
+ "tvdpll_ck",
+ "tvdpll_mainpll_d2_ck",
+ "univpll_d2",
+ "adsppll_d4"
+};
+
+static const char * const dsp3_parents[] = {
+ "clk26m",
+ "univpll_d3_d8",
+ "mainpll_d2_d4",
+ "univpll_d3_d2",
+ "mainpll_d2_d2",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "univpll_d3",
+ "mmpll_d7",
+ "mmpll_d6",
+ "mainpll_d2",
+ "tvdpll_ck",
+ "tvdpll_mainpll_d2_ck",
+ "univpll_d2",
+ "adsppll_d4",
+ "mmpll_d4"
+};
+
+static const char * const ipu_if_parents[] = {
+ "clk26m",
+ "univpll_d3_d8",
+ "univpll_d3_d4",
+ "mainpll_d2_d4",
+ "univpll_d3_d2",
+ "mainpll_d2_d2",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "univpll_d3",
+ "mmpll_d7",
+ "mmpll_d6",
+ "adsppll_d5",
+ "tvdpll_ck",
+ "tvdpll_mainpll_d2_ck",
+ "univpll_d2",
+ "adsppll_d4"
+};
+
+static const char * const mfg_parents[] = {
+ "clk26m",
+ "mfgpll_ck",
+ "univpll_d3",
+ "mainpll_d5"
+};
+
+static const char * const f52m_mfg_parents[] = {
+ "clk26m",
+ "univpll_d3_d2",
+ "univpll_d3_d4",
+ "univpll_d3_d8"
+};
+
+static const char * const camtg_parents[] = {
+ "clk26m",
+ "univpll_192m_d8",
+ "univpll_d3_d8",
+ "univpll_192m_d4",
+ "univpll_d3_d16",
+ "csw_f26m_ck_d2",
+ "univpll_192m_d16",
+ "univpll_192m_d32"
+};
+
+static const char * const camtg2_parents[] = {
+ "clk26m",
+ "univpll_192m_d8",
+ "univpll_d3_d8",
+ "univpll_192m_d4",
+ "univpll_d3_d16",
+ "csw_f26m_ck_d2",
+ "univpll_192m_d16",
+ "univpll_192m_d32"
+};
+
+static const char * const camtg3_parents[] = {
+ "clk26m",
+ "univpll_192m_d8",
+ "univpll_d3_d8",
+ "univpll_192m_d4",
+ "univpll_d3_d16",
+ "csw_f26m_ck_d2",
+ "univpll_192m_d16",
+ "univpll_192m_d32"
+};
+
+static const char * const camtg4_parents[] = {
+ "clk26m",
+ "univpll_192m_d8",
+ "univpll_d3_d8",
+ "univpll_192m_d4",
+ "univpll_d3_d16",
+ "csw_f26m_ck_d2",
+ "univpll_192m_d16",
+ "univpll_192m_d32"
+};
+
+static const char * const uart_parents[] = {
+ "clk26m",
+ "univpll_d3_d8"
+};
+
+static const char * const spi_parents[] = {
+ "clk26m",
+ "mainpll_d5_d2",
+ "mainpll_d3_d4",
+ "msdcpll_d4"
+};
+
+static const char * const msdc50_hclk_parents[] = {
+ "clk26m",
+ "mainpll_d2_d2",
+ "mainpll_d3_d2"
+};
+
+static const char * const msdc50_0_parents[] = {
+ "clk26m",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "univpll_d2_d4",
+ "mainpll_d3_d2",
+ "univpll_d2_d2"
+};
+
+static const char * const msdc30_1_parents[] = {
+ "clk26m",
+ "univpll_d3_d2",
+ "mainpll_d3_d2",
+ "mainpll_d7",
+ "msdcpll_d2"
+};
+
+static const char * const audio_parents[] = {
+ "clk26m",
+ "mainpll_d5_d4",
+ "mainpll_d7_d4",
+ "mainpll_d2_d16"
+};
+
+static const char * const aud_intbus_parents[] = {
+ "clk26m",
+ "mainpll_d2_d4",
+ "mainpll_d7_d2"
+};
+
+
+static const char * const fpwrap_ulposc_parents[] = {
+ "osc_d10",
+ "clk26m",
+ "osc_d4",
+ "osc_d8",
+ "osc_d16"
+};
+
+static const char * const atb_parents[] = {
+ "clk26m",
+ "mainpll_d2_d2",
+ "mainpll_d5"
+};
+
+static const char * const sspm_parents[] = {
+ "clk26m",
+ "univpll_d2_d4",
+ "mainpll_d2_d2",
+ "univpll_d2_d2",
+ "mainpll_d3"
+};
+
+static const char * const dpi0_parents[] = {
+ "clk26m",
+ "tvdpll_d2",
+ "tvdpll_d4",
+ "tvdpll_d8",
+ "tvdpll_d16"
+};
+
+static const char * const scam_parents[] = {
+ "clk26m",
+ "mainpll_d5_d2"
+};
+
+static const char * const disppwm_parents[] = {
+ "clk26m",
+ "univpll_d3_d4",
+ "osc_d2",
+ "osc_d4",
+ "osc_d16"
+};
+
+static const char * const usb_top_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d3_d4",
+ "univpll_d5_d2"
+};
+
+
+static const char * const ssusb_top_xhci_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d3_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const spm_parents[] = {
+ "clk26m",
+ "osc_d8",
+ "mainpll_d2_d8"
+};
+
+static const char * const i2c_parents[] = {
+ "clk26m",
+ "mainpll_d2_d8",
+ "univpll_d5_d2"
+};
+
+static const char * const seninf_parents[] = {
+ "clk26m",
+ "univpll_d7",
+ "univpll_d3_d2",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "mmpll_d4_d2",
+ "mmpll_d7",
+ "mmpll_d6"
+};
+
+static const char * const seninf1_parents[] = {
+ "clk26m",
+ "univpll_d7",
+ "univpll_d3_d2",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "mmpll_d4_d2",
+ "mmpll_d7",
+ "mmpll_d6"
+};
+
+static const char * const seninf2_parents[] = {
+ "clk26m",
+ "univpll_d7",
+ "univpll_d3_d2",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "mmpll_d4_d2",
+ "mmpll_d7",
+ "mmpll_d6"
+};
+
+static const char * const dxcc_parents[] = {
+ "clk26m",
+ "mainpll_d2_d2",
+ "mainpll_d2_d4",
+ "mainpll_d2_d8"
+};
+
+static const char * const aud_engen1_parents[] = {
+ "clk26m",
+ "apll1_d2",
+ "apll1_d4",
+ "apll1_d8"
+};
+
+static const char * const aud_engen2_parents[] = {
+ "clk26m",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8"
+};
+
+static const char * const faes_ufsfde_parents[] = {
+ "clk26m",
+ "mainpll_d2",
+ "mainpll_d2_d2",
+ "mainpll_d3",
+ "mainpll_d2_d4",
+ "univpll_d3"
+};
+
+static const char * const fufs_parents[] = {
+ "clk26m",
+ "mainpll_d2_d4",
+ "mainpll_d2_d8",
+ "mainpll_d2_d16"
+};
+
+static const char * const aud_1_parents[] = {
+ "clk26m",
+ "apll1_ck"
+};
+
+static const char * const aud_2_parents[] = {
+ "clk26m",
+ "apll2_ck"
+};
+
+static const char * const adsp_parents[] = {
+ "clk26m",
+ "mainpll_d3",
+ "univpll_d2_d4",
+ "univpll_d2",
+ "mmpll_d4",
+ "adsppll_d4",
+ "adsppll_d6"
+};
+
+static const char * const dpmaif_parents[] = {
+ "clk26m",
+ "univpll_d2_d4",
+ "mainpll_d3",
+ "mainpll_d2_d2",
+ "univpll_d2_d2",
+ "univpll_d3"
+};
+
+static const char * const venc_parents[] = {
+ "clk26m",
+ "mmpll_d7",
+ "mainpll_d3",
+ "univpll_d2_d2",
+ "mainpll_d2_d2",
+ "univpll_d3",
+ "mmpll_d6",
+ "mainpll_d5",
+ "mainpll_d3_d2",
+ "mmpll_d4_d2",
+ "univpll_d2_d4",
+ "mmpll_d5",
+ "univpll_192m_d2"
+
+};
+
+static const char * const vdec_parents[] = {
+ "clk26m",
+ "univpll_d2_d4",
+ "mainpll_d3",
+ "univpll_d2_d2",
+ "mainpll_d2_d2",
+ "univpll_d3",
+ "univpll_d5",
+ "univpll_d5_d2",
+ "mainpll_d2",
+ "univpll_d2",
+ "univpll_192m_d2"
+};
+
+static const char * const camtm_parents[] = {
+ "clk26m",
+ "univpll_d7",
+ "univpll_d3_d2",
+ "univpll_d2_d2"
+};
+
+static const char * const pwm_parents[] = {
+ "clk26m",
+ "univpll_d2_d8"
+};
+
+static const char * const audio_h_parents[] = {
+ "clk26m",
+ "univpll_d7",
+ "apll1_ck",
+ "apll2_ck"
+};
+
+static const char * const camtg5_parents[] = {
+ "clk26m",
+ "univpll_192m_d8",
+ "univpll_d3_d8",
+ "univpll_192m_d4",
+ "univpll_d3_d16",
+ "csw_f26m_ck_d2",
+ "univpll_192m_d16",
+ "univpll_192m_d32"
+};
+
+static const struct mtk_mux top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents,
+ 0x20, 0x24, 0x28,
+ 0, 2, 7,
+ 0x004, 0, CLK_IS_CRITICAL),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
+ 0x20, 0x24, 0x28,
+ 8, 3, 15,
+ 0x004, 1),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
+ 0x20, 0x24, 0x28,
+ 16, 3, 23,
+ 0x004, 2),
+
+ /* CLK_CFG_1 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
+ 0x30, 0x34, 0x38,
+ 0, 3, 7,
+ 0x004, 4),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
+ 0x30, 0x34, 0x38,
+ 8, 3, 15,
+ 0x004, 5),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
+ 0x30, 0x34, 0x38,
+ 16, 3, 23,
+ 0x004, 6),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
+ 0x30, 0x34, 0x38,
+ 24, 4, 31,
+ 0x004, 7),
+
+ /* CLK_CFG_2 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
+ 0x40, 0x44, 0x48,
+ 0, 4, 7,
+ 0x004, 8),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
+ 0x40, 0x44, 0x48,
+ 8, 4, 15,
+ 0x004, 9),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
+ 0x40, 0x44, 0x48,
+ 16, 4, 23,
+ 0x004, 10),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents,
+ 0x40, 0x44, 0x48,
+ 24, 4, 31,
+ 0x004, 11),
+
+ /* CLK_CFG_3 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "dsp3_sel", dsp3_parents,
+ 0x50, 0x54, 0x58,
+ 0, 4, 7,
+ 0x004, 12),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "ipu_if_sel", ipu_if_parents,
+ 0x50, 0x54, 0x58,
+ 8, 4, 15,
+ 0x004, 13),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "mfg_sel", mfg_parents,
+ 0x50, 0x54, 0x58,
+ 16, 2, 23,
+ 0x004, 14),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel",
+ f52m_mfg_parents,
+ 0x50, 0x54, 0x58,
+ 24, 2, 31,
+ 0x004, 15),
+
+ /* CLK_CFG_4 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "camtg_sel", camtg_parents,
+ 0x60, 0x64, 0x68,
+ 0, 3, 7,
+ 0x004, 16),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "camtg2_sel", camtg2_parents,
+ 0x60, 0x64, 0x68,
+ 8, 3, 15,
+ 0x004, 17),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "camtg3_sel", camtg3_parents,
+ 0x60, 0x64, 0x68,
+ 16, 3, 23,
+ 0x004, 18),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "camtg4_sel", camtg4_parents,
+ 0x60, 0x64, 0x68,
+ 24, 3, 31,
+ 0x004, 19),
+
+ /* CLK_CFG_5 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
+ 0x70, 0x74, 0x78,
+ 0, 1, 7,
+ 0x004, 20),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
+ 0x70, 0x74, 0x78,
+ 8, 2, 15,
+ 0x004, 21),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
+ msdc50_hclk_parents,
+ 0x70, 0x74, 0x78,
+ 16, 2, 23,
+ 0x004, 22),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",
+ msdc50_0_parents,
+ 0x70, 0x74, 0x78,
+ 24, 3, 31,
+ 0x004, 23),
+
+ /* CLK_CFG_6 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",
+ msdc30_1_parents,
+ 0x80, 0x84, 0x88,
+ 0, 3, 7,
+ 0x004, 24),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
+ 0x80, 0x84, 0x88,
+ 8, 2, 15,
+ 0x004, 25),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
+ aud_intbus_parents,
+ 0x80, 0x84, 0x88,
+ 16, 2, 23,
+ 0x004, 26),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
+ fpwrap_ulposc_parents,
+ 0x80, 0x84, 0x88,
+ 24, 3, 31,
+ 0x004, 27),
+
+ /* CLK_CFG_7 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "atb_sel", atb_parents,
+ 0x90, 0x94, 0x98,
+ 0, 2, 7,
+ 0x004, 28),
+
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents,
+ 0x90, 0x94, 0x98,
+ 8, 3, 15,
+ 0x004, 29, CLK_IS_CRITICAL),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents,
+ 0x90, 0x94, 0x98,
+ 16, 3, 23,
+ 0x004, 30),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents,
+ 0x90, 0x94, 0x98,
+ 24, 1, 31,
+ 0x004, 0),
+
+ /* CLK_CFG_8 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel",
+ disppwm_parents,
+ 0xa0, 0xa4, 0xa8,
+ 0, 3, 7,
+ 0x008, 1),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel",
+ usb_top_parents,
+ 0xa0, 0xa4, 0xa8,
+ 8, 2, 15,
+ 0x008, 2),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
+ ssusb_top_xhci_parents,
+ 0xa0, 0xa4, 0xa8,
+ 16, 2, 23,
+ 0x008, 3),
+
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents,
+ 0xa0, 0xa4, 0xa8,
+ 24, 2, 31,
+ 0x008, 4, CLK_IS_CRITICAL),
+
+ /* CLK_CFG_9 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents,
+ 0xb0, 0xb4, 0xb8,
+ 0, 2, 7,
+ 0x008, 5),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "seninf_sel", seninf_parents,
+ 0xb0, 0xb4, 0xb8,
+ 8, 2, 15,
+ 0x008, 6),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel",
+ seninf1_parents,
+ 0xb0, 0xb4, 0xb8,
+ 16, 2, 23,
+ 0x008, 7),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel",
+ seninf2_parents,
+ 0xb0, 0xb4, 0xb8,
+ 24, 2, 31,
+ 0x008, 8),
+
+ /* CLK_CFG_10 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents,
+ 0xc0, 0xc4, 0xc8,
+ 0, 2, 7,
+ 0x008, 9),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel",
+ aud_engen1_parents,
+ 0xc0, 0xc4, 0xc8,
+ 8, 2, 15,
+ 0x008, 10),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel",
+ aud_engen2_parents,
+ 0xc0, 0xc4, 0xc8,
+ 16, 2, 23,
+ 0x008, 11),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_FAES_UFSFDE, "faes_ufsfde_sel",
+ faes_ufsfde_parents,
+ 0xc0, 0xc4, 0xc8,
+ 24, 3, 31,
+ 0x008, 12),
+
+ /* CLK_CFG_11 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_FUFS, "fufs_sel", fufs_parents,
+ 0xd0, 0xd4, 0xd8,
+ 0, 2, 7,
+ 0x008, 13),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents,
+ 0xd0, 0xd4, 0xd8,
+ 8, 1, 15,
+ 0x008, 14),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents,
+ 0xd0, 0xd4, 0xd8,
+ 16, 1, 23,
+ 0x008, 15),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "adsp_sel", adsp_parents,
+ 0xd0, 0xd4, 0xd8,
+ 24, 3, 31,
+ 0x008, 16),
+
+ /* CLK_CFG_12 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "dpmaif_sel", dpmaif_parents,
+ 0xe0, 0xe4, 0xe8,
+ 0, 3, 7,
+ 0x008, 17),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "venc_sel", venc_parents,
+ 0xe0, 0xe4, 0xe8,
+ 8, 4, 15,
+ 0x008, 18),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "vdec_sel", vdec_parents,
+ 0xe0, 0xe4, 0xe8,
+ 16, 4, 23,
+ 0x008, 19),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "camtm_sel", camtm_parents,
+ 0xe0, 0xe4, 0xe8,
+ 24, 2, 31,
+ 0x004, 20),
+
+ /* CLK_CFG_13 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents,
+ 0xf0, 0xf4, 0xf8,
+ 0, 1, 7,
+ 0x008, 21),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_H, "audio_h_sel",
+ audio_h_parents,
+ 0xf0, 0xf4, 0xf8,
+ 8, 2, 15,
+ 0x008, 22),
+
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "camtg5_sel", camtg5_parents,
+ 0xf0, 0xf4, 0xf8,
+ 24, 3, 31,
+ 0x008, 24),
+};
+
+static const char * const i2s0_m_ck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const i2s1_m_ck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const i2s2_m_ck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const i2s3_m_ck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const i2s4_m_ck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const i2s5_m_ck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const struct mtk_composite top_aud_muxes[] = {
+ MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents,
+ 0x320, 8, 1),
+ MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents,
+ 0x320, 9, 1),
+ MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents,
+ 0x320, 10, 1),
+ MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents,
+ 0x320, 11, 1),
+ MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents,
+ 0x320, 12, 1),
+ MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents,
+ 0x328, 20, 1),
+};
+
+static struct mtk_composite top_aud_divs[] = {
+ DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
+ 0x320, 2, 0x324, 8, 0),
+ DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
+ 0x320, 3, 0x324, 8, 8),
+ DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel",
+ 0x320, 4, 0x324, 8, 16),
+ DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel",
+ 0x320, 5, 0x324, 8, 24),
+ DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
+ 0x320, 6, 0x328, 8, 0),
+ DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
+ 0x320, 7, 0x328, 8, 8),
+ DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
+ 0x328, 16, 0x328, 4, 28),
+};
+
+static const struct mtk_gate_regs infra0_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infra1_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infra2_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infra3_cg_regs = {
+ .set_ofs = 0xc0,
+ .clr_ofs = 0xc4,
+ .sta_ofs = 0xc8,
+};
+
+#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \
+ GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+#define GATE_INFRA0(_id, _name, _parent, _shift) \
+ GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, _flags)
+
+#define GATE_INFRA1(_id, _name, _parent, _shift) \
+ GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \
+ GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+#define GATE_INFRA2(_id, _name, _parent, _shift) \
+ GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \
+ GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+#define GATE_INFRA3(_id, _name, _parent, _shift) \
+ GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
+
+static const struct mtk_gate infra_clks[] = {
+
+ /* INFRA0 */
+ GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
+ "axi_sel", 0),
+ GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
+ "axi_sel", 1),
+ GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
+ "axi_sel", 2),
+ GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
+ "axi_sel", 3),
+ GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
+ "f_f26m_ck", 5),
+ GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
+ "axi_sel", 6),
+ GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
+ "axi_sel", 8),
+ GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
+ "axi_sel", 9),
+
+ GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
+ "axi_sel", 10),
+ GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
+ "i2c_sel", 11),
+ GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
+ "i2c_sel", 12),
+ GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
+ "i2c_sel", 13),
+ GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
+ "i2c_sel", 14),
+
+ GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
+ "pwm_sel", 15),
+ GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
+ "pwm_sel", 16),
+ GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
+ "pwm_sel", 17),
+ GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
+ "pwm_sel", 18),
+ GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
+ "pwm_sel", 19),
+ GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
+ "pwm_sel", 21),
+
+ GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
+ "uart_sel", 22),
+
+ GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
+ "uart_sel", 23),
+
+ GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
+ "uart_sel", 24),
+ GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
+ "uart_sel", 25),
+
+ GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
+ "axi_sel", 27),
+ GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
+ "axi_sel", 28),
+ GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
+ "axi_sel", 31),
+
+ /* INFRA1 */
+ GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
+ "spi_sel", 1),
+ GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
+ "msdc50_hclk_sel", 2),
+ GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
+ "axi_sel", 4),
+ GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
+ "axi_sel", 5),
+ GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
+ "msdc50_0_sel", 6),
+ GATE_INFRA1_FLAGS(CLK_INFRA_DVFSRC, "infra_dvfsrc",
+ "f_f26m_ck", 7, CLK_IS_CRITICAL),
+ GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
+ "axi_sel", 8),
+ GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
+ "axi_sel", 9),
+ GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
+ "f_f26m_ck", 10),
+ GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
+ "axi_sel", 11),
+ GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
+ "axi_sel", 12),
+ GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
+ "axi_sel", 13),
+ GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
+ "f_f26m_ck", 14),
+ GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
+ "msdc30_1_sel", 16),
+ GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
+ "msdc30_2_sel", 17),
+ GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
+ "axi_sel", 18),
+ GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
+ "axi_sel", 19),
+ GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
+ "axi_sel", 20),
+ GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
+ "axi_sel", 23),
+ /*GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",*/
+ /*"axi_sel", 24),*/
+ GATE_INFRA1(CLK_INFRA_AUD, "infra_audio",
+ "axi_sel", 25),
+ GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
+ "axi_sel", 26),
+ GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
+ "dxcc_sel", 27),
+ GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
+ "dxcc_sel", 28),
+ GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
+ "axi_sel", 30),
+ GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
+ "f_f26m_ck", 31),
+
+ /* INFRA2 */
+ GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
+ "f_f26m_ck", 0),
+ GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
+ "usb_top_sel", 1),
+ GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
+ "axi_sel", 2),
+ GATE_INFRA2(CLK_INFRA_AUD_26M_BCLK_CK,
+ "infracfg_ao_audio_26m_bclk_ck", "f_f26m_ck", 4),
+
+ GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
+ "spi_sel", 6),
+ GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
+ "i2c_sel", 7),
+ GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
+ "f_f26m_ck", 8),
+ GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
+ "spi_sel", 9),
+ GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
+ "spi_sel", 10),
+ GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
+ "fufs_sel", 11),
+ GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
+ "fufs_sel", 12),
+ GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
+ "fufs_sel", 13),
+ GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
+ "axi_sel", 14),
+
+ /*GATE_INFRA2_FLAGS(CLK_INFRA_SSPM, "infra_sspm",*/
+ /*"sspm_sel", 15, CLK_IGNORE_UNUSED),*/
+
+ GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
+ "axi_sel", 16),
+ GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
+ "axi_sel", 17),
+ GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
+ "i2c_sel", 18),
+ GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
+ "i2c_sel", 19),
+ GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
+ "i2c_sel", 20),
+ GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
+ "i2c_sel", 21),
+ GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
+ "i2c_sel", 22),
+ GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
+ "i2c_sel", 23),
+ GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
+ "i2c_sel", 24),
+ GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
+ "spi_sel", 25),
+ GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
+ "spi_sel", 26),
+ GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
+ "axi_sel", 27),
+ GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
+ "fufs_sel", 28),
+ GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
+ "faes_ufsfde_sel", 29),
+ GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
+ "fufs_sel", 30),
+ GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci",
+ "ssusb_top_xhci_sel", 31),
+
+ /* INFRA3 */
+ GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
+ "msdc50_0_sel", 0),
+ GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
+ "msdc50_0_sel", 1),
+ GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
+ "msdc50_0_sel", 2),
+ GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
+ "f_f26m_ck", 3),
+ GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
+ "f_f26m_ck", 4),
+ GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
+ "axi_sel", 5),
+ GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
+ "i2c_sel", 6),
+ GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
+ "msdc50_hclk_sel", 7),
+ GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
+ "msdc50_hclk_sel", 8),
+
+ GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
+ "axi_sel", 16),
+ GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
+ "axi_sel", 17),
+ GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
+ "axi_sel", 18),
+ GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
+ "axi_sel", 19),
+ GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
+ "f_f26m_ck", 20),
+ GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
+ "axi_sel", 21),
+ GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
+ "i2c_sel", 22),
+ GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
+ "i2c_sel", 23),
+ GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
+ "msdc50_0_sel", 24),
+ GATE_INFRA3(CLK_INFRA_DPMAIF_CK, "infra_dpmaif",
+ "dpmaif_sel", 26),
+ GATE_INFRA3(CLK_INFRA_FADSP, "infra_fadsp",
+ "adsp_sel", 27),
+ GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap",
+ "axi_sel", 28),
+ GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md",
+ "axi_sel", 29),
+ GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6",
+ "spi_sel", 30),
+ GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7",
+ "spi_sel", 31),
+};
+
+static const struct mtk_gate_regs apmixed_cg_regs = {
+ .set_ofs = 0x20,
+ .clr_ofs = 0x20,
+ .sta_ofs = 0x20,
+};
+
+#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
+ _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
+
+#define GATE_APMIXED(_id, _name, _parent, _shift) \
+ GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
+
+/*
+ * CRITICAL CLOCK:
+ * apmixed_appll26m is the toppest clock gate of all PLLs.
+ */
+static const struct mtk_gate apmixed_clks[] = {
+ GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m",
+ "f_f26m_ck",
+ 4),
+ GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL26M, "apmixed_appll26m",
+ "f_f26m_ck",
+ 5, CLK_IS_CRITICAL),
+ GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
+ "f_f26m_ck",
+ 6),
+ GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m",
+ "f_f26m_ck",
+ 7),
+ GATE_APMIXED(CLK_APMIXED_MM_F26M, "apmixed_mmsys26m",
+ "f_f26m_ck",
+ 8),
+ GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m",
+ "f_f26m_ck",
+ 9),
+ GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
+ "f_f26m_ck",
+ 11),
+ GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m",
+ "f_f26m_ck",
+ 13),
+ GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
+ "f_f26m_ck",
+ 14),
+ GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
+ "f_f26m_ck",
+ 16),
+ GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
+ "f_f26m_ck",
+ 17),
+};
+
+#define MT6779_PLL_FMAX (3800UL * MHZ)
+#define MT6779_PLL_FMIN (1500UL * MHZ)
+
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
+ _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
+ _pd_shift, _tuner_reg, _tuner_en_reg, \
+ _tuner_en_bit, _pcw_reg, _pcw_shift, \
+ _pcw_chg_reg, _div_table) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .flags = _flags, \
+ .rst_bar_mask = _rst_bar_mask, \
+ .fmax = MT6779_PLL_FMAX, \
+ .fmin = MT6779_PLL_FMIN, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = _pcwibits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .tuner_en_reg = _tuner_en_reg, \
+ .tuner_en_bit = _tuner_en_bit, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcw_chg_reg = _pcw_chg_reg, \
+ .div_table = _div_table, \
+ }
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
+ _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
+ _pd_shift, _tuner_reg, _tuner_en_reg, \
+ _tuner_en_bit, _pcw_reg, _pcw_shift, \
+ _pcw_chg_reg) \
+ PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
+ _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
+ _pd_shift, _tuner_reg, _tuner_en_reg, \
+ _tuner_en_bit, _pcw_reg, _pcw_shift, \
+ _pcw_chg_reg, NULL)
+
+static const struct mtk_pll_data plls[] = {
+ PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),
+ PLL_AO, 0,
+ 22, 8,
+ 0x0204, 24,
+ 0, 0, 0,
+ 0x0204, 0, 0),
+ PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),
+ PLL_AO, 0,
+ 22, 8,
+ 0x0214, 24,
+ 0, 0, 0,
+ 0x0214, 0, 0),
+ PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),
+ PLL_AO, 0,
+ 22, 8,
+ 0x02A4, 24,
+ 0, 0, 0,
+ 0x02A4, 0, 0),
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),
+ (HAVE_RST_BAR | PLL_AO), BIT(24),
+ 22, 8,
+ 0x0234, 24,
+ 0, 0, 0,
+ 0x0234, 0, 0),
+
+ PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),
+ (HAVE_RST_BAR), BIT(24),
+ 22, 8,
+ 0x0244, 24,
+ 0, 0, 0,
+ 0x0244, 0, 0),
+
+ PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),
+ 0, 0,
+ 22, 8,
+ 0x0254, 24,
+ 0, 0, 0,
+ 0x0254, 0, 0),
+
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),
+ 0, 0,
+ 22, 8,
+ 0x0264, 24,
+ 0, 0, 0,
+ 0x0264, 0, 0),
+
+ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
+ 0, 0,
+ 22, 8,
+ 0x0274, 24,
+ 0, 0, 0,
+ 0x0274, 0, 0),
+
+ PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),
+ (HAVE_RST_BAR), BIT(23),
+ 22, 8,
+ 0x02b4, 24,
+ 0, 0, 0,
+ 0x02b4, 0, 0),
+
+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),
+ (HAVE_RST_BAR), BIT(23),
+ 22, 8,
+ 0x0284, 24,
+ 0, 0, 0,
+ 0x0284, 0, 0),
+
+ PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),
+ 0, 0,
+ 32, 8,
+ 0x02C0, 1,
+ 0, 0x14, 0,
+ 0x02C4, 0, 0x2C0),
+
+ PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),
+ 0, 0,
+ 32, 8,
+ 0x02D4, 1,
+ 0, 0x14, 1,
+ 0x02D8, 0, 0x02D4),
+};
+
+
+static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+
+ mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static int clk_mt6779_top_probe(struct platform_device *pdev)
+{
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ void __iomem *base;
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ clk_data);
+
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+
+ mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
+ node, &mt6779_clk_lock, clk_data);
+
+ mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
+ base, &mt6779_clk_lock, clk_data);
+
+ mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
+ base, &mt6779_clk_lock, clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static int clk_mt6779_infra_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+
+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt6779[] = {
+ {
+ .compatible = "mediatek,mt6779-apmixed",
+ .data = clk_mt6779_apmixed_probe,
+ }, {
+ .compatible = "mediatek,mt6779-topckgen",
+ .data = clk_mt6779_top_probe,
+ }, {
+ .compatible = "mediatek,mt6779-infracfg_ao",
+ .data = clk_mt6779_infra_probe,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt6779_probe(struct platform_device *pdev)
+{
+ int (*clk_probe)(struct platform_device *pdev);
+ int r;
+
+ clk_probe = of_device_get_match_data(&pdev->dev);
+ if (!clk_probe)
+ return -EINVAL;
+
+ r = clk_probe(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt6779_drv = {
+ .probe = clk_mt6779_probe,
+ .driver = {
+ .name = "clk-mt6779",
+ .of_match_table = of_match_clk_mt6779,
+ },
+};
+
+static int __init clk_mt6779_init(void)
+{
+ return platform_driver_register(&clk_mt6779_drv);
+}
+
+arch_initcall(clk_mt6779_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797-img.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797-img.c
new file mode 100644
index 0000000..94cc480
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797-img.c
@@ -0,0 +1,76 @@
+/* Copyright (c) 2017 MediaTek Inc.
+ * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mt6797-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs img_cg_regs = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_IMG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &img_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate img_clks[] = {
+ GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),
+ GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10),
+ GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6),
+ GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0),
+};
+
+static const struct of_device_id of_match_clk_mt6797_img[] = {
+ { .compatible = "mediatek,mt6797-imgsys", },
+ {}
+};
+
+static int clk_mt6797_img_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
+
+ mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt6797_img_drv = {
+ .probe = clk_mt6797_img_probe,
+ .driver = {
+ .name = "clk-mt6797-img",
+ .of_match_table = of_match_clk_mt6797_img,
+ },
+};
+
+builtin_platform_driver(clk_mt6797_img_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797-mm.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797-mm.c
new file mode 100644
index 0000000..c57d3ee
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797-mm.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mt6797-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs mm0_cg_regs = {
+ .set_ofs = 0x0104,
+ .clr_ofs = 0x0108,
+ .sta_ofs = 0x0100,
+};
+
+static const struct mtk_gate_regs mm1_cg_regs = {
+ .set_ofs = 0x0114,
+ .clr_ofs = 0x0118,
+ .sta_ofs = 0x0110,
+};
+
+#define GATE_MM0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+}
+
+#define GATE_MM1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+}
+
+static const struct mtk_gate mm_clks[] = {
+ GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
+ GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
+ GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 2),
+ GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 3),
+ GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 4),
+ GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 5),
+ GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 6),
+ GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 7),
+ GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 8),
+ GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
+ GATE_MM0(CLK_MM_MDP_COLOR, "mm_mdp_color", "mm_sel", 10),
+ GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
+ GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
+ GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
+ GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
+ GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 15),
+ GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 16),
+ GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 17),
+ GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 18),
+ GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19),
+ GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 20),
+ GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
+ GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
+ GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 23),
+ GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "mm_sel", 24),
+ GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
+ GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
+ GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 27),
+ GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "mm_sel", 28),
+ GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 29),
+ GATE_MM0(CLK_MM_DISP_DSC, "mm_disp_dsc", "mm_sel", 30),
+ GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
+ GATE_MM1(CLK_MM_DSI0_MM_CLOCK, "mm_dsi0_mm_clock", "mm_sel", 0),
+ GATE_MM1(CLK_MM_DSI1_MM_CLOCK, "mm_dsi1_mm_clock", "mm_sel", 2),
+ GATE_MM1(CLK_MM_DPI_MM_CLOCK, "mm_dpi_mm_clock", "mm_sel", 4),
+ GATE_MM1(CLK_MM_DPI_INTERFACE_CLOCK, "mm_dpi_interface_clock",
+ "dpi0_sel", 5),
+ GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MM_CLOCK, "mm_larb4_axi_asif_mm_clock",
+ "mm_sel", 6),
+ GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK, "mm_larb4_axi_asif_mjc_clock",
+ "mjc_sel", 7),
+ GATE_MM1(CLK_MM_DISP_OVL0_MOUT_CLOCK, "mm_disp_ovl0_mout_clock",
+ "mm_sel", 8),
+ GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 9),
+ GATE_MM1(CLK_MM_DSI0_INTERFACE_CLOCK, "mm_dsi0_interface_clock",
+ "clk26m", 1),
+ GATE_MM1(CLK_MM_DSI1_INTERFACE_CLOCK, "mm_dsi1_interface_clock",
+ "clk26m", 3),
+};
+
+static const struct of_device_id of_match_clk_mt6797_mm[] = {
+ { .compatible = "mediatek,mt6797-mmsys", },
+ {}
+};
+
+static int clk_mt6797_mm_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_MM_NR);
+
+ mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt6797_mm_drv = {
+ .probe = clk_mt6797_mm_probe,
+ .driver = {
+ .name = "clk-mt6797-mm",
+ .of_match_table = of_match_clk_mt6797_mm,
+ },
+};
+
+builtin_platform_driver(clk_mt6797_mm_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797-vdec.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797-vdec.c
new file mode 100644
index 0000000..7c402ca
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797-vdec.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6797-clk.h>
+
+static const struct mtk_gate_regs vdec0_cg_regs = {
+ .set_ofs = 0x0000,
+ .clr_ofs = 0x0004,
+ .sta_ofs = 0x0000,
+};
+
+static const struct mtk_gate_regs vdec1_cg_regs = {
+ .set_ofs = 0x0008,
+ .clr_ofs = 0x000c,
+ .sta_ofs = 0x0008,
+};
+
+#define GATE_VDEC0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vdec0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+}
+
+#define GATE_VDEC1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vdec1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+}
+
+static const struct mtk_gate vdec_clks[] = {
+ GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8),
+ GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
+ GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
+ GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "mm_sel", 0),
+};
+
+static const struct of_device_id of_match_clk_mt6797_vdec[] = {
+ { .compatible = "mediatek,mt6797-vdecsys", },
+ {}
+};
+
+static int clk_mt6797_vdec_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
+
+ mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt6797_vdec_drv = {
+ .probe = clk_mt6797_vdec_probe,
+ .driver = {
+ .name = "clk-mt6797-vdec",
+ .of_match_table = of_match_clk_mt6797_vdec,
+ },
+};
+
+builtin_platform_driver(clk_mt6797_vdec_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797-venc.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797-venc.c
new file mode 100644
index 0000000..e73d517
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797-venc.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6797-clk.h>
+
+static const struct mtk_gate_regs venc_cg_regs = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_VENC(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &venc_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate venc_clks[] = {
+ GATE_VENC(CLK_VENC_0, "venc_0", "mm_sel", 0),
+ GATE_VENC(CLK_VENC_1, "venc_1", "venc_sel", 4),
+ GATE_VENC(CLK_VENC_2, "venc_2", "venc_sel", 8),
+ GATE_VENC(CLK_VENC_3, "venc_3", "venc_sel", 12),
+};
+
+static const struct of_device_id of_match_clk_mt6797_venc[] = {
+ { .compatible = "mediatek,mt6797-vencsys", },
+ {}
+};
+
+static int clk_mt6797_venc_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_VENC_NR);
+
+ mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt6797_venc_drv = {
+ .probe = clk_mt6797_venc_probe,
+ .driver = {
+ .name = "clk-mt6797-venc",
+ .of_match_table = of_match_clk_mt6797_venc,
+ },
+};
+
+builtin_platform_driver(clk_mt6797_venc_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797.c
new file mode 100644
index 0000000..5702bc9
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6797.c
@@ -0,0 +1,714 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6797-clk.h>
+
+/*
+ * For some clocks, we don't care what their actual rates are. And these
+ * clocks may change their rate on different products or different scenarios.
+ * So we model these clocks' rate as 0, to denote it's not an actual rate.
+ */
+
+static DEFINE_SPINLOCK(mt6797_clk_lock);
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1),
+ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
+ FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
+ FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
+ FACTOR(CLK_TOP_SYSPLL_D3_D3, "syspll_d3_d3", "syspll_d3", 1, 3),
+ FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
+ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
+ FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
+ FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
+ FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
+ FACTOR(CLK_TOP_SSUSB_PHY_48M_CK, "ssusb_phy_48m_ck", "univpll", 1, 1),
+ FACTOR(CLK_TOP_USB_PHY48M_CK, "usb_phy48m_ck", "univpll", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
+ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
+ FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
+ FACTOR(CLK_TOP_ULPOSC_CK_ORG, "ulposc_ck_org", "ulposc", 1, 1),
+ FACTOR(CLK_TOP_ULPOSC_CK, "ulposc_ck", "ulposc_ck_org", 1, 3),
+ FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc_ck", 1, 2),
+ FACTOR(CLK_TOP_ULPOSC_D3, "ulposc_d3", "ulposc_ck", 1, 4),
+ FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc_ck", 1, 8),
+ FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc_ck", 1, 10),
+ FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc_ck_org", 1, 1),
+ FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
+ FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
+ FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
+ FACTOR(CLK_TOP_MFGPLL_D2, "mfgpll_d2", "mfgpll_ck", 1, 2),
+ FACTOR(CLK_TOP_IMGPLL_CK, "imgpll_ck", "imgpll", 1, 1),
+ FACTOR(CLK_TOP_IMGPLL_D2, "imgpll_d2", "imgpll_ck", 1, 2),
+ FACTOR(CLK_TOP_IMGPLL_D4, "imgpll_d4", "imgpll_ck", 1, 4),
+ FACTOR(CLK_TOP_CODECPLL_CK, "codecpll_ck", "codecpll", 1, 1),
+ FACTOR(CLK_TOP_CODECPLL_D2, "codecpll_d2", "codecpll_ck", 1, 2),
+ FACTOR(CLK_TOP_VDECPLL_CK, "vdecpll_ck", "vdecpll", 1, 1),
+ FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
+ FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
+ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
+ FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
+ FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
+ FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
+ FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
+ FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll_ck", 1, 8),
+};
+
+static const char * const axi_parents[] = {
+ "clk26m",
+ "syspll_d7",
+ "ulposc_axi_ck_mux",
+};
+
+static const char * const ulposc_axi_ck_mux_parents[] = {
+ "syspll1_d4",
+ "ulposc_axi_ck_mux_pre",
+};
+
+static const char * const ulposc_axi_ck_mux_pre_parents[] = {
+ "ulposc_d2",
+ "ulposc_d3",
+};
+
+static const char * const ddrphycfg_parents[] = {
+ "clk26m",
+ "syspll3_d2",
+ "syspll2_d4",
+ "syspll1_d8",
+};
+
+static const char * const mm_parents[] = {
+ "clk26m",
+ "imgpll_ck",
+ "univpll1_d2",
+ "syspll1_d2",
+};
+
+static const char * const pwm_parents[] = {
+ "clk26m",
+ "univpll2_d4",
+ "ulposc_d2",
+ "ulposc_d3",
+ "ulposc_d8",
+ "ulposc_d10",
+ "ulposc_d4",
+};
+
+static const char * const vdec_parents[] = {
+ "clk26m",
+ "vdecpll_ck",
+ "imgpll_ck",
+ "syspll_d3",
+ "univpll_d5",
+ "clk26m",
+ "clk26m",
+};
+
+static const char * const venc_parents[] = {
+ "clk26m",
+ "codecpll_ck",
+ "syspll_d3",
+};
+
+static const char * const mfg_parents[] = {
+ "clk26m",
+ "mfgpll_ck",
+ "syspll_d3",
+ "univpll_d3",
+};
+
+static const char * const camtg[] = {
+ "clk26m",
+ "univpll_d26",
+ "univpll2_d2",
+};
+
+static const char * const uart_parents[] = {
+ "clk26m",
+ "univpll2_d8",
+};
+
+static const char * const spi_parents[] = {
+ "clk26m",
+ "syspll3_d2",
+ "syspll2_d4",
+ "ulposc_spi_ck_mux",
+};
+
+static const char * const ulposc_spi_ck_mux_parents[] = {
+ "ulposc_d2",
+ "ulposc_d3",
+};
+
+static const char * const usb20_parents[] = {
+ "clk26m",
+ "univpll1_d8",
+ "syspll4_d2",
+};
+
+static const char * const msdc50_0_hclk_parents[] = {
+ "clk26m",
+ "syspll1_d2",
+ "syspll2_d2",
+ "syspll4_d2",
+};
+
+static const char * const msdc50_0_parents[] = {
+ "clk26m",
+ "msdcpll",
+ "syspll_d3",
+ "univpll1_d4",
+ "syspll2_d2",
+ "syspll_d7",
+ "msdcpll_d2",
+ "univpll1_d2",
+ "univpll_d3",
+};
+
+static const char * const msdc30_1_parents[] = {
+ "clk26m",
+ "univpll2_d2",
+ "msdcpll_d2",
+ "univpll1_d4",
+ "syspll2_d2",
+ "syspll_d7",
+ "univpll_d7",
+};
+
+static const char * const msdc30_2_parents[] = {
+ "clk26m",
+ "univpll2_d8",
+ "syspll2_d8",
+ "syspll1_d8",
+ "msdcpll_d8",
+ "syspll3_d4",
+ "univpll_d26",
+};
+
+static const char * const audio_parents[] = {
+ "clk26m",
+ "syspll3_d4",
+ "syspll4_d4",
+ "syspll1_d16",
+};
+
+static const char * const aud_intbus_parents[] = {
+ "clk26m",
+ "syspll1_d4",
+ "syspll4_d2",
+};
+
+static const char * const pmicspi_parents[] = {
+ "clk26m",
+ "univpll_d26",
+ "syspll3_d4",
+ "syspll1_d8",
+ "ulposc_d4",
+ "ulposc_d8",
+ "syspll2_d8",
+};
+
+static const char * const scp_parents[] = {
+ "clk26m",
+ "syspll_d3",
+ "ulposc_ck",
+ "univpll_d5",
+};
+
+static const char * const atb_parents[] = {
+ "clk26m",
+ "syspll1_d2",
+ "syspll_d5",
+};
+
+static const char * const mjc_parents[] = {
+ "clk26m",
+ "imgpll_ck",
+ "univpll_d5",
+ "syspll1_d2",
+};
+
+static const char * const dpi0_parents[] = {
+ "clk26m",
+ "tvdpll_d2",
+ "tvdpll_d4",
+ "tvdpll_d8",
+ "tvdpll_d16",
+ "clk26m",
+ "clk26m",
+};
+
+static const char * const aud_1_parents[] = {
+ "clk26m",
+ "apll1_ck",
+};
+
+static const char * const aud_2_parents[] = {
+ "clk26m",
+ "apll2_ck",
+};
+
+static const char * const ssusb_top_sys_parents[] = {
+ "clk26m",
+ "univpll3_d2",
+};
+
+static const char * const spm_parents[] = {
+ "clk26m",
+ "syspll1_d8",
+};
+
+static const char * const bsi_spi_parents[] = {
+ "clk26m",
+ "syspll_d3_d3",
+ "syspll1_d4",
+ "syspll_d7",
+};
+
+static const char * const audio_h_parents[] = {
+ "clk26m",
+ "apll2_ck",
+ "apll1_ck",
+ "univpll_d7",
+};
+
+static const char * const mfg_52m_parents[] = {
+ "clk26m",
+ "univpll2_d8",
+ "univpll2_d4",
+ "univpll2_d4",
+};
+
+static const char * const anc_md32_parents[] = {
+ "clk26m",
+ "syspll1_d2",
+ "univpll_d5",
+};
+
+static const struct mtk_composite top_muxes[] = {
+ MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
+ ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
+ MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
+ ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
+ MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
+ 0x0040, 0, 2),
+ MUX(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
+ 0x0040, 16, 2),
+ MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
+ 0x0040, 24, 2),
+ MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, 0x0050, 8, 3, 15),
+ MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, 0x0050, 16, 2, 23),
+ MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31),
+ MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7),
+ MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
+ MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23),
+ MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux",
+ ulposc_spi_ck_mux_parents, 0x0060, 18, 1),
+ MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents,
+ 0x0060, 24, 2, 31),
+ MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
+ msdc50_0_hclk_parents, 0x0070, 8, 2),
+ MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
+ 0x0070, 16, 4, 23),
+ MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
+ 0x0070, 24, 3, 31),
+ MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents,
+ 0x0080, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents,
+ 0x0080, 16, 2, 23),
+ MUX(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents,
+ 0x0080, 24, 2),
+ MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents,
+ 0x0090, 0, 3),
+ MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents,
+ 0x0090, 8, 2),
+ MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents,
+ 0x0090, 16, 2),
+ MUX_GATE(CLK_TOP_MUX_MJC, "mjc_sel", mjc_parents, 0x0090, 24, 2, 31),
+ MUX_GATE(CLK_TOP_MUX_DPI0, "dpi0_sel", dpi0_parents, 0x00A0, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
+ 0x00A0, 16, 1, 23),
+ MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
+ 0x00A0, 24, 1, 31),
+ MUX(CLK_TOP_MUX_SSUSB_TOP_SYS, "ssusb_top_sys_sel",
+ ssusb_top_sys_parents, 0x00B0, 8, 1),
+ MUX(CLK_TOP_MUX_SPM, "spm_sel", spm_parents,
+ 0x00C0, 0, 1),
+ MUX(CLK_TOP_MUX_BSI_SPI, "bsi_spi_sel", bsi_spi_parents,
+ 0x00C0, 8, 2),
+ MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents,
+ 0x00C0, 16, 2, 23),
+ MUX_GATE(CLK_TOP_MUX_ANC_MD32, "anc_md32_sel", anc_md32_parents,
+ 0x00C0, 24, 2, 31),
+ MUX(CLK_TOP_MUX_MFG_52M, "mfg_52m_sel", mfg_52m_parents,
+ 0x0104, 1, 2),
+};
+
+static int mtk_topckgen_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ void __iomem *base;
+ struct device_node *node = pdev->dev.of_node;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
+
+ mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
+ clk_data);
+
+ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
+ &mt6797_clk_lock, clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct mtk_gate_regs infra0_cg_regs = {
+ .set_ofs = 0x0080,
+ .clr_ofs = 0x0084,
+ .sta_ofs = 0x0090,
+};
+
+static const struct mtk_gate_regs infra1_cg_regs = {
+ .set_ofs = 0x0088,
+ .clr_ofs = 0x008c,
+ .sta_ofs = 0x0094,
+};
+
+static const struct mtk_gate_regs infra2_cg_regs = {
+ .set_ofs = 0x00a8,
+ .clr_ofs = 0x00ac,
+ .sta_ofs = 0x00b0,
+};
+
+#define GATE_ICG0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+}
+
+#define GATE_ICG1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+}
+
+#define GATE_ICG2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+}
+
+static const struct mtk_gate infra_clks[] = {
+ GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
+ GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
+ GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pmicspi_sel", 2),
+ GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pmicspi_sel", 3),
+ GATE_ICG0(CLK_INFRA_SCP, "infra_scp", "scp_sel", 4),
+ GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
+ GATE_ICG0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
+ GATE_ICG0(CLK_INFRA_SEJ_13M, "infra_sej_13m", "clk26m", 7),
+ GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "usb20_sel", 8),
+ GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9),
+ GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
+ GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11),
+ GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12),
+ GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13),
+ GATE_ICG0(CLK_INFRA_I2C3, "infra_i2c3", "axi_sel", 14),
+ GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15),
+ GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16),
+ GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17),
+ GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18),
+ GATE_ICG0(CLK_INFRA_PWM4, "infra_pwm4", "axi_sel", 19),
+ GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21),
+ GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
+ GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
+ GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
+ GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
+ GATE_ICG0(CLK_INFRA_MD2MD_CCIF_0, "infra_md2md_ccif_0", "axi_sel", 27),
+ GATE_ICG0(CLK_INFRA_MD2MD_CCIF_1, "infra_md2md_ccif_1", "axi_sel", 28),
+ GATE_ICG0(CLK_INFRA_MD2MD_CCIF_2, "infra_md2md_ccif_2", "axi_sel", 29),
+ GATE_ICG0(CLK_INFRA_FHCTL, "infra_fhctl", "clk26m", 30),
+ GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
+ GATE_ICG1(CLK_INFRA_MD2MD_CCIF_3, "infra_md2md_ccif_3", "axi_sel", 0),
+ GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1),
+ GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_sel", 2),
+ GATE_ICG1(CLK_INFRA_MD2MD_CCIF_4, "infra_md2md_ccif_4", "axi_sel", 3),
+ GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4),
+ GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5),
+ GATE_ICG1(CLK_INFRA_MD2MD_CCIF_5, "infra_md2md_ccif_5", "axi_sel", 7),
+ GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
+ GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
+ GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
+ GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
+ GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_0, "infra_ap_c2k_ccif_0",
+ "axi_sel", 12),
+ GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_1, "infra_ap_c2k_ccif_1",
+ "axi_sel", 13),
+ GATE_ICG1(CLK_INFRA_CLDMA, "infra_cldma", "axi_sel", 16),
+ GATE_ICG1(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "pwm_sel", 17),
+ GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18),
+ GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20),
+ GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "mm_sel", 22),
+ GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
+ GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
+ GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
+ GATE_ICG1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
+ GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
+ GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
+ GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
+ GATE_ICG2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "axi_sel", 3),
+ GATE_ICG2(CLK_INFRA_I2C2_ARB, "infra_i2c2_arb", "axi_sel", 4),
+ GATE_ICG2(CLK_INFRA_I2C3_IMM, "infra_i2c3_imm", "axi_sel", 5),
+ GATE_ICG2(CLK_INFRA_I2C3_ARB, "infra_i2c3_arb", "axi_sel", 6),
+ GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
+ GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
+ GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
+ GATE_ICG2(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m", "clk26m", 11),
+ GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
+ GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
+ GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
+ GATE_ICG2(CLK_INFRA_AES_TOP0, "infra_aes_top0", "axi_sel", 16),
+ GATE_ICG2(CLK_INFRA_AES_TOP1, "infra_aes_top1", "axi_sel", 17),
+ GATE_ICG2(CLK_INFRA_SSUSB_BUS, "infra_ssusb_bus", "axi_sel", 18),
+ GATE_ICG2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 19),
+ GATE_ICG2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 20),
+ GATE_ICG2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 21),
+ GATE_ICG2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 22),
+ GATE_ICG2(CLK_INFRA_IRTX, "infra_irtx", "spi_sel", 23),
+ GATE_ICG2(CLK_INFRA_SSUSB_SYS, "infra_ssusb_sys",
+ "ssusb_top_sys_sel", 24),
+ GATE_ICG2(CLK_INFRA_SSUSB_REF, "infra_ssusb_ref", "clk26m", 9),
+ GATE_ICG2(CLK_INFRA_AUDIO_26M, "infra_audio_26m", "clk26m", 26),
+ GATE_ICG2(CLK_INFRA_AUDIO_26M_PAD_TOP, "infra_audio_26m_pad_top",
+ "clk26m", 27),
+ GATE_ICG2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share",
+ "axi_sel", 28),
+ GATE_ICG2(CLK_INFRA_VAD_WRAP_SOC, "infra_vad_wrap_soc", "axi_sel", 29),
+ GATE_ICG2(CLK_INFRA_DRAMC_CONF, "infra_dramc_conf", "axi_sel", 30),
+ GATE_ICG2(CLK_INFRA_DRAMC_B_CONF, "infra_dramc_b_conf", "axi_sel", 31),
+ GATE_ICG1(CLK_INFRA_MFG_VCG, "infra_mfg_vcg", "mfg_52m_sel", 14),
+};
+
+static const struct mtk_fixed_factor infra_fixed_divs[] = {
+ FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2),
+};
+
+static struct clk_onecell_data *infra_clk_data;
+
+static void mtk_infrasys_init_early(struct device_node *node)
+{
+ int r, i;
+
+ if (!infra_clk_data) {
+ infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
+
+ for (i = 0; i < CLK_INFRA_NR; i++)
+ infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
+ }
+
+ mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
+ infra_clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+
+CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg",
+ mtk_infrasys_init_early);
+
+static int mtk_infrasys_init(struct platform_device *pdev)
+{
+ int r, i;
+ struct device_node *node = pdev->dev.of_node;
+
+ if (!infra_clk_data) {
+ infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
+ } else {
+ for (i = 0; i < CLK_INFRA_NR; i++) {
+ if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
+ infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
+ }
+ }
+
+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+ infra_clk_data);
+ mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
+ infra_clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
+ if (r)
+ return r;
+
+ return 0;
+}
+
+#define MT6797_PLL_FMAX (3000UL * MHZ)
+
+#define CON0_MT6797_RST_BAR BIT(24)
+
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
+ _pcw_shift, _div_table) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .flags = _flags, \
+ .rst_bar_mask = CON0_MT6797_RST_BAR, \
+ .fmax = MT6797_PLL_FMAX, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .div_table = _div_table, \
+}
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
+ _pcw_shift) \
+ PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
+ NULL)
+
+static const struct mtk_pll_data plls[] = {
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, PLL_AO,
+ 21, 0x220, 4, 0x0, 0x224, 0),
+ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7,
+ 0x230, 4, 0x0, 0x234, 14),
+ PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21,
+ 0x244, 24, 0x0, 0x244, 0),
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21,
+ 0x250, 4, 0x0, 0x254, 0),
+ PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21,
+ 0x260, 4, 0x0, 0x264, 0),
+ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,
+ 0x270, 4, 0x0, 0x274, 0),
+ PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21,
+ 0x290, 4, 0x0, 0x294, 0),
+ PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21,
+ 0x2E4, 4, 0x0, 0x2E8, 0),
+ PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31,
+ 0x2A0, 4, 0x2A8, 0x2A4, 0),
+ PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31,
+ 0x2B4, 4, 0x2BC, 0x2B8, 0),
+};
+
+static int mtk_apmixedsys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
+ if (!clk_data)
+ return -ENOMEM;
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt6797[] = {
+ {
+ .compatible = "mediatek,mt6797-topckgen",
+ .data = mtk_topckgen_init,
+ }, {
+ .compatible = "mediatek,mt6797-infracfg",
+ .data = mtk_infrasys_init,
+ }, {
+ .compatible = "mediatek,mt6797-apmixedsys",
+ .data = mtk_apmixedsys_init,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt6797_probe(struct platform_device *pdev)
+{
+ int (*clk_init)(struct platform_device *);
+ int r;
+
+ clk_init = of_device_get_match_data(&pdev->dev);
+ if (!clk_init)
+ return -EINVAL;
+
+ r = clk_init(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt6797_drv = {
+ .probe = clk_mt6797_probe,
+ .driver = {
+ .name = "clk-mt6797",
+ .of_match_table = of_match_clk_mt6797,
+ },
+};
+
+static int __init clk_mt6797_init(void)
+{
+ return platform_driver_register(&clk_mt6797_drv);
+}
+
+arch_initcall(clk_mt6797_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-audsys.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-audsys.c
new file mode 100755
index 0000000..f7464ea
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-audsys.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6880-clk.h>
+
+#define MT_CLKMGR_MODULE_INIT 0
+
+#define MT_CCF_BRINGUP 1
+
+#define INV_OFS -1
+
+/* get spm power status struct to register inside clk_data */
+static struct pwr_status pwr_stat = GATE_PWR_STAT(0x16C,
+ 0x170, INV_OFS, BIT(21), BIT(21));
+
+static const struct mtk_gate_regs audsys0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs audsys1_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x4,
+};
+
+static const struct mtk_gate_regs audsys2_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x8,
+};
+
+#define GATE_AUDSYS0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audsys0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ .pwr_stat = &pwr_stat, \
+ }
+
+#define GATE_AUDSYS1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audsys1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ .pwr_stat = &pwr_stat, \
+ }
+
+#define GATE_AUDSYS2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audsys2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ .pwr_stat = &pwr_stat, \
+ }
+
+static const struct mtk_gate audsys_clks[] = {
+ /* AUDSYS0 */
+ GATE_AUDSYS0(CLK_AUDSYS_AFE, "aud_afe",
+ "audio_ck"/* parent */, 2),
+ GATE_AUDSYS0(CLK_AUDSYS_22M, "aud_22m",
+ "aud_engen1_ck"/* parent */, 8),
+ GATE_AUDSYS0(CLK_AUDSYS_24M, "aud_24m",
+ "aud_engen2_ck"/* parent */, 9),
+ GATE_AUDSYS0(CLK_AUDSYS_APLL2_TUNER, "aud_apll2_tuner",
+ "aud_engen2_ck"/* parent */, 18),
+ GATE_AUDSYS0(CLK_AUDSYS_APLL_TUNER, "aud_apll_tuner",
+ "aud_engen1_ck"/* parent */, 19),
+ GATE_AUDSYS0(CLK_AUDSYS_TDM, "aud_tdm_ck",
+ "aud_engen1_ck"/* parent */, 20),
+ GATE_AUDSYS0(CLK_AUDSYS_ADC, "aud_adc",
+ "audio_ck"/* parent */, 24),
+ GATE_AUDSYS0(CLK_AUDSYS_DAC, "aud_dac",
+ "audio_ck"/* parent */, 25),
+ GATE_AUDSYS0(CLK_AUDSYS_DAC_PREDIS, "aud_dac_predis",
+ "audio_ck"/* parent */, 26),
+ GATE_AUDSYS0(CLK_AUDSYS_TML, "aud_tml",
+ "audio_ck"/* parent */, 27),
+ /* AUDSYS1 */
+ GATE_AUDSYS1(CLK_AUDSYS_I2S0_BCLK, "aud_i2s0_bclk",
+ "audio_ck"/* parent */, 4),
+ GATE_AUDSYS1(CLK_AUDSYS_I2S1_BCLK, "aud_i2s1_bclk",
+ "audio_ck"/* parent */, 5),
+ GATE_AUDSYS1(CLK_AUDSYS_I2S2_BCLK, "aud_i2s2_bclk",
+ "audio_ck"/* parent */, 6),
+ GATE_AUDSYS1(CLK_AUDSYS_I2S4_BCLK, "aud_i2s4_bclk",
+ "audio_ck"/* parent */, 7),
+ GATE_AUDSYS1(CLK_AUDSYS_I2S5_BCLK, "aud_i2s5_bclk",
+ "audio_ck"/* parent */, 8),
+ GATE_AUDSYS1(CLK_AUDSYS_I2S6_BCLK, "aud_i2s6_bclk",
+ "audio_ck"/* parent */, 9),
+ GATE_AUDSYS1(CLK_AUDSYS_GENERAL1_ASRC, "aud_general1_asrc",
+ "audio_ck"/* parent */, 13),
+ GATE_AUDSYS1(CLK_AUDSYS_GENERAL2_ASRC, "aud_general2_asrc",
+ "audio_ck"/* parent */, 14),
+ GATE_AUDSYS1(CLK_AUDSYS_ADDA6_ADC, "aud_adda6_adc",
+ "audio_ck"/* parent */, 20),
+ /* AUDSYS2 */
+ GATE_AUDSYS2(CLK_AUDSYS_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc",
+ "audio_ck"/* parent */, 12),
+ GATE_AUDSYS2(CLK_AUDSYS_AFE_SRC_PCM_TX, "aud_afe_src_pcm_tx",
+ "audio_ck"/* parent */, 16),
+ GATE_AUDSYS2(CLK_AUDSYS_AFE_SRC_PCM_TX2, "aud_afe_src_pcm_tx2",
+ "audio_ck"/* parent */, 17),
+ GATE_AUDSYS2(CLK_AUDSYS_AFE_SRC_PCM_TX3, "aud_afe_src_pcm_tx3",
+ "audio_ck"/* parent */, 18),
+ GATE_AUDSYS2(CLK_AUDSYS_AFE_SRC_PCM_RX, "aud_afe_src_pcm_rx",
+ "audio_ck"/* parent */, 19),
+ GATE_AUDSYS2(CLK_AUDSYS_AFE_SRC_I2SIN, "aud_afe_src_i2sin",
+ "audio_ck"/* parent */, 20),
+ GATE_AUDSYS2(CLK_AUDSYS_AFE_SRC_I2SOUT, "aud_afe_src_i2sout",
+ "audio_ck"/* parent */, 21),
+};
+
+static int clk_mt6880_audsys_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_AUDSYS_NR_CLK);
+
+ mtk_clk_register_gates(node, audsys_clks, ARRAY_SIZE(audsys_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt6880_audsys[] = {
+ { .compatible = "mediatek,mt6880-audsys", },
+ {}
+};
+
+#if MT_CLKMGR_MODULE_INIT
+
+static struct platform_driver clk_mt6880_audsys_drv = {
+ .probe = clk_mt6880_audsys_probe,
+ .driver = {
+ .name = "clk-mt6880-audsys",
+ .of_match_table = of_match_clk_mt6880_audsys,
+ },
+};
+
+builtin_platform_driver(clk_mt6880_audsys_drv);
+
+#else
+
+static struct platform_driver clk_mt6880_audsys_drv = {
+ .probe = clk_mt6880_audsys_probe,
+ .driver = {
+ .name = "clk-mt6880-audsys",
+ .of_match_table = of_match_clk_mt6880_audsys,
+ },
+};
+static int __init clk_mt6880_audsys_platform_init(void)
+{
+ return platform_driver_register(&clk_mt6880_audsys_drv);
+}
+arch_initcall(clk_mt6880_audsys_platform_init);
+
+#endif /* MT_CLKMGR_MODULE_INIT */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-dbgsys_dem.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-dbgsys_dem.c
new file mode 100755
index 0000000..18259ed
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-dbgsys_dem.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6880-clk.h>
+
+#define MT_CLKMGR_MODULE_INIT 0
+
+#define MT_CCF_BRINGUP 1
+
+#define INV_OFS -1
+
+
+
+static const struct mtk_gate_regs dbgsys_dem0_cg_regs = {
+ .set_ofs = 0x2c,
+ .clr_ofs = 0x2c,
+ .sta_ofs = 0x2c,
+};
+
+static const struct mtk_gate_regs dbgsys_dem1_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+static const struct mtk_gate_regs dbgsys_dem2_cg_regs = {
+ .set_ofs = 0x70,
+ .clr_ofs = 0x70,
+ .sta_ofs = 0x70,
+};
+
+#define GATE_DBGSYS_DEM0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &dbgsys_dem0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_DBGSYS_DEM1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &dbgsys_dem1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_DBGSYS_DEM2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &dbgsys_dem2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate dbgsys_dem_clks[] = {
+ /* DBGSYS_DEM0 */
+ GATE_DBGSYS_DEM0(CLK_DBGSYS_DEM_BUSCLK_EN, "dbgsys_dem_busclk_en",
+ "axi_ck"/* parent */, 0),
+ /* DBGSYS_DEM1 */
+ GATE_DBGSYS_DEM1(CLK_DBGSYS_DEM_SYSCLK_EN, "dbgsys_dem_sysclk_en",
+ "axi_ck"/* parent */, 0),
+ /* DBGSYS_DEM2 */
+ GATE_DBGSYS_DEM2(CLK_DBGSYS_DEM_ATB_EN, "dbgsys_dem_atb_en",
+ "axi_ck"/* parent */, 0),
+};
+
+static int clk_mt6880_dbgsys_dem_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_DBGSYS_DEM_NR_CLK);
+
+ mtk_clk_register_gates(node, dbgsys_dem_clks, ARRAY_SIZE(dbgsys_dem_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt6880_dbgsys_dem[] = {
+ { .compatible = "mediatek,mt6880-dbgsys_dem", },
+ {}
+};
+
+#if MT_CLKMGR_MODULE_INIT
+
+static struct platform_driver clk_mt6880_dbgsys_dem_drv = {
+ .probe = clk_mt6880_dbgsys_dem_probe,
+ .driver = {
+ .name = "clk-mt6880-dbgsys_dem",
+ .of_match_table = of_match_clk_mt6880_dbgsys_dem,
+ },
+};
+
+builtin_platform_driver(clk_mt6880_dbgsys_dem_drv);
+
+#else
+
+static struct platform_driver clk_mt6880_dbgsys_dem_drv = {
+ .probe = clk_mt6880_dbgsys_dem_probe,
+ .driver = {
+ .name = "clk-mt6880-dbgsys_dem",
+ .of_match_table = of_match_clk_mt6880_dbgsys_dem,
+ },
+};
+static int __init clk_mt6880_dbgsys_dem_platform_init(void)
+{
+ return platform_driver_register(&clk_mt6880_dbgsys_dem_drv);
+}
+arch_initcall(clk_mt6880_dbgsys_dem_platform_init);
+
+#endif /* MT_CLKMGR_MODULE_INIT */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-fmeter.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-fmeter.h
new file mode 100755
index 0000000..bd8ec71
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-fmeter.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+
+#ifndef _CLK_MT6880_FMETER_H
+#define _CLK_MT6880_FMETER_H
+
+/* generate from clock_table.xlsx from TOPCKGEN DE */
+
+/* CKGEN Part */
+#define FM_AXI_CK 1
+#define FM_SPM_CK 2
+#define FM_BUS_CK 3
+#define FM_MM_CK 4
+#define FM_MFG_REF_CK 5
+#define FM_FUART_CK 6
+#define FM_MSDC50_0_H_CK 7
+#define FM_MSDC50_0_CK 8
+#define FM_MSDC30_1_CK 9
+#define FM_AUDIO_CK 10
+#define FM_AUD_INTBUS_CK 11
+#define FM_AUD_ENGEN1_CK 12
+#define FM_AUD_ENGEN2_CK 13
+#define FM_AUD1_CK 14
+#define FM_AUD2_CK 15
+#define FM_FPWRAP_ULPOSC_CK 16
+#define FM_ATB_CK 17
+#define FM_PWRMCU_CK 18
+#define FM_DBI_CK 19
+#define FM_FDISP_PWM_CK 20
+#define FM_FUSB_CK 21
+#define FM_FSSUSB_XHCI_CK 22
+#define FM_I2C_CK 23
+#define FM_TL_CK 24
+#define FM_DPMAIF_MAIN_CK 25
+#define FM_PWM_CK 26
+#define FM_SPMI_M_MST_CK 27
+#define FM_SPMI_P_MST_CK 28
+#define FM_DVFSRC_CK 29
+#define FM_MCUPM_CK 30
+#define FM_SFLASH_CK 31
+#define FM_GCPU_CK 32
+#define FM_SPI_CK 33
+#define FM_SPIS_CK 34
+#define FM_ECC_CK 35
+#define FM_NFI1X_CK 36
+#define FM_SPINFI_BCLK_CK 37
+#define FM_NETSYS_CK 38
+#define FM_MEDSYS_CK 39
+#define FM_HSM_CRYPTO_CK 40
+#define FM_HSM_ARC_CK 41
+#define FM_EIP97_CK 42
+#define FM_SNPS_ETH_312P5M_CK 43
+#define FM_SNPS_ETH_250M_CK 44
+#define FM_SNPS_PTP_CK 45
+#define FM_SNPS_ETH_50M_RMII_CK 46
+#define FM_NETSYS_500M_CK 47
+#define FM_NETSYS_MED_MCU_CK 48
+#define FM_NETSYS_WED_MCU_CK 49
+#define FM_NETSYS_2X_CK 50
+#define FM_SGMII_CK 51
+#define FM_SGMII_SBUS_CK 52
+/* ABIST Part */
+#define FM_APLL1_CK 2
+#define FM_APLL2_CK 3
+#define FM_APPLLGP_MON_FM_CK 4
+#define FM_ARMPLL_LL_CK 10
+#define FM_CCIPLL_CK 11
+#define FM_NET1PLL_CK 12
+#define FM_NET2PLL_CK 13
+#define FM_WEDMCUPLL_CK 14
+#define FM_MEDMCUPLL_CK 15
+#define FM_SGMIIPLL_CK 16
+#define FM_SNPSETHPLL_CK 17
+#define FM_DSI0_LNTC_DSICLK 20
+#define FM_DSI0_MPPLL_TST_CK 21
+#define FM_MDPLL1_FS26M_DRF_GUIDE 22
+#define FM_MFG_CK 23
+#define FM_MAINPLL_CK 24
+#define FM_MDPLL1_FS26M_GUIDE 25
+#define FM_MFGPLL_CK 26
+#define FM_MMPLL_CK 27
+#define FM_MMPLL_D3_CK 28
+#define FM_MPLL_CK 29
+#define FM_MSDCPLL_CK 30
+#define FM_RCLRPLL_DIV4_CK 31
+#define FM_RPHYPLL_DIV4_CK 33
+#define FM_ULPOSC_CK 37
+#define FM_UNIVPLL_CK 38
+#define FMEM_AFT_CH0 43
+#define FMEM_AFT_CH1 44
+#define FM_TRNG_FREQ_DEBUG_OUT0 45
+#define FM_TRNG_FREQ_DEBUG_OUT1 46
+#define FMEM_BFE_CH0 47
+#define FMEM_BFE_CH1 48
+#define FM_466M_FMEM_INFRASYS 49
+#define FM_MCUSYS_ARM_OUT_ALL 50
+#define FM_RTC32K_I_VAO 57
+/* ABIST2 Part */
+//#define FM_MCUPM_CK 13
+//#define FM_SFLASH_CK 14
+#define FM_UNIPLL_SES_CK 15
+//#define FM_ULPOSC_CK 16
+#define FM_ULPOSC_CORE_CK 17
+#define FM_SRCK_CK 18
+#define FM_MAINPLL_H728M_CK 19
+#define FM_MAINPLL_H546M_CK 20
+#define FM_MAINPLL_H436P8M_CK 21
+#define FM_MAINPLL_H364M_CK 22
+#define FM_MAINPLL_H312M_CK 23
+#define FM_UNIVPLL_1248M_CK 24
+#define FM_UNIVPLL_832M_CK 25
+#define FM_UNIVPLL_624M_CK 26
+#define FM_UNIVPLL_499M_CK 27
+#define FM_UNIVPLL_416M_CK 28
+#define FM_UNIVPLL_356P6M_CK 29
+//#define FM_MMPLL_D3_CK 30
+#define FM_MMPLL_D4_CK 31
+#define FM_MMPLL_D5_CK 32
+#define FM_MMPLL_D6_CK 33
+#define FM_MMPLL_D7_CK 34
+#define FM_MMPLL_D9_CK 35
+//#define FM_NET1PLL_CK 36
+//#define FM_NET2PLL_CK 37
+//#define FM_WEDMCUPLL_CK 38
+//#define FM_MEDMCUPLL_CK 39
+//#define FM_SGMIIPLL_CK 40
+
+#endif /* _CLK_MT6880_FMETER_H */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-gce.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-gce.c
new file mode 100755
index 0000000..57e4896
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-gce.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6880-clk.h>
+
+#define MT_CLKMGR_MODULE_INIT 0
+
+#define MT_CCF_BRINGUP 1
+
+#define INV_OFS -1
+
+
+
+static const struct mtk_gate_regs gce_cg_regs = {
+ .set_ofs = 0xf0,
+ .clr_ofs = 0xf0,
+ .sta_ofs = 0xf0,
+};
+
+#define GATE_GCE(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &gce_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+static const struct mtk_gate gce_clks[] = {
+ GATE_GCE(CLK_GCE_0, "gce_0",
+ "axi_ck"/* parent */, 16),
+};
+
+static int clk_mt6880_gce_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_GCE_NR_CLK);
+
+ mtk_clk_register_gates(node, gce_clks, ARRAY_SIZE(gce_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt6880_gce[] = {
+ { .compatible = "mediatek,mt6880-gce", },
+ {}
+};
+
+#if MT_CLKMGR_MODULE_INIT
+
+static struct platform_driver clk_mt6880_gce_drv = {
+ .probe = clk_mt6880_gce_probe,
+ .driver = {
+ .name = "clk-mt6880-gce",
+ .of_match_table = of_match_clk_mt6880_gce,
+ },
+};
+
+builtin_platform_driver(clk_mt6880_gce_drv);
+
+#else
+
+static struct platform_driver clk_mt6880_gce_drv = {
+ .probe = clk_mt6880_gce_probe,
+ .driver = {
+ .name = "clk-mt6880-gce",
+ .of_match_table = of_match_clk_mt6880_gce,
+ },
+};
+static int __init clk_mt6880_gce_platform_init(void)
+{
+ return platform_driver_register(&clk_mt6880_gce_drv);
+}
+arch_initcall(clk_mt6880_gce_platform_init);
+
+#endif /* MT_CLKMGR_MODULE_INIT */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-impe.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-impe.c
new file mode 100755
index 0000000..da92a3e
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-impe.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6880-clk.h>
+
+#define MT_CLKMGR_MODULE_INIT 0
+
+#define MT_CCF_BRINGUP 1
+
+#define INV_OFS -1
+
+
+
+static const struct mtk_gate_regs impe_cg_regs = {
+ .set_ofs = 0xe00,
+ .clr_ofs = 0xe00,
+ .sta_ofs = 0xe00,
+};
+
+#define GATE_IMPE(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &impe_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+static const struct mtk_gate impe_clks[] = {
+ GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C0_RO, "impe_i2c0_ro",
+ "i2c_ck"/* parent */, 0),
+ GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C1_RO, "impe_i2c1_ro",
+ "i2c_ck"/* parent */, 1),
+ GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C2_RO, "impe_i2c2_ro",
+ "i2c_ck"/* parent */, 2),
+ GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C3_RO, "impe_i2c3_ro",
+ "i2c_ck"/* parent */, 3),
+ GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C4_RO, "impe_i2c4_ro",
+ "i2c_ck"/* parent */, 4),
+ GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C5_RO, "impe_i2c5_ro",
+ "i2c_ck"/* parent */, 5),
+};
+
+static int clk_mt6880_impe_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_IMPE_NR_CLK);
+
+ mtk_clk_register_gates(node, impe_clks, ARRAY_SIZE(impe_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt6880_impe[] = {
+ { .compatible = "mediatek,mt6880-imp_iic_wrap_e", },
+ {}
+};
+
+#if MT_CLKMGR_MODULE_INIT
+
+static struct platform_driver clk_mt6880_impe_drv = {
+ .probe = clk_mt6880_impe_probe,
+ .driver = {
+ .name = "clk-mt6880-impe",
+ .of_match_table = of_match_clk_mt6880_impe,
+ },
+};
+
+builtin_platform_driver(clk_mt6880_impe_drv);
+
+#else
+
+static struct platform_driver clk_mt6880_impe_drv = {
+ .probe = clk_mt6880_impe_probe,
+ .driver = {
+ .name = "clk-mt6880-impe",
+ .of_match_table = of_match_clk_mt6880_impe,
+ },
+};
+static int __init clk_mt6880_impe_platform_init(void)
+{
+ return platform_driver_register(&clk_mt6880_impe_drv);
+}
+arch_initcall(clk_mt6880_impe_platform_init);
+
+#endif /* MT_CLKMGR_MODULE_INIT */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-mfgcfg.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-mfgcfg.c
new file mode 100755
index 0000000..1744146
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-mfgcfg.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6880-clk.h>
+
+#define MT_CLKMGR_MODULE_INIT 0
+
+#define MT_CCF_BRINGUP 1
+
+#define INV_OFS -1
+
+/* get spm power status struct to register inside clk_data */
+static struct pwr_status pwr_stat = GATE_PWR_STAT(0x16C,
+ 0x170, INV_OFS, BIT(2), BIT(2));
+
+static const struct mtk_gate_regs mfgcfg_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_MFGCFG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mfgcfg_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ .pwr_stat = &pwr_stat, \
+ }
+
+static const struct mtk_gate mfgcfg_clks[] = {
+ GATE_MFGCFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d",
+ "mfg_ck"/* parent */, 0),
+};
+
+static int clk_mt6880_mfgcfg_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
+
+ mtk_clk_register_gates(node, mfgcfg_clks, ARRAY_SIZE(mfgcfg_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt6880_mfgcfg[] = {
+ { .compatible = "mediatek,mt6880-mfgsys", },
+ {}
+};
+
+#if MT_CLKMGR_MODULE_INIT
+
+static struct platform_driver clk_mt6880_mfgcfg_drv = {
+ .probe = clk_mt6880_mfgcfg_probe,
+ .driver = {
+ .name = "clk-mt6880-mfgcfg",
+ .of_match_table = of_match_clk_mt6880_mfgcfg,
+ },
+};
+
+builtin_platform_driver(clk_mt6880_mfgcfg_drv);
+
+#else
+
+static struct platform_driver clk_mt6880_mfgcfg_drv = {
+ .probe = clk_mt6880_mfgcfg_probe,
+ .driver = {
+ .name = "clk-mt6880-mfgcfg",
+ .of_match_table = of_match_clk_mt6880_mfgcfg,
+ },
+};
+static int __init clk_mt6880_mfgcfg_platform_init(void)
+{
+ return platform_driver_register(&clk_mt6880_mfgcfg_drv);
+}
+arch_initcall(clk_mt6880_mfgcfg_platform_init);
+
+#endif /* MT_CLKMGR_MODULE_INIT */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-mm.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-mm.c
new file mode 100755
index 0000000..7cc1f1d
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880-mm.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6880-clk.h>
+
+#define MT_CLKMGR_MODULE_INIT 0
+
+#define MT_CCF_BRINGUP 1
+
+#define INV_OFS -1
+
+
+
+static const struct mtk_gate_regs mm_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+#define GATE_MM(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate mm_clks[] = {
+ GATE_MM(CLK_MMSYS_MUTEX0, "mmsys_mutex0",
+ "mm_ck"/* parent */, 0),
+ GATE_MM(CLK_MMSYS_APB_BUS, "mmsys_apb_bus",
+ "mm_ck"/* parent */, 1),
+ GATE_MM(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0",
+ "mm_ck"/* parent */, 2),
+ GATE_MM(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0",
+ "mm_ck"/* parent */, 3),
+ GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0",
+ "mm_ck"/* parent */, 4),
+ GATE_MM(CLK_MM_DISP_COLOR0, "mm_disp_color0",
+ "mm_ck"/* parent */, 5),
+ GATE_MM(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0",
+ "mm_ck"/* parent */, 6),
+ GATE_MM(CLK_MM_DISP_AAL0, "mm_disp_aal0",
+ "mm_ck"/* parent */, 7),
+ GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0",
+ "mm_ck"/* parent */, 8),
+ GATE_MM(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0",
+ "mm_ck"/* parent */, 9),
+ GATE_MM(CLK_MMSYS_FAKE_ENG0, "mmsys_fake_eng0",
+ "mm_ck"/* parent */, 10),
+ GATE_MM(CLK_MM_DISP_DITHER0, "mm_disp_dither0",
+ "mm_ck"/* parent */, 11),
+ GATE_MM(CLK_MM_DISP_WDMA0, "mm_disp_wdma0",
+ "mm_ck"/* parent */, 12),
+ GATE_MM(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0",
+ "mm_ck"/* parent */, 13),
+ GATE_MM(CLK_MM_DISP_OVL0, "mm_disp_ovl0",
+ "mm_ck"/* parent */, 14),
+ GATE_MM(CLK_MM_DBPI0, "mm_dbpi0",
+ "mm_ck"/* parent */, 15),
+ GATE_MM(CLK_MM_DISP_DSI0, "mm_disp_dsi0",
+ "mm_ck"/* parent */, 16),
+ GATE_MM(CLK_MMSYS_SMI_COMMON, "mmsys_smi_common",
+ "mm_ck"/* parent */, 17),
+};
+
+static int clk_mt6880_mm_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+
+ mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt6880_mm[] = {
+ { .compatible = "mediatek,mt6880-mmsys_config", },
+ {}
+};
+
+#if MT_CLKMGR_MODULE_INIT
+
+static struct platform_driver clk_mt6880_mm_drv = {
+ .probe = clk_mt6880_mm_probe,
+ .driver = {
+ .name = "clk-mt6880-mm",
+ .of_match_table = of_match_clk_mt6880_mm,
+ },
+};
+
+builtin_platform_driver(clk_mt6880_mm_drv);
+
+#else
+
+static struct platform_driver clk_mt6880_mm_drv = {
+ .probe = clk_mt6880_mm_probe,
+ .driver = {
+ .name = "clk-mt6880-mm",
+ .of_match_table = of_match_clk_mt6880_mm,
+ },
+};
+static int __init clk_mt6880_mm_platform_init(void)
+{
+ return platform_driver_register(&clk_mt6880_mm_drv);
+}
+arch_initcall(clk_mt6880_mm_platform_init);
+
+#endif /* MT_CLKMGR_MODULE_INIT */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880.c
new file mode 100755
index 0000000..7a6694a
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6880.c
@@ -0,0 +1,2608 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/seq_file.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-gate.h"
+#include "clkdbg.h"
+#include "clkdbg-mt6880.h"
+
+#include <dt-bindings/clock/mt6880-clk.h>
+
+/* bringup config */
+#define MT_CCF_BRINGUP 1
+#define MT_CCF_MUX_DISABLE 0
+#define MT_CCF_PLL_DISABLE 0
+
+/* Regular Number Definition */
+#define INV_OFS -1
+#define INV_BIT -1
+
+/* TOPCK MUX SEL REG */
+#define CLK_CFG_UPDATE 0x04
+#define CLK_CFG_UPDATE1 0x08
+#define CLK_CFG_0 0x0010
+#define CLK_CFG_0_SET 0x0014
+#define CLK_CFG_0_CLR 0x0018
+#define CLK_CFG_1 0x0020
+#define CLK_CFG_1_SET 0x0024
+#define CLK_CFG_1_CLR 0x0028
+#define CLK_CFG_2 0x0030
+#define CLK_CFG_2_SET 0x0034
+#define CLK_CFG_2_CLR 0x0038
+#define CLK_CFG_3 0x0040
+#define CLK_CFG_3_SET 0x0044
+#define CLK_CFG_3_CLR 0x0048
+#define CLK_CFG_4 0x0050
+#define CLK_CFG_4_SET 0x0054
+#define CLK_CFG_4_CLR 0x0058
+#define CLK_CFG_5 0x0060
+#define CLK_CFG_5_SET 0x0064
+#define CLK_CFG_5_CLR 0x0068
+#define CLK_CFG_6 0x0070
+#define CLK_CFG_6_SET 0x0074
+#define CLK_CFG_6_CLR 0x0078
+#define CLK_CFG_7 0x0080
+#define CLK_CFG_7_SET 0x0084
+#define CLK_CFG_7_CLR 0x0088
+#define CLK_CFG_8 0x0090
+#define CLK_CFG_8_SET 0x0094
+#define CLK_CFG_8_CLR 0x0098
+#define CLK_CFG_9 0x00A0
+#define CLK_CFG_9_SET 0x00A4
+#define CLK_CFG_9_CLR 0x00A8
+#define CLK_CFG_10 0x00B0
+#define CLK_CFG_10_SET 0x00B4
+#define CLK_CFG_10_CLR 0x00B8
+#define CLK_CFG_11 0x00C0
+#define CLK_CFG_11_SET 0x00C4
+#define CLK_CFG_11_CLR 0x00C8
+#define CLK_CFG_12 0x00D0
+#define CLK_CFG_12_SET 0x00D4
+#define CLK_CFG_12_CLR 0x00D8
+#define CLK_AUDDIV_0 0x0320
+
+/* TOPCK MUX SHIFT */
+#define TOP_MUX_AXI_SHIFT 0
+#define TOP_MUX_SPM_SHIFT 1
+#define TOP_MUX_BUS_AXIMEM_SHIFT 2
+#define TOP_MUX_MM_SHIFT 3
+#define TOP_MUX_MFG_REF_SHIFT 4
+#define TOP_MUX_UART_SHIFT 5
+#define TOP_MUX_MSDC50_0_HCLK_SHIFT 6
+#define TOP_MUX_MSDC50_0_SHIFT 7
+#define TOP_MUX_MSDC30_1_SHIFT 8
+#define TOP_MUX_AUDIO_SHIFT 9
+#define TOP_MUX_AUD_INTBUS_SHIFT 10
+#define TOP_MUX_AUD_ENGEN1_SHIFT 11
+#define TOP_MUX_AUD_ENGEN2_SHIFT 12
+#define TOP_MUX_AUD_1_SHIFT 13
+#define TOP_MUX_AUD_2_SHIFT 14
+#define TOP_MUX_PWRAP_ULPOSC_SHIFT 15
+#define TOP_MUX_ATB_SHIFT 16
+#define TOP_MUX_PWRMCU_SHIFT 17
+#define TOP_MUX_DBI_SHIFT 18
+#define TOP_MUX_DISP_PWM_SHIFT 19
+#define TOP_MUX_USB_TOP_SHIFT 20
+#define TOP_MUX_SSUSB_XHCI_SHIFT 21
+#define TOP_MUX_I2C_SHIFT 22
+#define TOP_MUX_TL_SHIFT 23
+#define TOP_MUX_DPMAIF_MAIN_SHIFT 24
+#define TOP_MUX_PWM_SHIFT 25
+#define TOP_MUX_SPMI_M_MST_SHIFT 26
+#define TOP_MUX_SPMI_P_MST_SHIFT 27
+#define TOP_MUX_DVFSRC_SHIFT 28
+#define TOP_MUX_MCUPM_SHIFT 29
+#define TOP_MUX_SFLASH_SHIFT 30
+#define TOP_MUX_GCPU_SHIFT 0
+#define TOP_MUX_SPI_SHIFT 1
+#define TOP_MUX_SPIS_SHIFT 2
+#define TOP_MUX_ECC_SHIFT 3
+#define TOP_MUX_NFI1X_SHIFT 4
+#define TOP_MUX_SPINFI_BCLK_SHIFT 5
+#define TOP_MUX_NETSYS_SHIFT 6
+#define TOP_MUX_MEDSYS_SHIFT 7
+#define TOP_MUX_HSM_CRYPTO_SHIFT 8
+#define TOP_MUX_HSM_ARC_SHIFT 9
+#define TOP_MUX_EIP97_SHIFT 10
+#define TOP_MUX_SNPS_ETH_312P5M_SHIFT 11
+#define TOP_MUX_SNPS_ETH_250M_SHIFT 12
+#define TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT 13
+#define TOP_MUX_SNPS_ETH_50M_RMII_SHIFT 14
+#define TOP_MUX_NETSYS_500M_SHIFT 15
+#define TOP_MUX_NETSYS_MED_MCU_SHIFT 16
+#define TOP_MUX_NETSYS_WED_MCU_SHIFT 17
+#define TOP_MUX_NETSYS_2X_SHIFT 18
+#define TOP_MUX_SGMII_SHIFT 19
+#define TOP_MUX_SGMII_SBUS_SHIFT 20
+
+/* TOPCK DIVIDER REG */
+#define CLK_AUDDIV_2 0x0328
+#define CLK_AUDDIV_3 0x0334
+
+/* APMIXED PLL REG */
+#define ARMPLL_LL_CON0 0x204
+#define ARMPLL_LL_CON1 0x208
+#define ARMPLL_LL_CON2 0x20c
+#define ARMPLL_LL_CON3 0x210
+#define ARMPLL_LL_CON4 0x214
+#define CCIPLL_CON0 0x218
+#define CCIPLL_CON1 0x21c
+#define CCIPLL_CON2 0x220
+#define CCIPLL_CON3 0x224
+#define CCIPLL_CON4 0x228
+#define MPLL_CON0 0x604
+#define MPLL_CON1 0x608
+#define MPLL_CON2 0x60c
+#define MPLL_CON3 0x610
+#define MPLL_CON4 0x614
+#define MAINPLL_CON0 0x404
+#define MAINPLL_CON1 0x408
+#define MAINPLL_CON2 0x40c
+#define MAINPLL_CON3 0x410
+#define MAINPLL_CON4 0x414
+#define UNIVPLL_CON0 0x418
+#define UNIVPLL_CON1 0x41c
+#define UNIVPLL_CON2 0x420
+#define UNIVPLL_CON3 0x424
+#define UNIVPLL_CON4 0x428
+#define MSDCPLL_CON0 0x22c
+#define MSDCPLL_CON1 0x230
+#define MSDCPLL_CON2 0x234
+#define MSDCPLL_CON3 0x238
+#define MSDCPLL_CON4 0x23c
+#define MMPLL_CON0 0x42c
+#define MMPLL_CON1 0x430
+#define MMPLL_CON2 0x434
+#define MMPLL_CON3 0x438
+#define MMPLL_CON4 0x43c
+#define MFGPLL_CON0 0x618
+#define MFGPLL_CON1 0x61c
+#define MFGPLL_CON2 0x620
+#define MFGPLL_CON3 0x624
+#define MFGPLL_CON4 0x628
+#define APLL1_CON0 0x454
+#define APLL1_CON1 0x458
+#define APLL1_CON2 0x45c
+#define APLL1_CON3 0x460
+#define APLL1_CON4 0x464
+#define APLL1_CON5 0x468
+#define APLL2_CON0 0x46c
+#define APLL2_CON1 0x470
+#define APLL2_CON2 0x474
+#define APLL2_CON3 0x478
+#define APLL2_CON4 0x47c
+#define APLL2_CON5 0x480
+#define NET1PLL_CON0 0x804
+#define NET1PLL_CON1 0x808
+#define NET1PLL_CON2 0x80c
+#define NET1PLL_CON3 0x810
+#define NET1PLL_CON4 0x814
+#define NET2PLL_CON0 0x818
+#define NET2PLL_CON1 0x81c
+#define NET2PLL_CON2 0x820
+#define NET2PLL_CON3 0x824
+#define NET2PLL_CON4 0x828
+#define WEDMCUPLL_CON0 0x82c
+#define WEDMCUPLL_CON1 0x830
+#define WEDMCUPLL_CON2 0x834
+#define WEDMCUPLL_CON3 0x838
+#define WEDMCUPLL_CON4 0x83c
+#define MEDMCUPLL_CON0 0x840
+#define MEDMCUPLL_CON1 0x844
+#define MEDMCUPLL_CON2 0x848
+#define MEDMCUPLL_CON3 0x84c
+#define MEDMCUPLL_CON4 0x850
+#define SGMIIPLL_CON0 0x240
+#define SGMIIPLL_CON1 0x244
+#define SGMIIPLL_CON2 0x248
+#define SGMIIPLL_CON3 0x24c
+#define SGMIIPLL_CON4 0x250
+#define APLL1_TUNER_CON0 0x0054
+#define APLL2_TUNER_CON0 0x0058
+#define AP_PLL_CON0 0x0
+
+static DEFINE_SPINLOCK(mt6880_clk_lock);
+
+static void __iomem *apmixed_base;
+
+static const struct mtk_fixed_factor top_divs[] = {
+ FACTOR(CLK_TOP_ARMPLL_LL_CK_VRPOC, "armpll_ll_vrpoc",
+ "armpll_ll", 1, 1),
+ FACTOR(CLK_TOP_CCIPLL_CK_VRPOC_CCI, "ccipll_vrpoc_cci",
+ "ccipll", 1, 1),
+ FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck",
+ "mfgpll", 1, 1),
+ FACTOR(CLK_TOP_MAINPLL, "mainpll_ck",
+ "mainpll", 1, 1),
+ FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3",
+ "mainpll", 1, 3),
+ FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4",
+ "mainpll", 1, 4),
+ FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2",
+ "mainpll", 1, 8),
+ FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4",
+ "mainpll", 1, 16),
+ FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8",
+ "mainpll", 1, 32),
+ FACTOR(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16",
+ "mainpll", 1, 64),
+ FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5",
+ "mainpll", 1, 5),
+ FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2",
+ "mainpll", 1, 10),
+ FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4",
+ "mainpll", 1, 20),
+ FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8",
+ "mainpll", 1, 40),
+ FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6",
+ "mainpll", 1, 6),
+ FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2",
+ "mainpll", 1, 12),
+ FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4",
+ "mainpll", 1, 24),
+ FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8",
+ "mainpll", 1, 48),
+ FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7",
+ "mainpll", 1, 7),
+ FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2",
+ "mainpll", 1, 14),
+ FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4",
+ "mainpll", 1, 28),
+ FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8",
+ "mainpll", 1, 56),
+ FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8",
+ "mainpll", 1, 8),
+ FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9",
+ "mainpll", 1, 9),
+ FACTOR(CLK_TOP_UNIVPLL, "univpll_ck",
+ "univpll", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2",
+ "univpll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3",
+ "univpll", 1, 3),
+ FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4",
+ "univpll", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2",
+ "univpll", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4",
+ "univpll", 1, 16),
+ FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8",
+ "univpll", 1, 32),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5",
+ "univpll", 1, 5),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2",
+ "univpll", 1, 10),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4",
+ "univpll", 1, 20),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8",
+ "univpll", 1, 40),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D16, "univpll_d5_d16",
+ "univpll", 1, 80),
+ FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6",
+ "univpll", 1, 6),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2",
+ "univpll", 1, 12),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4",
+ "univpll", 1, 24),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8",
+ "univpll", 1, 48),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16",
+ "univpll", 1, 96),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7",
+ "univpll", 1, 7),
+ FACTOR(CLK_TOP_UNIVPLL_D7_D2, "univpll_d7_d2",
+ "univpll", 1, 14),
+ FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m_ck",
+ "univpll", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2",
+ "univpll", 1, 26),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4",
+ "univpll", 1, 52),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8",
+ "univpll", 1, 104),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16",
+ "univpll", 1, 208),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32",
+ "univpll", 1, 416),
+ FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck",
+ "univpll", 1, 13),
+ FACTOR(CLK_TOP_USB20_PLL_D2, "usb20_pll_d2",
+ "univpll", 1, 26),
+ FACTOR(CLK_TOP_USB20_PLL_D4, "usb20_pll_d4",
+ "univpll", 1, 52),
+ FACTOR(CLK_TOP_APLL1, "apll1_ck",
+ "apll1", 1, 1),
+ FACTOR(CLK_TOP_APLL1_D2, "apll1_d2",
+ "apll1", 1, 2),
+ FACTOR(CLK_TOP_APLL1_D4, "apll1_d4",
+ "apll1", 1, 4),
+ FACTOR(CLK_TOP_APLL1_D8, "apll1_d8",
+ "apll1", 1, 8),
+ FACTOR(CLK_TOP_APLL2, "apll2_ck",
+ "apll2", 1, 1),
+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2",
+ "apll2", 1, 2),
+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4",
+ "apll2", 1, 4),
+ FACTOR(CLK_TOP_APLL2_D8, "apll2_d8",
+ "apll2", 1, 8),
+ FACTOR(CLK_TOP_MMPLL, "mmpll_ck",
+ "mmpll", 1, 1),
+ FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3",
+ "mmpll", 1, 3),
+ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4",
+ "mmpll", 1, 4),
+ FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2",
+ "mmpll", 1, 8),
+ FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4",
+ "mmpll", 1, 16),
+ FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5",
+ "mmpll", 1, 5),
+ FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2",
+ "mmpll", 1, 10),
+ FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4",
+ "mmpll", 1, 20),
+ FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6",
+ "mmpll", 1, 6),
+ FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2",
+ "mmpll", 1, 12),
+ FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7",
+ "mmpll", 1, 7),
+ FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9",
+ "mmpll", 1, 9),
+ FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck",
+ "net1pll", 1, 1),
+ FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2",
+ "net1pll", 1, 2),
+ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4",
+ "net1pll", 1, 4),
+ FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8",
+ "net1pll", 1, 8),
+ FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16",
+ "net1pll", 1, 16),
+ FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck",
+ "msdcpll", 1, 1),
+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2",
+ "msdcpll", 1, 2),
+ FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4",
+ "msdcpll", 1, 4),
+ FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8",
+ "msdcpll", 1, 8),
+ FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16",
+ "msdcpll", 1, 16),
+ FACTOR(CLK_TOP_CLKRTC, "clkrtc",
+ "clk32k", 1, 1),
+ FACTOR(CLK_TOP_TCK_26M_MX8, "tck_26m_mx8_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_TCK_26M_MX9, "tck_26m_mx9_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_TCK_26M_MX10, "tck_26m_mx10_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_TCK_26M_MX11, "tck_26m_mx11_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_TCK_26M_MX12, "tck_26m_mx12_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_CSW_FAXI, "csw_faxi_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_CSW_F26M_CK_D52, "csw_f26m_d52",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_CSW_F26M_CK_D2, "csw_f26m_d2",
+ "clk26m", 1, 2),
+ FACTOR(CLK_TOP_OSC, "osc_ck",
+ "ulposc", 1, 1),
+ FACTOR(CLK_TOP_OSC_D2, "osc_d2",
+ "ulposc", 1, 2),
+ FACTOR(CLK_TOP_OSC_D4, "osc_d4",
+ "ulposc", 1, 4),
+ FACTOR(CLK_TOP_OSC_D8, "osc_d8",
+ "ulposc", 1, 8),
+ FACTOR(CLK_TOP_OSC_D16, "osc_d16",
+ "ulposc", 1, 16),
+ FACTOR(CLK_TOP_OSC_D10, "osc_d10",
+ "ulposc", 1, 10),
+ FACTOR(CLK_TOP_OSC_D20, "osc_d20",
+ "ulposc", 1, 20),
+ FACTOR(CLK_TOP_TVDPLL_D5, "tvdpll_d5",
+ "net1pll", 1, 5),
+ FACTOR(CLK_TOP_TVDPLL_D10, "tvdpll_d10",
+ "net1pll", 1, 10),
+ FACTOR(CLK_TOP_TVDPLL_D25, "tvdpll_d25",
+ "net1pll", 1, 25),
+ FACTOR(CLK_TOP_TVDPLL_D50, "tvdpll_d50",
+ "net1pll", 1, 50),
+ FACTOR(CLK_TOP_NET2PLL, "net2pll_ck",
+ "net2pll", 1, 1),
+ FACTOR(CLK_TOP_WEDMCUPLL, "wedmcupll_ck",
+ "wedmcupll", 1, 1),
+ FACTOR(CLK_TOP_MEDMCUPLL, "medmcupll_ck",
+ "medmcupll", 1, 1),
+ FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck",
+ "sgmiipll", 1, 1),
+ FACTOR(CLK_TOP_F26M, "f26m_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_FRTC, "frtc_ck",
+ "clk32k", 1, 1),
+ FACTOR(CLK_TOP_AXI, "axi_ck",
+ "axi_sel", 1, 1),
+ FACTOR(CLK_TOP_SPM, "spm_ck",
+ "spm_sel", 1, 1),
+ FACTOR(CLK_TOP_BUS, "bus_ck",
+ "bus_aximem_sel", 1, 1),
+ FACTOR(CLK_TOP_MM, "mm_ck",
+ "mm_sel", 1, 1),
+ FACTOR(CLK_TOP_MFG_REF, "mfg_ref_ck",
+ "mfg_ref_sel", 1, 1),
+ FACTOR(CLK_TOP_MFG, "mfg_ck",
+ "mfg_sel", 1, 1),
+ FACTOR(CLK_TOP_FUART, "fuart_ck",
+ "uart_sel", 1, 1),
+ FACTOR(CLK_TOP_MSDC50_0_HCLK, "msdc50_0_h_ck",
+ "msdc50_0_h_sel", 1, 1),
+ FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck",
+ "msdc50_0_sel", 1, 1),
+ FACTOR(CLK_TOP_MSDC30_1, "msdc30_1_ck",
+ "msdc30_1_sel", 1, 1),
+ FACTOR(CLK_TOP_AUDIO, "audio_ck",
+ "audio_sel", 1, 1),
+ FACTOR(CLK_TOP_AUD_INTBUS, "aud_intbus_ck",
+ "aud_intbus_sel", 1, 1),
+ FACTOR(CLK_TOP_AUD_ENGEN1, "aud_engen1_ck",
+ "aud_engen1_sel", 1, 1),
+ FACTOR(CLK_TOP_AUD_ENGEN2, "aud_engen2_ck",
+ "aud_engen2_sel", 1, 1),
+ FACTOR(CLK_TOP_AUD_1, "aud_1_ck",
+ "aud_1_sel", 1, 1),
+ FACTOR(CLK_TOP_AUD_2, "aud_2_ck",
+ "aud_2_sel", 1, 1),
+ FACTOR(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_ck",
+ "pwrap_ulposc_sel", 1, 1),
+ FACTOR(CLK_TOP_ATB, "atb_ck",
+ "atb_sel", 1, 1),
+ FACTOR(CLK_TOP_PWRMCU, "pwrmcu_ck",
+ "pwrmcu_sel", 1, 1),
+ FACTOR(CLK_TOP_DBI, "dbi_ck",
+ "dbi_sel", 1, 1),
+ FACTOR(CLK_TOP_FDISP_PWM, "fdisp_pwm_ck",
+ "disp_pwm_sel", 1, 1),
+ FACTOR(CLK_TOP_FUSB_TOP, "fusb_ck",
+ "usb_sel", 1, 1),
+ FACTOR(CLK_TOP_FSSUSB_XHCI, "fssusb_xhci_ck",
+ "ssusb_xhci_sel", 1, 1),
+ FACTOR(CLK_TOP_I2C, "i2c_ck",
+ "i2c_sel", 1, 1),
+ FACTOR(CLK_TOP_TL, "tl_ck",
+ "tl_sel", 1, 1),
+ FACTOR(CLK_TOP_DPMAIF_MAIN, "dpmaif_main_ck",
+ "dpmaif_main_sel", 1, 1),
+ FACTOR(CLK_TOP_PWM, "pwm_ck",
+ "pwm_sel", 1, 1),
+ FACTOR(CLK_TOP_SPMI_M_MST, "spmi_m_mst_ck",
+ "spmi_m_mst_sel", 1, 1),
+ FACTOR(CLK_TOP_SPMI_P_MST, "spmi_p_mst_ck",
+ "spmi_p_mst_sel", 1, 1),
+ FACTOR(CLK_TOP_DVFSRC, "dvfsrc_ck",
+ "dvfsrc_sel", 1, 1),
+ FACTOR(CLK_TOP_MCUPM, "mcupm_ck",
+ "mcupm_sel", 1, 1),
+ FACTOR(CLK_TOP_SFLASH, "sflash_ck",
+ "sflash_sel", 1, 1),
+ FACTOR(CLK_TOP_GCPU, "gcpu_ck",
+ "gcpu_sel", 1, 1),
+ FACTOR(CLK_TOP_SPI, "spi_ck",
+ "spi_sel", 1, 1),
+ FACTOR(CLK_TOP_SPIS, "spis_ck",
+ "spis_sel", 1, 1),
+ FACTOR(CLK_TOP_ECC, "ecc_ck",
+ "ecc_sel", 1, 1),
+ FACTOR(CLK_TOP_NFI1X, "nfi1x_ck",
+ "nfi1x_sel", 1, 1),
+ FACTOR(CLK_TOP_SPINFI_BCLK, "spinfi_bclk_ck",
+ "spinfi_bclk_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS, "netsys_ck",
+ "netsys_sel", 1, 1),
+ FACTOR(CLK_TOP_MEDSYS, "medsys_ck",
+ "medsys_sel", 1, 1),
+ FACTOR(CLK_TOP_HSM_CRYPTO, "hsm_crypto_ck",
+ "hsm_crypto_sel", 1, 1),
+ FACTOR(CLK_TOP_HSM_ARC, "hsm_arc_ck",
+ "hsm_arc_sel", 1, 1),
+ FACTOR(CLK_TOP_EIP97, "eip97_ck",
+ "eip97_sel", 1, 1),
+ FACTOR(CLK_TOP_SNPS_ETH_312P5M, "snps_eth_312p5m_ck",
+ "snps_eth_312p5m_sel", 1, 1),
+ FACTOR(CLK_TOP_SNPS_ETH_250M, "snps_eth_250m_ck",
+ "snps_eth_250m_sel", 1, 1),
+ FACTOR(CLK_TOP_SNPS_ETH_62P4M_PTP, "snps_ptp_ck",
+ "snps_ptp_sel", 1, 1),
+ FACTOR(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii_ck",
+ "snps_rmii_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m_ck",
+ "netsys_500m_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS_MED_MCU, "netsys_med_mcu_ck",
+ "netsys_med_mcu_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu_ck",
+ "netsys_wed_mcu_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x_ck",
+ "netsys_2x_sel", 1, 1),
+ FACTOR(CLK_TOP_SGMII, "sgmii_ck",
+ "sgmii_sel", 1, 1),
+ FACTOR(CLK_TOP_SGMII_SBUS, "sgmii_sbus_ck",
+ "sgmii_sbus_sel", 1, 1),
+ FACTOR(CLK_TOP_SYS_26M, "sys_26m_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_F_UFS_MP_SAP_CFG, "ufs_cfg_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_F_UFS_TICK1US, "f_ufs_tick1us_ck",
+ "clk26m", 1, 1),
+};
+
+static const char * const axi_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d4",
+ "mainpll_d7_d2",
+ "mainpll_d4_d2",
+ "mainpll_d5_d2",
+ "mainpll_d6_d2",
+ "osc_d4"
+};
+
+static const char * const spm_parents[] = {
+ "tck_26m_mx9_ck",
+ "osc_d10",
+ "mainpll_d7_d4",
+ "clkrtc"
+};
+
+static const char * const bus_aximem_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d7_d2",
+ "mainpll_d4_d2",
+ "mainpll_d5_d2",
+ "mainpll_d6"
+};
+
+static const char * const mm_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d2",
+ "univpll_d7_d2",
+ "mainpll_d6_d2",
+ "univpll_d4_d4"
+};
+
+static const char * const mfg_ref_parents[] = {
+ "tck_26m_mx9_ck",
+ "tck_26m_mx9_ck",
+ "univpll_d6",
+ "mainpll_d5_d2"
+};
+
+static const char * const mfg_parents[] = {
+ "mfg_ref_sel",
+ "mfgpll_ck"
+};
+
+static const char * const uart_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d8"
+};
+
+static const char * const msdc50_0_h_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d2",
+ "mainpll_d6_d2"
+};
+
+static const char * const msdc50_0_parents[] = {
+ "tck_26m_mx9_ck",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "univpll_d4_d4",
+ "mainpll_d6_d2",
+ "univpll_d4_d2"
+};
+
+static const char * const msdc30_1_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d2",
+ "mainpll_d6_d2",
+ "mainpll_d7_d2",
+ "msdcpll_d2"
+};
+
+static const char * const audio_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d5_d8",
+ "mainpll_d7_d8",
+ "mainpll_d4_d16"
+};
+
+static const char * const aud_intbus_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d4",
+ "mainpll_d7_d4"
+};
+
+static const char * const aud_engen1_parents[] = {
+ "tck_26m_mx9_ck",
+ "apll1_d2",
+ "apll1_d4",
+ "apll1_d8"
+};
+
+static const char * const aud_engen2_parents[] = {
+ "tck_26m_mx9_ck",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8"
+};
+
+static const char * const aud_1_parents[] = {
+ "tck_26m_mx9_ck",
+ "apll1_ck"
+};
+
+static const char * const aud_2_parents[] = {
+ "tck_26m_mx9_ck",
+ "apll2_ck"
+};
+
+static const char * const pwrap_ulposc_parents[] = {
+ "osc_d10",
+ "tck_26m_mx9_ck",
+ "osc_d4",
+ "osc_d8",
+ "osc_d16"
+};
+
+static const char * const atb_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d2",
+ "mainpll_d5_d2"
+};
+
+static const char * const pwrmcu_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d5_d2",
+ "univpll_d5_d2",
+ "mainpll_d4_d2",
+ "univpll_d4_d2",
+ "mainpll_d6"
+};
+
+static const char * const dbi_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d5_d4",
+ "univpll_d6_d4",
+ "univpll_d4_d8",
+ "univpll_d6_d8"
+};
+
+static const char * const disp_pwm_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d4",
+ "osc_d2",
+ "osc_d4",
+ "osc_d16"
+};
+
+static const char * const usb_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d5_d4",
+ "univpll_d6_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const ssusb_xhci_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d5_d4",
+ "univpll_d6_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const i2c_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d8",
+ "univpll_d5_d4"
+};
+
+static const char * const tl_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d4",
+ "mainpll_d6_d4"
+};
+
+static const char * const dpmaif_main_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d4_d4",
+ "mainpll_d6",
+ "mainpll_d4_d2",
+ "univpll_d4_d2"
+};
+
+static const char * const pwm_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d4_d8"
+};
+
+static const char * const spmi_m_mst_parents[] = {
+ "tck_26m_mx9_ck",
+ "csw_f26m_d2",
+ "osc_d8",
+ "osc_d10",
+ "osc_d16",
+ "osc_d20",
+ "clkrtc"
+};
+
+static const char * const spmi_p_mst_parents[] = {
+ "tck_26m_mx9_ck",
+ "csw_f26m_d2",
+ "osc_d8",
+ "osc_d10",
+ "osc_d16",
+ "osc_d20",
+ "clkrtc",
+ "mainpll_d7_d8",
+ "mainpll_d5_d8"
+};
+
+static const char * const dvfsrc_parents[] = {
+ "tck_26m_mx9_ck",
+ "osc_d10"
+};
+
+static const char * const mcupm_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d6_d4",
+ "mainpll_d6_d2"
+};
+
+static const char * const sflash_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d7_d8",
+ "univpll_d6_d8",
+ "univpll_d5_d8"
+};
+
+static const char * const gcpu_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6",
+ "mainpll_d6",
+ "univpll_d4_d2",
+ "mainpll_d4_d2",
+ "univpll_d6_d2"
+};
+
+static const char * const spi_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d8",
+ "univpll_d4_d8",
+ "univpll_d6_d4",
+ "univpll_d5_d4",
+ "univpll_d4_d4",
+ "univpll_d7_d2",
+ "univpll_d6_d2"
+};
+
+static const char * const spis_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d8",
+ "univpll_d4_d8",
+ "univpll_d6_d4",
+ "univpll_d4_d4",
+ "univpll_d6_d2",
+ "univpll_d4_d2",
+ "univpll_d6"
+};
+
+static const char * const ecc_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d4",
+ "mainpll_d9",
+ "univpll_d4_d2"
+};
+
+static const char * const nfi1x_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d5_d4",
+ "mainpll_d7_d4",
+ "mainpll_d6_d4",
+ "univpll_d6_d4",
+ "mainpll_d4_d4",
+ "univpll_d4_d4",
+ "mainpll_d6_d2"
+};
+
+static const char * const spinfi_bclk_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d8",
+ "univpll_d5_d8",
+ "mainpll_d4_d8",
+ "univpll_d4_d8",
+ "mainpll_d6_d4",
+ "univpll_d6_d4",
+ "univpll_d5_d4"
+};
+
+static const char * const netsys_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d4_d8",
+ "mainpll_d7_d2",
+ "mainpll_d9",
+ "univpll_d7"
+};
+
+static const char * const medsys_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d4_d8",
+ "mainpll_d7_d2",
+ "mainpll_d9",
+ "univpll_d7"
+};
+
+static const char * const hsm_crypto_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d2",
+ "mainpll_d6_d2",
+ "mainpll_d7"
+};
+
+static const char * const hsm_arc_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d8",
+ "mainpll_d4_d4",
+ "mainpll_d6_d2"
+};
+
+static const char * const eip97_parents[] = {
+ "tck_26m_mx9_ck",
+ "net2pll_ck",
+ "mainpll_d3",
+ "univpll_d4",
+ "mainpll_d4",
+ "univpll_d5",
+ "mainpll_d6",
+ "mainpll_d5_d2"
+};
+
+static const char * const snps_eth_312p5m_parents[] = {
+ "tck_26m_mx9_ck",
+ "tvdpll_d8"
+};
+
+static const char * const snps_eth_250m_parents[] = {
+ "tck_26m_mx9_ck",
+ "tvdpll_d10"
+};
+
+static const char * const snps_ptp_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d5_d8"
+};
+
+static const char * const snps_rmii_parents[] = {
+ "tck_26m_mx9_ck",
+ "tvdpll_d50"
+};
+
+static const char * const netsys_500m_parents[] = {
+ "tck_26m_mx9_ck",
+ "tvdpll_d5"
+};
+
+static const char * const netsys_med_mcu_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d4",
+ "mainpll_d4_d2",
+ "univpll_d7",
+ "medmcupll_ck"
+};
+
+static const char * const netsys_wed_mcu_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d6_d2",
+ "mainpll_d6",
+ "mainpll_d5",
+ "wedmcupll_ck"
+};
+
+static const char * const netsys_2x_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d5_d4",
+ "mainpll_d4_d2",
+ "mainpll_d4",
+ "net2pll_ck"
+};
+
+static const char * const sgmii_parents[] = {
+ "tck_26m_mx9_ck",
+ "sgmiipll_ck"
+};
+
+static const char * const sgmii_sbus_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d7_d4"
+};
+
+static const char * const apll_i2s0_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s1_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s2_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s4_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_tdmout_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s5_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s6_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const struct mtk_mux top_muxes[] = {
+#if MT_CCF_MUX_DISABLE
+ /* CLK_CFG_0 */
+ MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL/* dts */, "axi_sel",
+ axi_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AXI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPM_SEL/* dts */, "spm_sel",
+ spm_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SPM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_BUS_AXIMEM_SEL/* dts */, "bus_aximem_sel",
+ bus_aximem_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_BUS_AXIMEM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MM_SEL/* dts */, "mm_sel",
+ mm_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MM_SHIFT/* upd shift */),
+ /* CLK_CFG_1 */
+ MUX_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL/* dts */, "mfg_ref_sel",
+ mfg_ref_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MFG_REF_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MFG_SEL/* dts */, "mfg_sel",
+ mfg_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 2/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, INV_OFS/* upd ofs */,
+ INV_BIT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_UART_SEL/* dts */, "uart_sel",
+ uart_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_UART_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL/* dts */, "msdc50_0_h_sel",
+ msdc50_0_h_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MSDC50_0_HCLK_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL/* dts */, "msdc50_0_sel",
+ msdc50_0_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MSDC50_0_SHIFT/* upd shift */),
+ /* CLK_CFG_2 */
+ MUX_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL/* dts */, "msdc30_1_sel",
+ msdc30_1_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MSDC30_1_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUDIO_SEL/* dts */, "audio_sel",
+ audio_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUDIO_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL/* dts */, "aud_intbus_sel",
+ aud_intbus_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_INTBUS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL/* dts */, "aud_engen1_sel",
+ aud_engen1_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 24/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_ENGEN1_SHIFT/* upd shift */),
+ /* CLK_CFG_3 */
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL/* dts */, "aud_engen2_sel",
+ aud_engen2_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_ENGEN2_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_1_SEL/* dts */, "aud_1_sel",
+ aud_1_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_1_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_2_SEL/* dts */, "aud_2_sel",
+ aud_2_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_2_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL/* dts */, "pwrap_ulposc_sel",
+ pwrap_ulposc_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_PWRAP_ULPOSC_SHIFT/* upd shift */),
+ /* CLK_CFG_4 */
+ MUX_CLR_SET_UPD(CLK_TOP_ATB_SEL/* dts */, "atb_sel",
+ atb_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_ATB_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_PWRMCU_SEL/* dts */, "pwrmcu_sel",
+ pwrmcu_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_PWRMCU_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_DBI_SEL/* dts */, "dbi_sel",
+ dbi_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DBI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL/* dts */, "disp_pwm_sel",
+ disp_pwm_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DISP_PWM_SHIFT/* upd shift */),
+ /* CLK_CFG_5 */
+ MUX_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL/* dts */, "usb_sel",
+ usb_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_USB_TOP_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL/* dts */, "ssusb_xhci_sel",
+ ssusb_xhci_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SSUSB_XHCI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_I2C_SEL/* dts */, "i2c_sel",
+ i2c_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_I2C_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_TL_SEL/* dts */, "tl_sel",
+ tl_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 24/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_TL_SHIFT/* upd shift */),
+ /* CLK_CFG_6 */
+ MUX_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL/* dts */, "dpmaif_main_sel",
+ dpmaif_main_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DPMAIF_MAIN_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_PWM_SEL/* dts */, "pwm_sel",
+ pwm_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_PWM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPMI_M_MST_SEL/* dts */, "spmi_m_mst_sel",
+ spmi_m_mst_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SPMI_M_MST_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPMI_P_MST_SEL/* dts */, "spmi_p_mst_sel",
+ spmi_p_mst_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 24/* lsb */, 4/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SPMI_P_MST_SHIFT/* upd shift */),
+ /* CLK_CFG_7 */
+ MUX_CLR_SET_UPD(CLK_TOP_DVFSRC_SEL/* dts */, "dvfsrc_sel",
+ dvfsrc_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 0/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DVFSRC_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MCUPM_SEL/* dts */, "mcupm_sel",
+ mcupm_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MCUPM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SFLASH_SEL/* dts */, "sflash_sel",
+ sflash_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SFLASH_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_GCPU_SEL/* dts */, "gcpu_sel",
+ gcpu_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_GCPU_SHIFT/* upd shift */),
+ /* CLK_CFG_8 */
+ MUX_CLR_SET_UPD(CLK_TOP_SPI_SEL/* dts */, "spi_sel",
+ spi_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SPI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPIS_SEL/* dts */, "spis_sel",
+ spis_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SPIS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_ECC_SEL/* dts */, "ecc_sel",
+ ecc_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_ECC_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NFI1X_SEL/* dts */, "nfi1x_sel",
+ nfi1x_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NFI1X_SHIFT/* upd shift */),
+ /* CLK_CFG_9 */
+ MUX_CLR_SET_UPD(CLK_TOP_SPINFI_BCLK_SEL/* dts */, "spinfi_bclk_sel",
+ spinfi_bclk_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SPINFI_BCLK_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_SEL/* dts */, "netsys_sel",
+ netsys_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MEDSYS_SEL/* dts */, "medsys_sel",
+ medsys_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_MEDSYS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_HSM_CRYPTO_SEL/* dts */, "hsm_crypto_sel",
+ hsm_crypto_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 24/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_HSM_CRYPTO_SHIFT/* upd shift */),
+ /* CLK_CFG_10 */
+ MUX_CLR_SET_UPD(CLK_TOP_HSM_ARC_SEL/* dts */, "hsm_arc_sel",
+ hsm_arc_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_HSM_ARC_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_EIP97_SEL/* dts */, "eip97_sel",
+ eip97_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_EIP97_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_312P5M_SEL/* dts */, "snps_eth_312p5m_sel",
+ snps_eth_312p5m_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_312P5M_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M_SEL/* dts */, "snps_eth_250m_sel",
+ snps_eth_250m_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 24/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_250M_SHIFT/* upd shift */),
+ /* CLK_CFG_11 */
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP_SEL/* dts */, "snps_ptp_sel",
+ snps_ptp_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 0/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII_SEL/* dts */, "snps_rmii_sel",
+ snps_rmii_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_50M_RMII_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL/* dts */, "netsys_500m_sel",
+ netsys_500m_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_500M_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_MED_MCU_SEL/* dts */, "netsys_med_mcu_sel",
+ netsys_med_mcu_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_MED_MCU_SHIFT/* upd shift */),
+ /* CLK_CFG_12 */
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_WED_MCU_SEL/* dts */, "netsys_wed_mcu_sel",
+ netsys_wed_mcu_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_WED_MCU_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL/* dts */, "netsys_2x_sel",
+ netsys_2x_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_2X_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SGMII_SEL/* dts */, "sgmii_sel",
+ sgmii_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SGMII_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SGMII_SBUS_SEL/* dts */, "sgmii_sbus_sel",
+ sgmii_sbus_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 24/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SGMII_SBUS_SHIFT/* upd shift */),
+#else
+ /* CLK_CFG_0 */
+ MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL/* dts */, "axi_sel",
+ axi_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AXI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPM_SEL/* dts */, "spm_sel",
+ spm_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SPM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_BUS_AXIMEM_SEL/* dts */, "bus_aximem_sel",
+ bus_aximem_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_BUS_AXIMEM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MM_SEL/* dts */, "mm_sel",
+ mm_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MM_SHIFT/* upd shift */),
+ /* CLK_CFG_1 */
+ MUX_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL/* dts */, "mfg_ref_sel",
+ mfg_ref_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MFG_REF_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MFG_SEL/* dts */, "mfg_sel",
+ mfg_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 2/* lsb */, 1/* width */,
+ INV_BIT/* pdn */, INV_OFS/* upd ofs */,
+ INV_BIT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_UART_SEL/* dts */, "uart_sel",
+ uart_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_UART_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL/* dts */, "msdc50_0_h_sel",
+ msdc50_0_h_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MSDC50_0_HCLK_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL/* dts */, "msdc50_0_sel",
+ msdc50_0_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MSDC50_0_SHIFT/* upd shift */),
+ /* CLK_CFG_2 */
+ MUX_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL/* dts */, "msdc30_1_sel",
+ msdc30_1_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MSDC30_1_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUDIO_SEL/* dts */, "audio_sel",
+ audio_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUDIO_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL/* dts */, "aud_intbus_sel",
+ aud_intbus_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_INTBUS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL/* dts */, "aud_engen1_sel",
+ aud_engen1_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 24/* lsb */, 2/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_ENGEN1_SHIFT/* upd shift */),
+ /* CLK_CFG_3 */
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL/* dts */, "aud_engen2_sel",
+ aud_engen2_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_ENGEN2_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_1_SEL/* dts */, "aud_1_sel",
+ aud_1_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_1_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_2_SEL/* dts */, "aud_2_sel",
+ aud_2_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_2_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL/* dts */, "pwrap_ulposc_sel",
+ pwrap_ulposc_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_PWRAP_ULPOSC_SHIFT/* upd shift */),
+ /* CLK_CFG_4 */
+ MUX_CLR_SET_UPD(CLK_TOP_ATB_SEL/* dts */, "atb_sel",
+ atb_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_ATB_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_PWRMCU_SEL/* dts */, "pwrmcu_sel",
+ pwrmcu_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_PWRMCU_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_DBI_SEL/* dts */, "dbi_sel",
+ dbi_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DBI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL/* dts */, "disp_pwm_sel",
+ disp_pwm_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DISP_PWM_SHIFT/* upd shift */),
+ /* CLK_CFG_5 */
+ MUX_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL/* dts */, "usb_sel",
+ usb_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_USB_TOP_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL/* dts */, "ssusb_xhci_sel",
+ ssusb_xhci_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SSUSB_XHCI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_I2C_SEL/* dts */, "i2c_sel",
+ i2c_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_I2C_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_TL_SEL/* dts */, "tl_sel",
+ tl_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 24/* lsb */, 2/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_TL_SHIFT/* upd shift */),
+ /* CLK_CFG_6 */
+ MUX_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL/* dts */, "dpmaif_main_sel",
+ dpmaif_main_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DPMAIF_MAIN_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_PWM_SEL/* dts */, "pwm_sel",
+ pwm_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_PWM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPMI_M_MST_SEL/* dts */, "spmi_m_mst_sel",
+ spmi_m_mst_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SPMI_M_MST_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPMI_P_MST_SEL/* dts */, "spmi_p_mst_sel",
+ spmi_p_mst_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 24/* lsb */, 4/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SPMI_P_MST_SHIFT/* upd shift */),
+ /* CLK_CFG_7 */
+ MUX_CLR_SET_UPD(CLK_TOP_DVFSRC_SEL/* dts */, "dvfsrc_sel",
+ dvfsrc_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 0/* lsb */, 1/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DVFSRC_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MCUPM_SEL/* dts */, "mcupm_sel",
+ mcupm_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MCUPM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SFLASH_SEL/* dts */, "sflash_sel",
+ sflash_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SFLASH_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_GCPU_SEL/* dts */, "gcpu_sel",
+ gcpu_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_GCPU_SHIFT/* upd shift */),
+ /* CLK_CFG_8 */
+ MUX_CLR_SET_UPD(CLK_TOP_SPI_SEL/* dts */, "spi_sel",
+ spi_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SPI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPIS_SEL/* dts */, "spis_sel",
+ spis_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SPIS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_ECC_SEL/* dts */, "ecc_sel",
+ ecc_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_ECC_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NFI1X_SEL/* dts */, "nfi1x_sel",
+ nfi1x_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NFI1X_SHIFT/* upd shift */),
+ /* CLK_CFG_9 */
+ MUX_CLR_SET_UPD(CLK_TOP_SPINFI_BCLK_SEL/* dts */, "spinfi_bclk_sel",
+ spinfi_bclk_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SPINFI_BCLK_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_SEL/* dts */, "netsys_sel",
+ netsys_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MEDSYS_SEL/* dts */, "medsys_sel",
+ medsys_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_MEDSYS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_HSM_CRYPTO_SEL/* dts */, "hsm_crypto_sel",
+ hsm_crypto_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 24/* lsb */, 2/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_HSM_CRYPTO_SHIFT/* upd shift */),
+ /* CLK_CFG_10 */
+ MUX_CLR_SET_UPD(CLK_TOP_HSM_ARC_SEL/* dts */, "hsm_arc_sel",
+ hsm_arc_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_HSM_ARC_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_EIP97_SEL/* dts */, "eip97_sel",
+ eip97_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_EIP97_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_312P5M_SEL/* dts */, "snps_eth_312p5m_sel",
+ snps_eth_312p5m_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_312P5M_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M_SEL/* dts */, "snps_eth_250m_sel",
+ snps_eth_250m_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 24/* lsb */, 1/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_250M_SHIFT/* upd shift */),
+ /* CLK_CFG_11 */
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP_SEL/* dts */, "snps_ptp_sel",
+ snps_ptp_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 0/* lsb */, 1/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII_SEL/* dts */, "snps_rmii_sel",
+ snps_rmii_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_50M_RMII_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL/* dts */, "netsys_500m_sel",
+ netsys_500m_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_500M_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_MED_MCU_SEL/* dts */, "netsys_med_mcu_sel",
+ netsys_med_mcu_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_MED_MCU_SHIFT/* upd shift */),
+ /* CLK_CFG_12 */
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_WED_MCU_SEL/* dts */, "netsys_wed_mcu_sel",
+ netsys_wed_mcu_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_WED_MCU_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL/* dts */, "netsys_2x_sel",
+ netsys_2x_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_2X_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SGMII_SEL/* dts */, "sgmii_sel",
+ sgmii_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SGMII_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SGMII_SBUS_SEL/* dts */, "sgmii_sbus_sel",
+ sgmii_sbus_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 24/* lsb */, 1/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SGMII_SBUS_SHIFT/* upd shift */),
+#endif /* MT_CCF_MUX_DISABLE */
+};
+
+static const struct mtk_composite top_composites[] = {
+ /* CLK_AUDDIV_0 */
+ MUX(CLK_TOP_APLL_I2S0_MCK_SEL/* dts */, "apll_i2s0_mck_sel",
+ apll_i2s0_mck_parents/* parent */, 0x0320/* ofs */,
+ 16/* lsb */, 1/* width */),
+ MUX(CLK_TOP_APLL_I2S1_MCK_SEL/* dts */, "apll_i2s1_mck_sel",
+ apll_i2s1_mck_parents/* parent */, 0x0320/* ofs */,
+ 17/* lsb */, 1/* width */),
+ MUX(CLK_TOP_APLL_I2S2_MCK_SEL/* dts */, "apll_i2s2_mck_sel",
+ apll_i2s2_mck_parents/* parent */, 0x0320/* ofs */,
+ 18/* lsb */, 1/* width */),
+ MUX(CLK_TOP_APLL_I2S4_MCK_SEL/* dts */, "apll_i2s4_mck_sel",
+ apll_i2s4_mck_parents/* parent */, 0x0320/* ofs */,
+ 19/* lsb */, 1/* width */),
+ MUX(CLK_TOP_APLL_TDMOUT_MCK_SEL/* dts */, "apll_tdmout_mck_sel",
+ apll_tdmout_mck_parents/* parent */, 0x0320/* ofs */,
+ 20/* lsb */, 1/* width */),
+ MUX(CLK_TOP_APLL_I2S5_MCK_SEL/* dts */, "apll_i2s5_mck_sel",
+ apll_i2s5_mck_parents/* parent */, 0x0320/* ofs */,
+ 21/* lsb */, 1/* width */),
+ MUX(CLK_TOP_APLL_I2S6_MCK_SEL/* dts */, "apll_i2s6_mck_sel",
+ apll_i2s6_mck_parents/* parent */, 0x0320/* ofs */,
+ 22/* lsb */, 1/* width */),
+#if MT_CCF_MUX_DISABLE
+ /* CLK_AUDDIV_2 */
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV0/* dts */, "apll12_div0"/* ccf */,
+ "apll_i2s0_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_2/* ofs */, 0/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV1/* dts */, "apll12_div1"/* ccf */,
+ "apll_i2s1_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_2/* ofs */, 8/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV2/* dts */, "apll12_div2"/* ccf */,
+ "apll_i2s2_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_2/* ofs */, 16/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV4/* dts */, "apll12_div4"/* ccf */,
+ "apll_i2s4_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_2/* ofs */, 24/* lsb */,
+ 8/* width */),
+ /* CLK_AUDDIV_3 */
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_M/* dts */, "apll12_div_tdmout_m"/* ccf */,
+ "apll_tdmout_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_3/* ofs */, 0/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_B/* dts */, "apll12_div_tdmout_b"/* ccf */,
+ "apll_tdmout_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_3/* ofs */, 8/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV5/* dts */, "apll12_div5"/* ccf */,
+ "apll_i2s5_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_3/* ofs */, 16/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV6/* dts */, "apll12_div6"/* ccf */,
+ "apll_i2s6_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_3/* ofs */, 24/* lsb */,
+ 8/* width */),
+#else
+ /* CLK_AUDDIV_2 */
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV0/* dts */, "apll12_div0"/* ccf */,
+ "apll_i2s0_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 0/* pdn bit */, CLK_AUDDIV_2/* ofs */, 0/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV1/* dts */, "apll12_div1"/* ccf */,
+ "apll_i2s1_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 1/* pdn bit */, CLK_AUDDIV_2/* ofs */, 8/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV2/* dts */, "apll12_div2"/* ccf */,
+ "apll_i2s2_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 2/* pdn bit */, CLK_AUDDIV_2/* ofs */, 16/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV4/* dts */, "apll12_div4"/* ccf */,
+ "apll_i2s4_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 3/* pdn bit */, CLK_AUDDIV_2/* ofs */, 24/* lsb */,
+ 8/* width */),
+ /* CLK_AUDDIV_3 */
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_M/* dts */, "apll12_div_tdmout_m"/* ccf */,
+ "apll_tdmout_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 4/* pdn bit */, CLK_AUDDIV_3/* ofs */, 0/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_B/* dts */, "apll12_div_tdmout_b"/* ccf */,
+ "apll_tdmout_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 5/* pdn bit */, CLK_AUDDIV_3/* ofs */, 8/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV5/* dts */, "apll12_div5"/* ccf */,
+ "apll_i2s5_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 6/* pdn bit */, CLK_AUDDIV_3/* ofs */, 16/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV6/* dts */, "apll12_div6"/* ccf */,
+ "apll_i2s6_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 7/* pdn bit */, CLK_AUDDIV_3/* ofs */, 24/* lsb */,
+ 8/* width */),
+#endif /* MT_CCF_MUX_DISABLE */
+};
+
+
+
+
+
+
+
+
+
+
+
+static const struct mtk_gate_regs ifrao0_cg_regs = {
+ .set_ofs = 0x70,
+ .clr_ofs = 0x70,
+ .sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs ifrao1_cg_regs = {
+ .set_ofs = 0x74,
+ .clr_ofs = 0x74,
+ .sta_ofs = 0x74,
+};
+
+static const struct mtk_gate_regs ifrao2_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs ifrao3_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs ifrao4_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs ifrao5_cg_regs = {
+ .set_ofs = 0xc0,
+ .clr_ofs = 0xc4,
+ .sta_ofs = 0xc8,
+};
+
+static const struct mtk_gate_regs ifrao6_cg_regs = {
+ .set_ofs = 0xe0,
+ .clr_ofs = 0xe4,
+ .sta_ofs = 0xe8,
+};
+
+#define GATE_IFRAO0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_IFRAO1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_IFRAO2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFRAO3(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao3_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFRAO3_I(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao3_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_IFRAO4(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao4_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFRAO5(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao5_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFRAO6(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao6_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFRAO6_I(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao6_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate ifrao_clks[] = {
+ /* IFRAO0 */
+ /* IFRAO1 */
+ /* IFRAO2 */
+ GATE_IFRAO2(CLK_IFRAO_PMIC_TMR_SET, "ifrao_pmic_tmr_set",
+ "fpwrap_ulposc_ck"/* parent */, 0),
+ GATE_IFRAO2(CLK_IFRAO_PMIC_AP_SET, "ifrao_pmic_ap_set",
+ "fpwrap_ulposc_ck"/* parent */, 1),
+ GATE_IFRAO2(CLK_IFRAO_PMIC_MD_SET, "ifrao_pmic_md_set",
+ "fpwrap_ulposc_ck"/* parent */, 2),
+ GATE_IFRAO2(CLK_IFRAO_PMIC_CONN_SET, "ifrao_pmic_conn_set",
+ "fpwrap_ulposc_ck"/* parent */, 3),
+ GATE_IFRAO2(CLK_IFRAO_SEJ, "ifrao_sej",
+ "axi_ck"/* parent */, 5),
+ GATE_IFRAO2(CLK_IFRAO_MCUPM, "ifrao_mcupm",
+ "mcupm_ck"/* parent */, 7),
+ GATE_IFRAO2(CLK_IFRAO_GCE, "ifrao_gce",
+ "axi_ck"/* parent */, 8),
+ GATE_IFRAO2(CLK_IFRAO_GCE2, "ifrao_gce2",
+ "axi_ck"/* parent */, 9),
+ GATE_IFRAO2(CLK_IFRAO_THERM, "ifrao_therm",
+ "axi_ck"/* parent */, 10),
+ GATE_IFRAO2(CLK_IFRAO_I2C0, "ifrao_i2c0",
+ "i2c_ck"/* parent */, 11),
+ GATE_IFRAO2(CLK_IFRAO_I2C1, "ifrao_i2c1",
+ "i2c_ck"/* parent */, 12),
+ GATE_IFRAO2(CLK_IFRAO_I2C2, "ifrao_i2c2",
+ "i2c_ck"/* parent */, 13),
+ GATE_IFRAO2(CLK_IFRAO_I2C3, "ifrao_i2c3",
+ "i2c_ck"/* parent */, 14),
+ GATE_IFRAO2(CLK_IFRAO_PWM_HCLK, "ifrao_pwm_hclk",
+ "axi_ck"/* parent */, 15),
+ GATE_IFRAO2(CLK_IFRAO_PWM1, "ifrao_pwm1",
+ "pwm_ck"/* parent */, 16),
+ GATE_IFRAO2(CLK_IFRAO_PWM2, "ifrao_pwm2",
+ "pwm_ck"/* parent */, 17),
+ GATE_IFRAO2(CLK_IFRAO_PWM3, "ifrao_pwm3",
+ "pwm_ck"/* parent */, 18),
+ GATE_IFRAO2(CLK_IFRAO_PWM4, "ifrao_pwm4",
+ "pwm_ck"/* parent */, 19),
+ GATE_IFRAO2(CLK_IFRAO_PWM5, "ifrao_pwm5",
+ "pwm_ck"/* parent */, 20),
+ GATE_IFRAO2(CLK_IFRAO_PWM, "ifrao_pwm",
+ "pwm_ck"/* parent */, 21),
+ GATE_IFRAO2(CLK_IFRAO_UART0, "ifrao_uart0",
+ "fuart_ck"/* parent */, 22),
+ GATE_IFRAO2(CLK_IFRAO_UART1, "ifrao_uart1",
+ "fuart_ck"/* parent */, 23),
+ GATE_IFRAO2(CLK_IFRAO_UART2, "ifrao_uart2",
+ "fuart_ck"/* parent */, 24),
+ GATE_IFRAO2(CLK_IFRAO_UART3, "ifrao_uart3",
+ "fuart_ck"/* parent */, 25),
+ GATE_IFRAO2(CLK_IFRAO_GCE_26M_SET, "ifrao_gce_26m_set",
+ "axi_ck"/* parent */, 27),
+ /* IFRAO3 */
+ GATE_IFRAO3(CLK_IFRAO_SPI0, "ifrao_spi0",
+ "spi_ck"/* parent */, 1),
+ GATE_IFRAO3(CLK_IFRAO_MSDC0, "ifrao_msdc0",
+ "axi_ck"/* parent */, 2),
+ GATE_IFRAO3(CLK_IFRAO_MSDC1, "ifrao_msdc1",
+ "axi_ck"/* parent */, 4),
+ GATE_IFRAO3(CLK_IFRAO_MSDC0_SRC_CLK, "ifrao_msdc0_clk",
+ "msdc50_0_ck"/* parent */, 6),
+ GATE_IFRAO3(CLK_IFRAO_GCPU, "ifrao_gcpu",
+ "axi_ck"/* parent */, 8),
+ GATE_IFRAO3(CLK_IFRAO_TRNG, "ifrao_trng",
+ "axi_ck"/* parent */, 9),
+ GATE_IFRAO3(CLK_IFRAO_AUXADC, "ifrao_auxadc",
+ "f26m_ck"/* parent */, 10),
+ GATE_IFRAO3(CLK_IFRAO_CPUM, "ifrao_cpum",
+ "axi_ck"/* parent */, 11),
+ GATE_IFRAO3(CLK_IFRAO_CCIF1_AP, "ifrao_ccif1_ap",
+ "axi_ck"/* parent */, 12),
+ GATE_IFRAO3(CLK_IFRAO_CCIF1_MD, "ifrao_ccif1_md",
+ "axi_ck"/* parent */, 13),
+ GATE_IFRAO3(CLK_IFRAO_AUXADC_MD, "ifrao_auxadc_md",
+ "f26m_ck"/* parent */, 14),
+ GATE_IFRAO3(CLK_IFRAO_PCIE_TL_26M, "ifrao_pcie_tl_26m",
+ "axi_ck"/* parent */, 15),
+ GATE_IFRAO3(CLK_IFRAO_MSDC1_SRC_CLK, "ifrao_msdc1_clk",
+ "msdc30_1_ck"/* parent */, 16),
+ GATE_IFRAO3(CLK_IFRAO_PCIE_TL_96M, "ifrao_pcie_tl_96m",
+ "tl_ck"/* parent */, 18),
+ GATE_IFRAO3(CLK_IFRAO_DEVICE_APC, "ifrao_dapc",
+ "axi_ck"/* parent */, 20),
+ GATE_IFRAO3(CLK_IFRAO_CCIF_AP, "ifrao_ccif_ap",
+ "axi_ck"/* parent */, 23),
+ GATE_IFRAO3(CLK_IFRAO_DEBUGSYS, "ifrao_debugsys",
+ "axi_ck"/* parent */, 24),
+ GATE_IFRAO3(CLK_IFRAO_AUDIO, "ifrao_audio",
+ "axi_ck"/* parent */, 25),
+ GATE_IFRAO3(CLK_IFRAO_CCIF_MD, "ifrao_ccif_md",
+ "axi_ck"/* parent */, 26),
+ GATE_IFRAO3(CLK_IFRAO_DEVMPU_BCLK, "ifrao_devmpu_bclk",
+ "axi_ck"/* parent */, 30),
+ /* IFRAO4 */
+ GATE_IFRAO4(CLK_IFRAO_SSUSB, "ifrao_ssusb",
+ "fusb_ck"/* parent */, 1),
+ GATE_IFRAO4(CLK_IFRAO_DISP_PWM, "ifrao_disp_pwm",
+ "axi_ck"/* parent */, 2),
+ GATE_IFRAO4(CLK_IFRAO_CLDMA_BCLK, "ifrao_cldmabclk",
+ "axi_ck"/* parent */, 3),
+ GATE_IFRAO4(CLK_IFRAO_AUDIO_26M_BCLK, "ifrao_audio26m",
+ "f26m_ck"/* parent */, 4),
+ GATE_IFRAO4(CLK_IFRAO_MODEM_TEMP_SHARE, "ifrao_mdtemp",
+ "f26m_ck"/* parent */, 5),
+ GATE_IFRAO4(CLK_IFRAO_SPI1, "ifrao_spi1",
+ "spi_ck"/* parent */, 6),
+ GATE_IFRAO4(CLK_IFRAO_I2C4, "ifrao_i2c4",
+ "i2c_ck"/* parent */, 7),
+ GATE_IFRAO4(CLK_IFRAO_SPI2, "ifrao_spi2",
+ "spi_ck"/* parent */, 9),
+ GATE_IFRAO4(CLK_IFRAO_SPI3, "ifrao_spi3",
+ "spi_ck"/* parent */, 10),
+ GATE_IFRAO4(CLK_IFRAO_UNIPRO_TICK, "ifrao_unipro_tick",
+ "f26m_ck"/* parent */, 12),
+ GATE_IFRAO4(CLK_IFRAO_UFS_MP_SAP_BCLK, "ifrao_ufs_bclk",
+ "f26m_ck"/* parent */, 13),
+ GATE_IFRAO4(CLK_IFRAO_MD32_BCLK, "ifrao_md32_bclk",
+ "axi_ck"/* parent */, 14),
+ GATE_IFRAO4(CLK_IFRAO_UNIPRO_MBIST, "ifrao_unipro_mbist",
+ "axi_ck"/* parent */, 16),
+ GATE_IFRAO4(CLK_IFRAO_PWM6, "ifrao_pwm6",
+ "i2c_ck"/* parent */, 18),
+ GATE_IFRAO4(CLK_IFRAO_PWM7, "ifrao_pwm7",
+ "i2c_ck"/* parent */, 19),
+ GATE_IFRAO4(CLK_IFRAO_I2C_SLAVE, "ifrao_i2c_slave",
+ "i2c_ck"/* parent */, 20),
+ GATE_IFRAO4(CLK_IFRAO_I2C1_ARBITER, "ifrao_i2c1a",
+ "i2c_ck"/* parent */, 21),
+ GATE_IFRAO4(CLK_IFRAO_I2C1_IMM, "ifrao_i2c1_imm",
+ "i2c_ck"/* parent */, 22),
+ GATE_IFRAO4(CLK_IFRAO_I2C2_ARBITER, "ifrao_i2c2a",
+ "i2c_ck"/* parent */, 23),
+ GATE_IFRAO4(CLK_IFRAO_I2C2_IMM, "ifrao_i2c2_imm",
+ "i2c_ck"/* parent */, 24),
+ GATE_IFRAO4(CLK_IFRAO_SSUSB_XHCI, "ifrao_ssusb_xhci",
+ "fssusb_xhci_ck"/* parent */, 31),
+ /* IFRAO5 */
+ GATE_IFRAO5(CLK_IFRAO_MSDC0_SELF, "ifrao_msdc0sf",
+ "msdc50_0_ck"/* parent */, 0),
+ GATE_IFRAO5(CLK_IFRAO_MSDC1_SELF, "ifrao_msdc1sf",
+ "msdc50_0_ck"/* parent */, 1),
+ GATE_IFRAO5(CLK_IFRAO_MSDC2_SELF, "ifrao_msdc2sf",
+ "msdc50_0_ck"/* parent */, 2),
+ GATE_IFRAO5(CLK_IFRAO_SSPM_26M_SELF, "ifrao_sspm_26m",
+ "f26m_ck"/* parent */, 3),
+ GATE_IFRAO5(CLK_IFRAO_SSPM_32K_SELF, "ifrao_sspm_32k",
+ "frtc_ck"/* parent */, 4),
+ GATE_IFRAO5(CLK_IFRAO_I2C6, "ifrao_i2c6",
+ "i2c_ck"/* parent */, 6),
+ GATE_IFRAO5(CLK_IFRAO_AP_MSDC0, "ifrao_ap_msdc0",
+ "msdc50_0_ck"/* parent */, 7),
+ GATE_IFRAO5(CLK_IFRAO_MD_MSDC0, "ifrao_md_msdc0",
+ "msdc50_0_ck"/* parent */, 8),
+ GATE_IFRAO5(CLK_IFRAO_CCIF5_AP, "ifrao_ccif5_ap",
+ "axi_ck"/* parent */, 9),
+ GATE_IFRAO5(CLK_IFRAO_CCIF5_MD, "ifrao_ccif5_md",
+ "axi_ck"/* parent */, 10),
+ GATE_IFRAO5(CLK_IFRAO_PCIE_TOP_HCLK_133M, "ifrao_pcie_h_133m",
+ "axi_ck"/* parent */, 11),
+ GATE_IFRAO5(CLK_IFRAO_SPIS_HCLK_66M, "ifrao_spis_h_66m",
+ "axi_ck"/* parent */, 14),
+ GATE_IFRAO5(CLK_IFRAO_PCIE_PERI_26M, "ifrao_pcie_peri_26m",
+ "f26m_ck"/* parent */, 15),
+ GATE_IFRAO5(CLK_IFRAO_CCIF2_AP, "ifrao_ccif2_ap",
+ "axi_ck"/* parent */, 16),
+ GATE_IFRAO5(CLK_IFRAO_CCIF2_MD, "ifrao_ccif2_md",
+ "axi_ck"/* parent */, 17),
+ GATE_IFRAO5(CLK_IFRAO_SEJ_F13M, "ifrao_sej_f13m",
+ "f26m_ck"/* parent */, 20),
+ GATE_IFRAO5(CLK_IFRAO_AES, "ifrao_aes",
+ "axi_ck"/* parent */, 21),
+ GATE_IFRAO5(CLK_IFRAO_I2C7, "ifrao_i2c7",
+ "i2c_ck"/* parent */, 22),
+ GATE_IFRAO5(CLK_IFRAO_I2C8, "ifrao_i2c8",
+ "i2c_ck"/* parent */, 23),
+ GATE_IFRAO5(CLK_IFRAO_FBIST2FPC, "ifrao_fbist2fpc",
+ "msdc50_0_ck"/* parent */, 24),
+ GATE_IFRAO5(CLK_IFRAO_DPMAIF_MAIN, "ifrao_dpmaif_main",
+ "dpmaif_main_ck"/* parent */, 26),
+ GATE_IFRAO5(CLK_IFRAO_PCIE_TL_32K, "ifrao_pcie_tl_32k",
+ "frtc_ck"/* parent */, 27),
+ GATE_IFRAO5(CLK_IFRAO_CCIF4_AP, "ifrao_ccif4_ap",
+ "axi_ck"/* parent */, 28),
+ GATE_IFRAO5(CLK_IFRAO_CCIF4_MD, "ifrao_ccif4_md",
+ "axi_ck"/* parent */, 29),
+ /* IFRAO6 */
+ GATE_IFRAO6(CLK_IFRAO_133M_MCLK_CK, "ifrao_133m_mclk_ck",
+ "axi_ck"/* parent */, 0),
+ GATE_IFRAO6(CLK_IFRAO_66M_MCLK_CK, "ifrao_66m_mclk_ck",
+ "axi_ck"/* parent */, 1),
+ GATE_IFRAO6(CLK_IFRAO_66M_PERI_BUS_MCLK_CK, "ifrao_66m_peri_mclk",
+ "axi_ck"/* parent */, 2),
+ GATE_IFRAO6(CLK_IFRAO_INFRA_FREE_DCM_133M, "ifrao_infra_133m",
+ "axi_ck"/* parent */, 3),
+ GATE_IFRAO6(CLK_IFRAO_INFRA_FREE_DCM_66M, "ifrao_infra_66m",
+ "axi_ck"/* parent */, 4),
+ GATE_IFRAO6(CLK_IFRAO_PERU_BUS_DCM_133M, "ifrao_peru_bus_133m",
+ "axi_ck"/* parent */, 5),
+ GATE_IFRAO6(CLK_IFRAO_PERU_BUS_DCM_66M, "ifrao_peru_bus_66m",
+ "axi_ck"/* parent */, 6),
+ GATE_IFRAO6(CLK_IFRAO_RG_133M_CLDMA_TOP, "ifrao_133m_cldma_top",
+ "axi_ck"/* parent */, 7),
+ GATE_IFRAO6(CLK_IFRAO_RG_ECC_TOP, "ifrao_ecc_top",
+ "axi_ck"/* parent */, 8),
+ GATE_IFRAO6(CLK_IFRAO_RG_66M_GCPU, "ifrao_66m_gcpu",
+ "axi_ck"/* parent */, 9),
+ GATE_IFRAO6(CLK_IFRAO_RG_133M_DWC_ETHER, "ifrao_133m_dwc_ether",
+ "axi_ck"/* parent */, 11),
+ GATE_IFRAO6(CLK_IFRAO_RG_133M_FLASHIF, "ifrao_133m_flashif",
+ "axi_ck"/* parent */, 12),
+ GATE_IFRAO6(CLK_IFRAO_RG_133M_PCIE_P0, "ifrao_133m_pcie_p0",
+ "axi_ck"/* parent */, 13),
+ GATE_IFRAO6_I(CLK_IFRAO_RG_133M_PCIE_P1, "ifrao_133m_pcie_p1",
+ "axi_ck"/* parent */, 14),
+ GATE_IFRAO6_I(CLK_IFRAO_RG_133M_PCIE_P2, "ifrao_133m_pcie_p2",
+ "axi_ck"/* parent */, 15),
+ GATE_IFRAO6_I(CLK_IFRAO_RG_133M_PCIE_P3, "ifrao_133m_pcie_p3",
+ "axi_ck"/* parent */, 16),
+ GATE_IFRAO6(CLK_IFRAO_RG_MMW_DPMAIF_TOP_CK, "ifrao_mmw_dpmaif_ck",
+ "axi_ck"/* parent */, 17),
+ GATE_IFRAO6(CLK_IFRAO_RG_NFI, "ifrao_nfi",
+ "nfi1x_ck"/* parent */, 18),
+ GATE_IFRAO6(CLK_IFRAO_RG_FPINFI_BCLK_CK, "ifrao_fpinfi_bclk_ck",
+ "spinfi_bclk_ck"/* parent */, 19),
+ GATE_IFRAO6(CLK_IFRAO_RG_66M_NFI_HCLK_CK, "ifrao_66m_nfi_h_ck",
+ "axi_ck"/* parent */, 20),
+ GATE_IFRAO6(CLK_IFRAO_RG_FSPIS_CK, "ifrao_fspis_ck",
+ "axi_ck"/* parent */, 21),
+ GATE_IFRAO6(CLK_IFRAO_RG_PCIE_PERI_26M_P1, "ifrao_26m_p1",
+ "axi_ck"/* parent */, 25),
+ GATE_IFRAO6(CLK_IFRAO_RG_PCIE_PERI_26M_P2, "ifrao_26m_p2",
+ "axi_ck"/* parent */, 26),
+ GATE_IFRAO6(CLK_IFRAO_RG_PCIE_PERI_26M_P3, "ifrao_26m_p3",
+ "axi_ck"/* parent */, 27),
+ GATE_IFRAO6(CLK_IFRAO_RG_FLASHIF_PERI_26M, "ifrao_flash_26m",
+ "axi_ck"/* parent */, 30),
+ GATE_IFRAO6(CLK_IFRAO_RG_FLASHIF_SFLASH, "ifrao_sflash_ck",
+ "axi_ck"/* parent */, 31),
+};
+
+
+
+static const struct mtk_gate_regs peri_cg_regs = {
+ .set_ofs = 0x20c,
+ .clr_ofs = 0x20c,
+ .sta_ofs = 0x20c,
+};
+
+#define GATE_PERI(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate peri_clks[] = {
+};
+
+static const struct mtk_gate_regs apmixed_cg_regs = {
+ .set_ofs = 0x14,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x14,
+};
+#define GATE_APMIXED(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &apmixed_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate apmixed_clks[] = {
+};
+
+
+#define MT6880_PLL_FMAX (3800UL * MHZ)
+#define MT6880_PLL_FMIN (1500UL * MHZ)
+#define MT6880_INTEGER_BITS 8
+
+#if MT_CCF_PLL_DISABLE
+#define PLL_CFLAGS PLL_AO
+#else
+#define PLL_CFLAGS (0)
+#endif
+
+#define PLL_B(_id, _name, _reg, _en_reg, _en_mask, _pwr_reg, \
+ _iso_mask, _pwron_mask, _flags, _rst_bar_reg, \
+ _rst_bar_mask, _pd_reg, _pd_shift, _tuner_reg, \
+ _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
+ _pcw_shift, _pcwbits, _div_table) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .en_reg = _en_reg, \
+ .en_mask = _en_mask, \
+ .pwr_reg = _pwr_reg, \
+ .iso_mask = _iso_mask, \
+ .pwron_mask = _pwron_mask, \
+ .flags = (_flags | PLL_CFLAGS), \
+ .rst_bar_reg = _rst_bar_reg, \
+ .rst_bar_mask = _rst_bar_mask, \
+ .fmax = MT6880_PLL_FMAX, \
+ .fmin = MT6880_PLL_FMIN, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .tuner_en_reg = _tuner_en_reg, \
+ .tuner_en_bit = _tuner_en_bit, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = MT6880_INTEGER_BITS, \
+ .div_table = _div_table, \
+ }
+
+#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pwr_reg, \
+ _iso_mask, _pwron_mask, _flags, _rst_bar_reg, \
+ _rst_bar_mask, _pd_reg, _pd_shift, _tuner_reg, \
+ _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
+ _pcw_shift, _pcwbits) \
+ PLL_B(_id, _name, _reg, _en_reg, _en_mask, _pwr_reg, \
+ _iso_mask, _pwron_mask, _flags, _rst_bar_reg, \
+ _rst_bar_mask, _pd_reg, _pd_shift, _tuner_reg, \
+ _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
+ _pcw_shift, _pcwbits, NULL) \
+
+static const struct mtk_pll_data plls[] = {
+ PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", ARMPLL_LL_CON0/*base*/,
+ ARMPLL_LL_CON0, 0x0200/*en*/,
+ ARMPLL_LL_CON4, 0x0002, 0x0001/*pwr*/,
+ PLL_AO, 0, BIT(0)/*rstb*/,
+ 0x020C, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ ARMPLL_LL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_CCIPLL, "ccipll", CCIPLL_CON0/*base*/,
+ CCIPLL_CON0, 0x0200/*en*/,
+ CCIPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ PLL_AO, 0, BIT(0)/*rstb*/,
+ 0x0220, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ CCIPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_MPLL, "mpll", MPLL_CON0/*base*/,
+ MPLL_CON0, 0x0200/*en*/,
+ MPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ PLL_AO, 0, BIT(0)/*rstb*/,
+ 0x060C, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ MPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0/*base*/,
+ MAINPLL_CON0, 0x0200/*en*/,
+ MAINPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ HAVE_RST_BAR|PLL_AO, 0x0404, BIT(23)/*rstb*/,
+ 0x040C, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ MAINPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0/*base*/,
+ UNIVPLL_CON0, 0x0200/*en*/,
+ UNIVPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ HAVE_RST_BAR, 0x0418, BIT(23)/*rstb*/,
+ 0x0420, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ UNIVPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0/*base*/,
+ MSDCPLL_CON0, 0x0200/*en*/,
+ MSDCPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x234, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ MSDCPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_MMPLL, "mmpll", MMPLL_CON0/*base*/,
+ MMPLL_CON0, 0x0200/*en*/,
+ MMPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ HAVE_RST_BAR, 0x042C, BIT(23)/*rstb*/,
+ 0x0434, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ MMPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_MFGPLL, "mfgpll", MFGPLL_CON0/*base*/,
+ MFGPLL_CON0, 0x0200/*en*/,
+ MFGPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x0620, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ MFGPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_APLL1, "apll1", APLL1_CON0/*base*/,
+ APLL1_CON0, 0x0200/*en*/,
+ APLL1_CON5, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x045C, 24/*pd*/,
+ APLL1_TUNER_CON0, AP_PLL_CON0, 12/*tuner*/,
+ APLL1_CON3, 0, 32/*pcw*/),
+ PLL(CLK_APMIXED_APLL2, "apll2", APLL2_CON0/*base*/,
+ APLL2_CON0, 0x0200/*en*/,
+ APLL2_CON5, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x0474, 24/*pd*/,
+ APLL2_TUNER_CON0, AP_PLL_CON0, 13/*tuner*/,
+ APLL2_CON3, 0, 32/*pcw*/),
+ PLL(CLK_APMIXED_NET1PLL, "net1pll", NET1PLL_CON0/*base*/,
+ NET1PLL_CON0, 0x0200/*en*/,
+ NET1PLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x080C, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ NET1PLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_NET2PLL, "net2pll", NET2PLL_CON0/*base*/,
+ NET2PLL_CON0, 0x0200/*en*/,
+ NET2PLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x0820, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ NET2PLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", WEDMCUPLL_CON0/*base*/,
+ WEDMCUPLL_CON0, 0x0200/*en*/,
+ WEDMCUPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x0834, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ WEDMCUPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_MEDMCUPLL, "medmcupll", MEDMCUPLL_CON0/*base*/,
+ MEDMCUPLL_CON0, 0x0200/*en*/,
+ MEDMCUPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x0848, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ MEDMCUPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_SGMIIPLL, "sgmiipll", SGMIIPLL_CON0/*base*/,
+ SGMIIPLL_CON0, 0x0200/*en*/,
+ SGMIIPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x0248, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ SGMIIPLL_CON2, 0, 22/*pcw*/),
+};
+
+static int clk_mt6880_apmixed_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ void __iomem *base;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base)) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return PTR_ERR(base);
+ }
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+ clk_data);
+
+ mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ apmixed_base = base;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static int clk_mt6880_ifrao_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_IFRAO_NR_CLK);
+
+ mtk_clk_register_gates(node, ifrao_clks, ARRAY_SIZE(ifrao_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static int clk_mt6880_peri_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+ mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static struct clk_onecell_data *mt6880_top_clk_data;
+
+static int clk_mt6880_top_probe(struct platform_device *pdev)
+{
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ void __iomem *base;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base)) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return PTR_ERR(base);
+ }
+
+ mt6880_top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
+ mt6880_top_clk_data);
+
+ mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
+ &mt6880_clk_lock, mt6880_top_clk_data);
+
+ mtk_clk_register_composites(top_composites, ARRAY_SIZE(top_composites),
+ base, &mt6880_clk_lock, mt6880_top_clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get,
+ mt6880_top_clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+/*
+ mtk_clk_check_muxes(top_muxes, ARRAY_SIZE(top_muxes),
+ mt6880_top_clk_data);
+*/
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+/* for suspend LDVT only */
+void pll_force_off(void)
+{
+ void __iomem *rst_reg, *en_reg, *pwr_reg;
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(plls); i++) {
+ /* do not pwrdn the AO PLLs */
+ if ((plls[i].flags & PLL_AO) == PLL_AO)
+ continue;
+
+ if ((plls[i].flags & HAVE_RST_BAR) == HAVE_RST_BAR) {
+ rst_reg = apmixed_base + plls[i].rst_bar_reg;
+ writel(readl(rst_reg) & ~plls[i].rst_bar_mask,
+ rst_reg);
+ }
+
+ en_reg = apmixed_base + plls[i].en_reg;
+
+ pwr_reg = apmixed_base + plls[i].pwr_reg;
+
+ writel(readl(en_reg) & ~plls[i].en_mask,
+ en_reg);
+ writel(readl(pwr_reg) | plls[i].iso_mask,
+ pwr_reg);
+ writel(readl(pwr_reg) & ~plls[i].pwron_mask,
+ pwr_reg);
+ }
+}
+
+static struct generic_pm_domain **get_all_genpd(void)
+{
+ static struct generic_pm_domain *pds[31];
+ static int num_pds;
+ const size_t maxpd = ARRAY_SIZE(pds);
+ struct device_node *node;
+ struct platform_device *pdev;
+ int r;
+ if (num_pds != 0)
+ goto out;
+ node = of_find_node_with_property(NULL, "#power-domain-cells");
+ if (node == NULL)
+ return NULL;
+ pdev = platform_device_alloc("traverse", 0);
+ for (num_pds = 0; num_pds < maxpd; num_pds++) {
+ struct of_phandle_args pa;
+ pa.np = node;
+ pa.args[0] = num_pds;
+ pa.args_count = 1;
+ r = of_genpd_add_device(&pa, &pdev->dev);
+ if (r == -EINVAL)
+ continue;
+ else if (r != 0)
+ pr_warn("%s(): of_genpd_add_device(%d)\n", __func__, r);
+ pds[num_pds] = pd_to_genpd(pdev->dev.pm_domain);
+ //r = pm_genpd_remove_device(pds[num_pds], &pdev->dev);
+ r = pm_genpd_remove_device(&pdev->dev);
+ if (r != 0)
+ pr_warn("%s(): pm_genpd_remove_device(%d)\n",
+ __func__, r);
+ if (IS_ERR(pds[num_pds])) {
+ pds[num_pds] = NULL;
+ break;
+ }
+ }
+ platform_device_put(pdev);
+out:
+ return pds;
+}
+
+void subsys_force_off(void)
+{
+ struct generic_pm_domain *genpd;
+ int (*gpd_op)(struct generic_pm_domain *);
+ int r = 0;
+ struct generic_pm_domain **pds = get_all_genpd();
+ for (; *pds != NULL; pds++) {
+ genpd = *pds;
+ if (IS_ERR_OR_NULL(genpd))
+ continue;
+ if((genpd->flags & GENPD_FLAG_ALWAYS_ON)|(genpd->status == GPD_STATE_POWER_OFF))
+ continue;
+ gpd_op = genpd->power_off;
+ r |= gpd_op(genpd);
+ }
+}
+
+void pll_if_on(void)
+{
+ void __iomem *en_reg;
+ u32 i;
+ for (i = 0; i < ARRAY_SIZE(plls); i++) {
+
+ en_reg = apmixed_base + plls[i].en_reg;
+
+ if (readl(en_reg) & plls[i].en_mask)
+ pr_notice("suspend warning : %s is on !!!\n",plls[i].name);
+
+ }
+}
+
+void subsys_if_on(void)
+{
+ static const char * const pwr_names[] = {
+ [0] = "MD1",
+ [1] = "CONN",
+ [2] = "MFG0",
+ [3] = "PEXTP_D_2LX1_PHY",
+ [4] = "PEXTP_R_2LX1_PHY",
+ [5] = "PEXTP_R_1LX2_0P_PHY",
+ [6] = "PEXTP_R_1LX2_1P_PHY",
+ [7] = "SSUSB_PHY",
+ [8] = "SGMII_0_PHY",
+ [9] = "IFR",
+ [10] = "SGMII_1_PHY",
+ [11] = "DPY",
+ [12] = "PEXTP_D_2LX1",
+ [13] = "PEXTP_R_2LX1",
+ [14] = "PEXTP_R_1LX2",
+ [15] = "ETH",
+ [16] = "SSUSB",
+ [17] = "SGMII_0_TOP",
+ [18] = "SGMII_1_TOP",
+ [19] = "NETSYS",
+ [20] = "DIS",
+ [21] = "AUDIO",
+ [22] = "EIP97",
+ [23] = "HSMTOP",
+ [24] = "DRAMC_MD32",
+ [25] = "(Reserved)",
+ [26] = "(Reserved)",
+ [27] = "(Reserved)",
+ [28] = "DPY2",
+ [29] = "MCUPM",
+ [30] = "MSDC",
+ [31] = "PERI",
+ };
+ u32 val = 0,i;
+ static void __iomem *scpsys_base, *pwr_sta, *pwr_sta_2nd;
+
+ scpsys_base = ioremap(0x10006000, PAGE_SIZE);
+ pwr_sta = scpsys_base + 0x16c;
+ pwr_sta_2nd = scpsys_base + 0x170;
+ val = readl(pwr_sta) & readl(pwr_sta_2nd);
+
+ for (i = 0; i < 32; i++) {
+ if((val & BIT(i)) != 0U)
+ pr_notice("suspend warning: %s is on!!\n",pwr_names[i]);
+ }
+}
+
+static int pll_status_cmd(struct seq_file *s, void *v)
+{
+ seq_printf(s, "Call pll_if_on \n");
+ pll_if_on();
+ return 0;
+}
+
+static int mtcmos_status_cmd(struct seq_file *s, void *v)
+{
+ seq_printf(s, "Call subsys_if_on \n");
+ subsys_if_on();
+ return 0;
+}
+
+static int pll_off_cmd(struct seq_file *s, void *v)
+{
+ seq_printf(s, "Call pll_force_off \n");
+ pll_force_off();
+ return 0;
+}
+
+static int mtcmos_off_cmd(struct seq_file *s, void *v)
+{
+ seq_printf(s, "Call subsys_force_off \n");
+ subsys_force_off();
+ return 0;
+}
+
+static int all_off_cmd(struct seq_file *s, void *v)
+{
+ seq_printf(s, "Call pll/mtcmos off and status \n");
+ pll_force_off();
+ subsys_force_off();
+ pll_if_on();
+ subsys_if_on();
+ return 0;
+}
+
+static const struct cmd_fn cmds[] = {
+ CMDFN("pll_status", pll_status_cmd),
+ CMDFN("mtcmos_status", mtcmos_status_cmd),
+ CMDFN("pll_off", pll_off_cmd),
+ CMDFN("mtcmos_off", mtcmos_off_cmd),
+ CMDFN("all_off", all_off_cmd),
+ {}
+};
+
+static const struct of_device_id of_match_clk_mt6880[] = {
+ {
+ .compatible = "mediatek,mt6880-apmixedsys",
+ .data = clk_mt6880_apmixed_probe,
+ }, {
+ .compatible = "mediatek,mt6880-infracfg_ao",
+ .data = clk_mt6880_ifrao_probe,
+ }, {
+ .compatible = "mediatek,mt6880-pericfg",
+ .data = clk_mt6880_peri_probe,
+ }, {
+ .compatible = "mediatek,mt6880-topckgen",
+ .data = clk_mt6880_top_probe,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt6880_probe(struct platform_device *pdev)
+{
+ int (*clk_probe)(struct platform_device *pd);
+ int r;
+
+ clk_probe = of_device_get_match_data(&pdev->dev);
+ if (!clk_probe)
+ return -EINVAL;
+
+ r = clk_probe(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ set_custom_cmds(cmds);
+ return r;
+}
+
+static struct platform_driver clk_mt6880_drv = {
+ .probe = clk_mt6880_probe,
+ .driver = {
+ .name = "clk-mt6880",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_clk_mt6880,
+ },
+};
+
+static int __init clk_mt6880_init(void)
+{
+ return platform_driver_register(&clk_mt6880_drv);
+}
+
+arch_initcall_sync(clk_mt6880_init);
+
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-audsys.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-audsys.c
new file mode 100755
index 0000000..9191f45
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-audsys.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6890-clk.h>
+
+#define MT_CLKMGR_MODULE_INIT 0
+
+#define MT_CCF_BRINGUP 1
+
+#define INV_OFS -1
+
+/* get spm power status struct to register inside clk_data */
+static struct pwr_status pwr_stat = GATE_PWR_STAT(0x16C,
+ 0x170, INV_OFS, BIT(21), BIT(21));
+
+static const struct mtk_gate_regs audsys0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs audsys1_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x4,
+};
+
+static const struct mtk_gate_regs audsys2_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x8,
+};
+
+#define GATE_AUDSYS0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audsys0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ .pwr_stat = &pwr_stat, \
+ }
+
+#define GATE_AUDSYS1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audsys1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ .pwr_stat = &pwr_stat, \
+ }
+
+#define GATE_AUDSYS2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audsys2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ .pwr_stat = &pwr_stat, \
+ }
+
+static const struct mtk_gate audsys_clks[] = {
+ /* AUDSYS0 */
+ GATE_AUDSYS0(CLK_AUDSYS_AFE, "aud_afe",
+ "audio_ck"/* parent */, 2),
+ GATE_AUDSYS0(CLK_AUDSYS_22M, "aud_22m",
+ "aud_engen1_ck"/* parent */, 8),
+ GATE_AUDSYS0(CLK_AUDSYS_24M, "aud_24m",
+ "aud_engen2_ck"/* parent */, 9),
+ GATE_AUDSYS0(CLK_AUDSYS_APLL2_TUNER, "aud_apll2_tuner",
+ "aud_engen2_ck"/* parent */, 18),
+ GATE_AUDSYS0(CLK_AUDSYS_APLL_TUNER, "aud_apll_tuner",
+ "aud_engen1_ck"/* parent */, 19),
+ GATE_AUDSYS0(CLK_AUDSYS_TDM, "aud_tdm_ck",
+ "aud_engen1_ck"/* parent */, 20),
+ GATE_AUDSYS0(CLK_AUDSYS_ADC, "aud_adc",
+ "audio_ck"/* parent */, 24),
+ GATE_AUDSYS0(CLK_AUDSYS_DAC, "aud_dac",
+ "audio_ck"/* parent */, 25),
+ GATE_AUDSYS0(CLK_AUDSYS_DAC_PREDIS, "aud_dac_predis",
+ "audio_ck"/* parent */, 26),
+ GATE_AUDSYS0(CLK_AUDSYS_TML, "aud_tml",
+ "audio_ck"/* parent */, 27),
+ /* AUDSYS1 */
+ GATE_AUDSYS1(CLK_AUDSYS_I2S0_BCLK, "aud_i2s0_bclk",
+ "audio_ck"/* parent */, 4),
+ GATE_AUDSYS1(CLK_AUDSYS_I2S1_BCLK, "aud_i2s1_bclk",
+ "audio_ck"/* parent */, 5),
+ GATE_AUDSYS1(CLK_AUDSYS_I2S2_BCLK, "aud_i2s2_bclk",
+ "audio_ck"/* parent */, 6),
+ GATE_AUDSYS1(CLK_AUDSYS_I2S4_BCLK, "aud_i2s4_bclk",
+ "audio_ck"/* parent */, 7),
+ GATE_AUDSYS1(CLK_AUDSYS_I2S5_BCLK, "aud_i2s5_bclk",
+ "audio_ck"/* parent */, 8),
+ GATE_AUDSYS1(CLK_AUDSYS_I2S6_BCLK, "aud_i2s6_bclk",
+ "audio_ck"/* parent */, 9),
+ GATE_AUDSYS1(CLK_AUDSYS_GENERAL1_ASRC, "aud_general1_asrc",
+ "audio_ck"/* parent */, 13),
+ GATE_AUDSYS1(CLK_AUDSYS_GENERAL2_ASRC, "aud_general2_asrc",
+ "audio_ck"/* parent */, 14),
+ GATE_AUDSYS1(CLK_AUDSYS_ADDA6_ADC, "aud_adda6_adc",
+ "audio_ck"/* parent */, 20),
+ /* AUDSYS2 */
+ GATE_AUDSYS2(CLK_AUDSYS_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc",
+ "audio_ck"/* parent */, 12),
+ GATE_AUDSYS2(CLK_AUDSYS_AFE_SRC_PCM_TX, "aud_afe_src_pcm_tx",
+ "audio_ck"/* parent */, 16),
+ GATE_AUDSYS2(CLK_AUDSYS_AFE_SRC_PCM_TX2, "aud_afe_src_pcm_tx2",
+ "audio_ck"/* parent */, 17),
+ GATE_AUDSYS2(CLK_AUDSYS_AFE_SRC_PCM_TX3, "aud_afe_src_pcm_tx3",
+ "audio_ck"/* parent */, 18),
+ GATE_AUDSYS2(CLK_AUDSYS_AFE_SRC_PCM_RX, "aud_afe_src_pcm_rx",
+ "audio_ck"/* parent */, 19),
+ GATE_AUDSYS2(CLK_AUDSYS_AFE_SRC_I2SIN, "aud_afe_src_i2sin",
+ "audio_ck"/* parent */, 20),
+ GATE_AUDSYS2(CLK_AUDSYS_AFE_SRC_I2SOUT, "aud_afe_src_i2sout",
+ "audio_ck"/* parent */, 21),
+};
+
+static int clk_mt6890_audsys_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_AUDSYS_NR_CLK);
+
+ mtk_clk_register_gates(node, audsys_clks, ARRAY_SIZE(audsys_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt6890_audsys[] = {
+ { .compatible = "mediatek,mt6890-audsys", },
+ {}
+};
+
+#if MT_CLKMGR_MODULE_INIT
+
+static struct platform_driver clk_mt6890_audsys_drv = {
+ .probe = clk_mt6890_audsys_probe,
+ .driver = {
+ .name = "clk-mt6890-audsys",
+ .of_match_table = of_match_clk_mt6890_audsys,
+ },
+};
+
+builtin_platform_driver(clk_mt6890_audsys_drv);
+
+#else
+
+static struct platform_driver clk_mt6890_audsys_drv = {
+ .probe = clk_mt6890_audsys_probe,
+ .driver = {
+ .name = "clk-mt6890-audsys",
+ .of_match_table = of_match_clk_mt6890_audsys,
+ },
+};
+static int __init clk_mt6890_audsys_platform_init(void)
+{
+ return platform_driver_register(&clk_mt6890_audsys_drv);
+}
+arch_initcall(clk_mt6890_audsys_platform_init);
+
+#endif /* MT_CLKMGR_MODULE_INIT */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-dbgsys_dem.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-dbgsys_dem.c
new file mode 100755
index 0000000..6ce5a24
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-dbgsys_dem.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6890-clk.h>
+
+#define MT_CLKMGR_MODULE_INIT 0
+
+#define MT_CCF_BRINGUP 1
+
+#define INV_OFS -1
+
+
+
+static const struct mtk_gate_regs dbgsys_dem0_cg_regs = {
+ .set_ofs = 0x2c,
+ .clr_ofs = 0x2c,
+ .sta_ofs = 0x2c,
+};
+
+static const struct mtk_gate_regs dbgsys_dem1_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+static const struct mtk_gate_regs dbgsys_dem2_cg_regs = {
+ .set_ofs = 0x70,
+ .clr_ofs = 0x70,
+ .sta_ofs = 0x70,
+};
+
+#define GATE_DBGSYS_DEM0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &dbgsys_dem0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_DBGSYS_DEM1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &dbgsys_dem1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_DBGSYS_DEM2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &dbgsys_dem2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate dbgsys_dem_clks[] = {
+ /* DBGSYS_DEM0 */
+ GATE_DBGSYS_DEM0(CLK_DBGSYS_DEM_BUSCLK_EN, "dbgsys_dem_busclk_en",
+ "axi_ck"/* parent */, 0),
+ /* DBGSYS_DEM1 */
+ GATE_DBGSYS_DEM1(CLK_DBGSYS_DEM_SYSCLK_EN, "dbgsys_dem_sysclk_en",
+ "axi_ck"/* parent */, 0),
+ /* DBGSYS_DEM2 */
+ GATE_DBGSYS_DEM2(CLK_DBGSYS_DEM_ATB_EN, "dbgsys_dem_atb_en",
+ "axi_ck"/* parent */, 0),
+};
+
+static int clk_mt6890_dbgsys_dem_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_DBGSYS_DEM_NR_CLK);
+
+ mtk_clk_register_gates(node, dbgsys_dem_clks, ARRAY_SIZE(dbgsys_dem_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt6890_dbgsys_dem[] = {
+ { .compatible = "mediatek,mt6890-dbgsys_dem", },
+ {}
+};
+
+#if MT_CLKMGR_MODULE_INIT
+
+static struct platform_driver clk_mt6890_dbgsys_dem_drv = {
+ .probe = clk_mt6890_dbgsys_dem_probe,
+ .driver = {
+ .name = "clk-mt6890-dbgsys_dem",
+ .of_match_table = of_match_clk_mt6890_dbgsys_dem,
+ },
+};
+
+builtin_platform_driver(clk_mt6890_dbgsys_dem_drv);
+
+#else
+
+static struct platform_driver clk_mt6890_dbgsys_dem_drv = {
+ .probe = clk_mt6890_dbgsys_dem_probe,
+ .driver = {
+ .name = "clk-mt6890-dbgsys_dem",
+ .of_match_table = of_match_clk_mt6890_dbgsys_dem,
+ },
+};
+static int __init clk_mt6890_dbgsys_dem_platform_init(void)
+{
+ return platform_driver_register(&clk_mt6890_dbgsys_dem_drv);
+}
+arch_initcall(clk_mt6890_dbgsys_dem_platform_init);
+
+#endif /* MT_CLKMGR_MODULE_INIT */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-fmeter.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-fmeter.h
new file mode 100755
index 0000000..12078f0
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-fmeter.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+
+#ifndef _CLK_MT6890_FMETER_H
+#define _CLK_MT6890_FMETER_H
+
+/* generate from clock_table.xlsx from TOPCKGEN DE */
+
+/* CKGEN Part */
+#define FM_AXI_CK 1
+#define FM_SPM_CK 2
+#define FM_BUS_CK 3
+#define FM_MM_CK 4
+#define FM_MFG_REF_CK 5
+#define FM_FUART_CK 6
+#define FM_MSDC50_0_H_CK 7
+#define FM_MSDC50_0_CK 8
+#define FM_MSDC30_1_CK 9
+#define FM_AUDIO_CK 10
+#define FM_AUD_INTBUS_CK 11
+#define FM_AUD_ENGEN1_CK 12
+#define FM_AUD_ENGEN2_CK 13
+#define FM_AUD1_CK 14
+#define FM_AUD2_CK 15
+#define FM_FPWRAP_ULPOSC_CK 16
+#define FM_ATB_CK 17
+#define FM_PWRMCU_CK 18
+#define FM_DBI_CK 19
+#define FM_FDISP_PWM_CK 20
+#define FM_FUSB_CK 21
+#define FM_FSSUSB_XHCI_CK 22
+#define FM_I2C_CK 23
+#define FM_TL_CK 24
+#define FM_DPMAIF_MAIN_CK 25
+#define FM_PWM_CK 26
+#define FM_SPMI_M_MST_CK 27
+#define FM_SPMI_P_MST_CK 28
+#define FM_DVFSRC_CK 29
+#define FM_MCUPM_CK 30
+#define FM_SFLASH_CK 31
+#define FM_GCPU_CK 32
+#define FM_SPI_CK 33
+#define FM_SPIS_CK 34
+#define FM_ECC_CK 35
+#define FM_NFI1X_CK 36
+#define FM_SPINFI_BCLK_CK 37
+#define FM_NETSYS_CK 38
+#define FM_MEDSYS_CK 39
+#define FM_HSM_CRYPTO_CK 40
+#define FM_HSM_ARC_CK 41
+#define FM_EIP97_CK 42
+#define FM_SNPS_ETH_312P5M_CK 43
+#define FM_SNPS_ETH_250M_CK 44
+#define FM_SNPS_PTP_CK 45
+#define FM_SNPS_ETH_50M_RMII_CK 46
+#define FM_NETSYS_500M_CK 47
+#define FM_NETSYS_MED_MCU_CK 48
+#define FM_NETSYS_WED_MCU_CK 49
+#define FM_NETSYS_2X_CK 50
+#define FM_SGMII_CK 51
+#define FM_SGMII_SBUS_CK 52
+/* ABIST Part */
+#define FM_APLL1_CK 2
+#define FM_APLL2_CK 3
+#define FM_APPLLGP_MON_FM_CK 4
+#define FM_ARMPLL_LL_CK 10
+#define FM_CCIPLL_CK 11
+#define FM_NET1PLL_CK 12
+#define FM_NET2PLL_CK 13
+#define FM_WEDMCUPLL_CK 14
+#define FM_MEDMCUPLL_CK 15
+#define FM_SGMIIPLL_CK 16
+#define FM_SNPSETHPLL_CK 17
+#define FM_DSI0_LNTC_DSICLK 20
+#define FM_DSI0_MPPLL_TST_CK 21
+#define FM_MDPLL1_FS26M_DRF_GUIDE 22
+#define FM_MFG_CK 23
+#define FM_MAINPLL_CK 24
+#define FM_MDPLL1_FS26M_GUIDE 25
+#define FM_MFGPLL_CK 26
+#define FM_MMPLL_CK 27
+#define FM_MMPLL_D3_CK 28
+#define FM_MPLL_CK 29
+#define FM_MSDCPLL_CK 30
+#define FM_RCLRPLL_DIV4_CK 31
+#define FM_RPHYPLL_DIV4_CK 33
+#define FM_ULPOSC_CK 37
+#define FM_UNIVPLL_CK 38
+#define FMEM_AFT_CH0 43
+#define FMEM_AFT_CH1 44
+#define FM_TRNG_FREQ_DEBUG_OUT0 45
+#define FM_TRNG_FREQ_DEBUG_OUT1 46
+#define FMEM_BFE_CH0 47
+#define FMEM_BFE_CH1 48
+#define FM_466M_FMEM_INFRASYS 49
+#define FM_MCUSYS_ARM_OUT_ALL 50
+#define FM_RTC32K_I_VAO 57
+/* ABIST2 Part */
+//#define FM_MCUPM_CK 13
+//#define FM_SFLASH_CK 14
+#define FM_UNIPLL_SES_CK 15
+//#define FM_ULPOSC_CK 16
+#define FM_ULPOSC_CORE_CK 17
+#define FM_SRCK_CK 18
+#define FM_MAINPLL_H728M_CK 19
+#define FM_MAINPLL_H546M_CK 20
+#define FM_MAINPLL_H436P8M_CK 21
+#define FM_MAINPLL_H364M_CK 22
+#define FM_MAINPLL_H312M_CK 23
+#define FM_UNIVPLL_1248M_CK 24
+#define FM_UNIVPLL_832M_CK 25
+#define FM_UNIVPLL_624M_CK 26
+#define FM_UNIVPLL_499M_CK 27
+#define FM_UNIVPLL_416M_CK 28
+#define FM_UNIVPLL_356P6M_CK 29
+//#define FM_MMPLL_D3_CK 30
+#define FM_MMPLL_D4_CK 31
+#define FM_MMPLL_D5_CK 32
+#define FM_MMPLL_D6_CK 33
+#define FM_MMPLL_D7_CK 34
+#define FM_MMPLL_D9_CK 35
+//#define FM_NET1PLL_CK 36
+//#define FM_NET2PLL_CK 37
+//#define FM_WEDMCUPLL_CK 38
+//#define FM_MEDMCUPLL_CK 39
+//#define FM_SGMIIPLL_CK 40
+
+#endif /* _CLK_MT6890_FMETER_H */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-gce.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-gce.c
new file mode 100755
index 0000000..8435baf
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-gce.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6890-clk.h>
+
+#define MT_CLKMGR_MODULE_INIT 0
+
+#define MT_CCF_BRINGUP 1
+
+#define INV_OFS -1
+
+
+
+static const struct mtk_gate_regs gce_cg_regs = {
+ .set_ofs = 0xf0,
+ .clr_ofs = 0xf0,
+ .sta_ofs = 0xf0,
+};
+
+#define GATE_GCE(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &gce_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+static const struct mtk_gate gce_clks[] = {
+ GATE_GCE(CLK_GCE_0, "gce_0",
+ "axi_ck"/* parent */, 16),
+};
+
+static int clk_mt6890_gce_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_GCE_NR_CLK);
+
+ mtk_clk_register_gates(node, gce_clks, ARRAY_SIZE(gce_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt6890_gce[] = {
+ { .compatible = "mediatek,mt6890-gce", },
+ {}
+};
+
+#if MT_CLKMGR_MODULE_INIT
+
+static struct platform_driver clk_mt6890_gce_drv = {
+ .probe = clk_mt6890_gce_probe,
+ .driver = {
+ .name = "clk-mt6890-gce",
+ .of_match_table = of_match_clk_mt6890_gce,
+ },
+};
+
+builtin_platform_driver(clk_mt6890_gce_drv);
+
+#else
+
+static struct platform_driver clk_mt6890_gce_drv = {
+ .probe = clk_mt6890_gce_probe,
+ .driver = {
+ .name = "clk-mt6890-gce",
+ .of_match_table = of_match_clk_mt6890_gce,
+ },
+};
+static int __init clk_mt6890_gce_platform_init(void)
+{
+ return platform_driver_register(&clk_mt6890_gce_drv);
+}
+arch_initcall(clk_mt6890_gce_platform_init);
+
+#endif /* MT_CLKMGR_MODULE_INIT */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-impe.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-impe.c
new file mode 100755
index 0000000..dfacd4a
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-impe.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6890-clk.h>
+
+#define MT_CLKMGR_MODULE_INIT 0
+
+#define MT_CCF_BRINGUP 1
+
+#define INV_OFS -1
+
+
+
+static const struct mtk_gate_regs impe_cg_regs = {
+ .set_ofs = 0xe00,
+ .clr_ofs = 0xe00,
+ .sta_ofs = 0xe00,
+};
+
+#define GATE_IMPE(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &impe_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+static const struct mtk_gate impe_clks[] = {
+ GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C0_RO, "impe_i2c0_ro",
+ "i2c_ck"/* parent */, 0),
+ GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C1_RO, "impe_i2c1_ro",
+ "i2c_ck"/* parent */, 1),
+ GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C2_RO, "impe_i2c2_ro",
+ "i2c_ck"/* parent */, 2),
+ GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C3_RO, "impe_i2c3_ro",
+ "i2c_ck"/* parent */, 3),
+ GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C4_RO, "impe_i2c4_ro",
+ "i2c_ck"/* parent */, 4),
+ GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C5_RO, "impe_i2c5_ro",
+ "i2c_ck"/* parent */, 5),
+};
+
+static int clk_mt6890_impe_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_IMPE_NR_CLK);
+
+ mtk_clk_register_gates(node, impe_clks, ARRAY_SIZE(impe_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt6890_impe[] = {
+ { .compatible = "mediatek,mt6890-imp_iic_wrap_e", },
+ {}
+};
+
+#if MT_CLKMGR_MODULE_INIT
+
+static struct platform_driver clk_mt6890_impe_drv = {
+ .probe = clk_mt6890_impe_probe,
+ .driver = {
+ .name = "clk-mt6890-impe",
+ .of_match_table = of_match_clk_mt6890_impe,
+ },
+};
+
+builtin_platform_driver(clk_mt6890_impe_drv);
+
+#else
+
+static struct platform_driver clk_mt6890_impe_drv = {
+ .probe = clk_mt6890_impe_probe,
+ .driver = {
+ .name = "clk-mt6890-impe",
+ .of_match_table = of_match_clk_mt6890_impe,
+ },
+};
+static int __init clk_mt6890_impe_platform_init(void)
+{
+ return platform_driver_register(&clk_mt6890_impe_drv);
+}
+arch_initcall(clk_mt6890_impe_platform_init);
+
+#endif /* MT_CLKMGR_MODULE_INIT */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-mfgcfg.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-mfgcfg.c
new file mode 100755
index 0000000..f990c6d
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-mfgcfg.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6890-clk.h>
+
+#define MT_CLKMGR_MODULE_INIT 0
+
+#define MT_CCF_BRINGUP 1
+
+#define INV_OFS -1
+
+/* get spm power status struct to register inside clk_data */
+static struct pwr_status pwr_stat = GATE_PWR_STAT(0x16C,
+ 0x170, INV_OFS, BIT(2), BIT(2));
+
+static const struct mtk_gate_regs mfgcfg_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_MFGCFG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mfgcfg_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ .pwr_stat = &pwr_stat, \
+ }
+
+static const struct mtk_gate mfgcfg_clks[] = {
+ GATE_MFGCFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d",
+ "mfg_ck"/* parent */, 0),
+};
+
+static int clk_mt6890_mfgcfg_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
+
+ mtk_clk_register_gates(node, mfgcfg_clks, ARRAY_SIZE(mfgcfg_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt6890_mfgcfg[] = {
+ { .compatible = "mediatek,mt6890-mfgsys", },
+ {}
+};
+
+#if MT_CLKMGR_MODULE_INIT
+
+static struct platform_driver clk_mt6890_mfgcfg_drv = {
+ .probe = clk_mt6890_mfgcfg_probe,
+ .driver = {
+ .name = "clk-mt6890-mfgcfg",
+ .of_match_table = of_match_clk_mt6890_mfgcfg,
+ },
+};
+
+builtin_platform_driver(clk_mt6890_mfgcfg_drv);
+
+#else
+
+static struct platform_driver clk_mt6890_mfgcfg_drv = {
+ .probe = clk_mt6890_mfgcfg_probe,
+ .driver = {
+ .name = "clk-mt6890-mfgcfg",
+ .of_match_table = of_match_clk_mt6890_mfgcfg,
+ },
+};
+static int __init clk_mt6890_mfgcfg_platform_init(void)
+{
+ return platform_driver_register(&clk_mt6890_mfgcfg_drv);
+}
+arch_initcall(clk_mt6890_mfgcfg_platform_init);
+
+#endif /* MT_CLKMGR_MODULE_INIT */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-mm.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-mm.c
new file mode 100755
index 0000000..9685da0
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890-mm.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt6890-clk.h>
+
+#define MT_CLKMGR_MODULE_INIT 0
+
+#define MT_CCF_BRINGUP 1
+
+#define INV_OFS -1
+
+
+
+static const struct mtk_gate_regs mm_cg0_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+static const struct mtk_gate_regs mm_cg1_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+static const struct mtk_gate_regs mm_cg2_regs = {
+ .set_ofs = 0x124,
+ .clr_ofs = 0x128,
+ .sta_ofs = 0x120,
+};
+
+#define GATE_MM0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm_cg0_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+#define GATE_MM1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm_cg1_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+#define GATE_MM2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm_cg2_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+static const struct mtk_gate mm_clks[] = {
+ GATE_MM0(CLK_MMSYS_MUTEX0, "mmsys_mutex0",
+ "mm_ck"/* parent */, 0),
+ GATE_MM0(CLK_MMSYS_APB_BUS, "mmsys_apb_bus",
+ "mm_ck"/* parent */, 1),
+ GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0",
+ "mm_ck"/* parent */, 2),
+ GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0",
+ "mm_ck"/* parent */, 3),
+ GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0",
+ "mm_ck"/* parent */, 4),
+ GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0",
+ "mm_ck"/* parent */, 5),
+ GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0",
+ "mm_ck"/* parent */, 6),
+ GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0",
+ "mm_ck"/* parent */, 7),
+ GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0",
+ "mm_ck"/* parent */, 8),
+ GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0",
+ "mm_ck"/* parent */, 9),
+ GATE_MM0(CLK_MMSYS_FAKE_ENG0, "mmsys_fake_eng0",
+ "mm_ck"/* parent */, 10),
+ GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0",
+ "mm_ck"/* parent */, 11),
+ GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0",
+ "mm_ck"/* parent */, 12),
+ GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0",
+ "mm_ck"/* parent */, 13),
+ GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0",
+ "mm_ck"/* parent */, 14),
+ GATE_MM0(CLK_MM_DBPI0, "mm_dbpi0",
+ "mm_ck"/* parent */, 15),
+ GATE_MM0(CLK_MM_DISP_DSI0, "mm_disp_dsi0",
+ "mm_ck"/* parent */, 16),
+ GATE_MM0(CLK_MMSYS_SMI_COMMON, "mmsys_smi_common",
+ "mm_ck"/* parent */, 17),
+ GATE_MM1(CLK_MMSYS_SMI_COMMON, "disp_axi",
+ "axi_ck"/* parent */, 0),
+ GATE_MM1(CLK_MMSYS_SMI_COMMON, "dsi",
+ "mm_ck"/* parent */, 16),
+ GATE_MM2(CLK_MMSYS_SMI_COMMON, "dbi",
+ "dbi_ck"/* parent */, 0),
+};
+
+static int clk_mt6890_mm_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+
+ mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt6890_mm[] = {
+ { .compatible = "mediatek,mt6890-mmsys_config", },
+ {}
+};
+
+#if MT_CLKMGR_MODULE_INIT
+
+static struct platform_driver clk_mt6890_mm_drv = {
+ .probe = clk_mt6890_mm_probe,
+ .driver = {
+ .name = "clk-mt6890-mm",
+ .of_match_table = of_match_clk_mt6890_mm,
+ },
+};
+
+builtin_platform_driver(clk_mt6890_mm_drv);
+
+#else
+
+static struct platform_driver clk_mt6890_mm_drv = {
+ .probe = clk_mt6890_mm_probe,
+ .driver = {
+ .name = "clk-mt6890-mm",
+ .of_match_table = of_match_clk_mt6890_mm,
+ },
+};
+static int __init clk_mt6890_mm_platform_init(void)
+{
+ return platform_driver_register(&clk_mt6890_mm_drv);
+}
+arch_initcall(clk_mt6890_mm_platform_init);
+
+#endif /* MT_CLKMGR_MODULE_INIT */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890.c
new file mode 100755
index 0000000..de820bc
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt6890.c
@@ -0,0 +1,2560 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/seq_file.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-gate.h"
+#include "clkdbg.h"
+#include "clkdbg-mt6890.h"
+
+#include <dt-bindings/clock/mt6890-clk.h>
+
+/* bringup config */
+#define MT_CCF_BRINGUP 1
+#define MT_CCF_MUX_DISABLE 0
+#define MT_CCF_PLL_DISABLE 0
+
+/* Regular Number Definition */
+#define INV_OFS -1
+#define INV_BIT -1
+
+/* TOPCK MUX SEL REG */
+#define CLK_CFG_UPDATE 0x0004
+#define CLK_CFG_UPDATE1 0x0008
+#define CLK_CFG_0 0x0010
+#define CLK_CFG_0_SET 0x0014
+#define CLK_CFG_0_CLR 0x0018
+#define CLK_CFG_1 0x0020
+#define CLK_CFG_1_SET 0x0024
+#define CLK_CFG_1_CLR 0x0028
+#define CLK_CFG_2 0x0030
+#define CLK_CFG_2_SET 0x0034
+#define CLK_CFG_2_CLR 0x0038
+#define CLK_CFG_3 0x0040
+#define CLK_CFG_3_SET 0x0044
+#define CLK_CFG_3_CLR 0x0048
+#define CLK_CFG_4 0x0050
+#define CLK_CFG_4_SET 0x0054
+#define CLK_CFG_4_CLR 0x0058
+#define CLK_CFG_5 0x0060
+#define CLK_CFG_5_SET 0x0064
+#define CLK_CFG_5_CLR 0x0068
+#define CLK_CFG_6 0x0070
+#define CLK_CFG_6_SET 0x0074
+#define CLK_CFG_6_CLR 0x0078
+#define CLK_CFG_7 0x0080
+#define CLK_CFG_7_SET 0x0084
+#define CLK_CFG_7_CLR 0x0088
+#define CLK_CFG_8 0x0090
+#define CLK_CFG_8_SET 0x0094
+#define CLK_CFG_8_CLR 0x0098
+#define CLK_CFG_9 0x00A0
+#define CLK_CFG_9_SET 0x00A4
+#define CLK_CFG_9_CLR 0x00A8
+#define CLK_CFG_10 0x00B0
+#define CLK_CFG_10_SET 0x00B4
+#define CLK_CFG_10_CLR 0x00B8
+#define CLK_CFG_11 0x00C0
+#define CLK_CFG_11_SET 0x00C4
+#define CLK_CFG_11_CLR 0x00C8
+#define CLK_CFG_12 0x00D0
+#define CLK_CFG_12_SET 0x00D4
+#define CLK_CFG_12_CLR 0x00D8
+#define CLK_AUDDIV_0 0x0320
+
+/* TOPCK MUX SHIFT */
+#define TOP_MUX_AXI_SHIFT 0
+#define TOP_MUX_SPM_SHIFT 1
+#define TOP_MUX_BUS_AXIMEM_SHIFT 2
+#define TOP_MUX_MM_SHIFT 3
+#define TOP_MUX_MFG_REF_SHIFT 4
+#define TOP_MUX_UART_SHIFT 5
+#define TOP_MUX_MSDC50_0_HCLK_SHIFT 6
+#define TOP_MUX_MSDC50_0_SHIFT 7
+#define TOP_MUX_MSDC30_1_SHIFT 8
+#define TOP_MUX_AUDIO_SHIFT 9
+#define TOP_MUX_AUD_INTBUS_SHIFT 10
+#define TOP_MUX_AUD_ENGEN1_SHIFT 11
+#define TOP_MUX_AUD_ENGEN2_SHIFT 12
+#define TOP_MUX_AUD_1_SHIFT 13
+#define TOP_MUX_AUD_2_SHIFT 14
+#define TOP_MUX_PWRAP_ULPOSC_SHIFT 15
+#define TOP_MUX_ATB_SHIFT 16
+#define TOP_MUX_PWRMCU_SHIFT 17
+#define TOP_MUX_DBI_SHIFT 18
+#define TOP_MUX_DISP_PWM_SHIFT 19
+#define TOP_MUX_USB_TOP_SHIFT 20
+#define TOP_MUX_SSUSB_XHCI_SHIFT 21
+#define TOP_MUX_I2C_SHIFT 22
+#define TOP_MUX_TL_SHIFT 23
+#define TOP_MUX_DPMAIF_MAIN_SHIFT 24
+#define TOP_MUX_PWM_SHIFT 25
+#define TOP_MUX_SPMI_M_MST_SHIFT 26
+#define TOP_MUX_SPMI_P_MST_SHIFT 27
+#define TOP_MUX_DVFSRC_SHIFT 28
+#define TOP_MUX_MCUPM_SHIFT 29
+#define TOP_MUX_SFLASH_SHIFT 30
+#define TOP_MUX_GCPU_SHIFT 0
+#define TOP_MUX_SPI_SHIFT 1
+#define TOP_MUX_SPIS_SHIFT 2
+#define TOP_MUX_ECC_SHIFT 3
+#define TOP_MUX_NFI1X_SHIFT 4
+#define TOP_MUX_SPINFI_BCLK_SHIFT 5
+#define TOP_MUX_NETSYS_SHIFT 6
+#define TOP_MUX_MEDSYS_SHIFT 7
+#define TOP_MUX_HSM_CRYPTO_SHIFT 8
+#define TOP_MUX_HSM_ARC_SHIFT 9
+#define TOP_MUX_EIP97_SHIFT 10
+#define TOP_MUX_SNPS_ETH_312P5M_SHIFT 11
+#define TOP_MUX_SNPS_ETH_250M_SHIFT 12
+#define TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT 13
+#define TOP_MUX_SNPS_ETH_50M_RMII_SHIFT 14
+#define TOP_MUX_NETSYS_500M_SHIFT 15
+#define TOP_MUX_NETSYS_MED_MCU_SHIFT 16
+#define TOP_MUX_NETSYS_WED_MCU_SHIFT 17
+#define TOP_MUX_NETSYS_2X_SHIFT 18
+#define TOP_MUX_SGMII_SHIFT 19
+#define TOP_MUX_SGMII_SBUS_SHIFT 20
+
+/* TOPCK DIVIDER REG */
+#define CLK_AUDDIV_2 0x0328
+#define CLK_AUDDIV_3 0x0334
+
+/* APMIXED PLL REG */
+#define ARMPLL_LL_CON0 0x204
+#define ARMPLL_LL_CON1 0x208
+#define ARMPLL_LL_CON2 0x20c
+#define ARMPLL_LL_CON3 0x210
+#define ARMPLL_LL_CON4 0x214
+#define CCIPLL_CON0 0x218
+#define CCIPLL_CON1 0x21c
+#define CCIPLL_CON2 0x220
+#define CCIPLL_CON3 0x224
+#define CCIPLL_CON4 0x228
+#define MPLL_CON0 0x604
+#define MPLL_CON1 0x608
+#define MPLL_CON2 0x60c
+#define MPLL_CON3 0x610
+#define MPLL_CON4 0x614
+#define MAINPLL_CON0 0x404
+#define MAINPLL_CON1 0x408
+#define MAINPLL_CON2 0x40c
+#define MAINPLL_CON3 0x410
+#define MAINPLL_CON4 0x414
+#define UNIVPLL_CON0 0x418
+#define UNIVPLL_CON1 0x41c
+#define UNIVPLL_CON2 0x420
+#define UNIVPLL_CON3 0x424
+#define UNIVPLL_CON4 0x428
+#define MSDCPLL_CON0 0x22c
+#define MSDCPLL_CON1 0x230
+#define MSDCPLL_CON2 0x234
+#define MSDCPLL_CON3 0x238
+#define MSDCPLL_CON4 0x23c
+#define MMPLL_CON0 0x42c
+#define MMPLL_CON1 0x430
+#define MMPLL_CON2 0x434
+#define MMPLL_CON3 0x438
+#define MMPLL_CON4 0x43c
+#define MFGPLL_CON0 0x618
+#define MFGPLL_CON1 0x61c
+#define MFGPLL_CON2 0x620
+#define MFGPLL_CON3 0x624
+#define MFGPLL_CON4 0x628
+#define APLL1_CON0 0x454
+#define APLL1_CON1 0x458
+#define APLL1_CON2 0x45c
+#define APLL1_CON3 0x460
+#define APLL1_CON4 0x464
+#define APLL1_CON5 0x468
+#define APLL2_CON0 0x46c
+#define APLL2_CON1 0x470
+#define APLL2_CON2 0x474
+#define APLL2_CON3 0x478
+#define APLL2_CON4 0x47c
+#define APLL2_CON5 0x480
+#define NET1PLL_CON0 0x804
+#define NET1PLL_CON1 0x808
+#define NET1PLL_CON2 0x80c
+#define NET1PLL_CON3 0x810
+#define NET1PLL_CON4 0x814
+#define NET2PLL_CON0 0x818
+#define NET2PLL_CON1 0x81c
+#define NET2PLL_CON2 0x820
+#define NET2PLL_CON3 0x824
+#define NET2PLL_CON4 0x828
+#define WEDMCUPLL_CON0 0x82c
+#define WEDMCUPLL_CON1 0x830
+#define WEDMCUPLL_CON2 0x834
+#define WEDMCUPLL_CON3 0x838
+#define WEDMCUPLL_CON4 0x83c
+#define MEDMCUPLL_CON0 0x840
+#define MEDMCUPLL_CON1 0x844
+#define MEDMCUPLL_CON2 0x848
+#define MEDMCUPLL_CON3 0x84c
+#define MEDMCUPLL_CON4 0x850
+#define SGMIIPLL_CON0 0x240
+#define SGMIIPLL_CON1 0x244
+#define SGMIIPLL_CON2 0x248
+#define SGMIIPLL_CON3 0x24c
+#define SGMIIPLL_CON4 0x250
+#define APLL1_TUNER_CON0 0x0054
+#define APLL2_TUNER_CON0 0x0058
+#define AP_PLL_CON0 0x0
+
+static DEFINE_SPINLOCK(mt6890_clk_lock);
+
+static void __iomem *apmixed_base;
+
+static const struct mtk_fixed_factor top_divs[] = {
+ FACTOR(CLK_TOP_ARMPLL_LL_CK_VRPOC, "armpll_ll_vrpoc",
+ "armpll_ll", 1, 1),
+ FACTOR(CLK_TOP_CCIPLL_CK_VRPOC_CCI, "ccipll_vrpoc_cci",
+ "ccipll", 1, 1),
+ FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck",
+ "mfgpll", 1, 1),
+ FACTOR(CLK_TOP_MAINPLL, "mainpll_ck",
+ "mainpll", 1, 1),
+ FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3",
+ "mainpll", 1, 3),
+ FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4",
+ "mainpll", 1, 4),
+ FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2",
+ "mainpll", 1, 8),
+ FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4",
+ "mainpll", 1, 16),
+ FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8",
+ "mainpll", 1, 32),
+ FACTOR(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16",
+ "mainpll", 1, 64),
+ FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5",
+ "mainpll", 1, 5),
+ FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2",
+ "mainpll", 1, 10),
+ FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4",
+ "mainpll", 1, 20),
+ FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8",
+ "mainpll", 1, 40),
+ FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6",
+ "mainpll", 1, 6),
+ FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2",
+ "mainpll", 1, 12),
+ FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4",
+ "mainpll", 1, 24),
+ FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8",
+ "mainpll", 1, 48),
+ FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7",
+ "mainpll", 1, 7),
+ FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2",
+ "mainpll", 1, 14),
+ FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4",
+ "mainpll", 1, 28),
+ FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8",
+ "mainpll", 1, 56),
+ FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8",
+ "mainpll", 1, 8),
+ FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9",
+ "mainpll", 1, 9),
+ FACTOR(CLK_TOP_UNIVPLL, "univpll_ck",
+ "univpll", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2",
+ "univpll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3",
+ "univpll", 1, 3),
+ FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4",
+ "univpll", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2",
+ "univpll", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4",
+ "univpll", 1, 16),
+ FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8",
+ "univpll", 1, 32),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5",
+ "univpll", 1, 5),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2",
+ "univpll", 1, 10),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4",
+ "univpll", 1, 20),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8",
+ "univpll", 1, 40),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D16, "univpll_d5_d16",
+ "univpll", 1, 80),
+ FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6",
+ "univpll", 1, 6),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2",
+ "univpll", 1, 12),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4",
+ "univpll", 1, 24),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8",
+ "univpll", 1, 48),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16",
+ "univpll", 1, 96),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7",
+ "univpll", 1, 7),
+ FACTOR(CLK_TOP_UNIVPLL_D7_D2, "univpll_d7_d2",
+ "univpll", 1, 14),
+ FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m_ck",
+ "univpll", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2",
+ "univpll", 1, 26),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4",
+ "univpll", 1, 52),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8",
+ "univpll", 1, 104),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16",
+ "univpll", 1, 208),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32",
+ "univpll", 1, 416),
+ FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck",
+ "univpll", 1, 13),
+ FACTOR(CLK_TOP_USB20_PLL_D2, "usb20_pll_d2",
+ "univpll", 1, 26),
+ FACTOR(CLK_TOP_USB20_PLL_D4, "usb20_pll_d4",
+ "univpll", 1, 52),
+ FACTOR(CLK_TOP_APLL1, "apll1_ck",
+ "apll1", 1, 1),
+ FACTOR(CLK_TOP_APLL1_D2, "apll1_d2",
+ "apll1", 1, 2),
+ FACTOR(CLK_TOP_APLL1_D4, "apll1_d4",
+ "apll1", 1, 4),
+ FACTOR(CLK_TOP_APLL1_D8, "apll1_d8",
+ "apll1", 1, 8),
+ FACTOR(CLK_TOP_APLL2, "apll2_ck",
+ "apll2", 1, 1),
+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2",
+ "apll2", 1, 2),
+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4",
+ "apll2", 1, 4),
+ FACTOR(CLK_TOP_APLL2_D8, "apll2_d8",
+ "apll2", 1, 8),
+ FACTOR(CLK_TOP_MMPLL, "mmpll_ck",
+ "mmpll", 1, 1),
+ FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3",
+ "mmpll", 1, 3),
+ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4",
+ "mmpll", 1, 4),
+ FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2",
+ "mmpll", 1, 8),
+ FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4",
+ "mmpll", 1, 16),
+ FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5",
+ "mmpll", 1, 5),
+ FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2",
+ "mmpll", 1, 10),
+ FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4",
+ "mmpll", 1, 20),
+ FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6",
+ "mmpll", 1, 6),
+ FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2",
+ "mmpll", 1, 12),
+ FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7",
+ "mmpll", 1, 7),
+ FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9",
+ "mmpll", 1, 9),
+ FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck",
+ "net1pll", 1, 1),
+ FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2",
+ "net1pll", 1, 2),
+ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4",
+ "net1pll", 1, 4),
+ FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8",
+ "net1pll", 1, 8),
+ FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16",
+ "net1pll", 1, 16),
+ FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck",
+ "msdcpll", 1, 1),
+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2",
+ "msdcpll", 1, 2),
+ FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4",
+ "msdcpll", 1, 4),
+ FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8",
+ "msdcpll", 1, 8),
+ FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16",
+ "msdcpll", 1, 16),
+ FACTOR(CLK_TOP_CLKRTC, "clkrtc",
+ "clk32k", 1, 1),
+ FACTOR(CLK_TOP_TCK_26M_MX8, "tck_26m_mx8_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_TCK_26M_MX9, "tck_26m_mx9_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_TCK_26M_MX10, "tck_26m_mx10_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_TCK_26M_MX11, "tck_26m_mx11_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_TCK_26M_MX12, "tck_26m_mx12_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_CSW_FAXI, "csw_faxi_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_CSW_F26M_CK_D52, "csw_f26m_d52",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_CSW_F26M_CK_D2, "csw_f26m_d2",
+ "clk26m", 1, 2),
+ FACTOR(CLK_TOP_OSC, "osc_ck",
+ "ulposc", 1, 1),
+ FACTOR(CLK_TOP_OSC_D2, "osc_d2",
+ "ulposc", 1, 2),
+ FACTOR(CLK_TOP_OSC_D4, "osc_d4",
+ "ulposc", 1, 4),
+ FACTOR(CLK_TOP_OSC_D8, "osc_d8",
+ "ulposc", 1, 8),
+ FACTOR(CLK_TOP_OSC_D16, "osc_d16",
+ "ulposc", 1, 16),
+ FACTOR(CLK_TOP_OSC_D10, "osc_d10",
+ "ulposc", 1, 10),
+ FACTOR(CLK_TOP_OSC_D20, "osc_d20",
+ "ulposc", 1, 20),
+ FACTOR(CLK_TOP_TVDPLL_D5, "tvdpll_d5",
+ "net1pll", 1, 5),
+ FACTOR(CLK_TOP_TVDPLL_D10, "tvdpll_d10",
+ "net1pll", 1, 10),
+ FACTOR(CLK_TOP_TVDPLL_D25, "tvdpll_d25",
+ "net1pll", 1, 25),
+ FACTOR(CLK_TOP_TVDPLL_D50, "tvdpll_d50",
+ "net1pll", 1, 50),
+ FACTOR(CLK_TOP_NET2PLL, "net2pll_ck",
+ "net2pll", 1, 1),
+ FACTOR(CLK_TOP_WEDMCUPLL, "wedmcupll_ck",
+ "wedmcupll", 1, 1),
+ FACTOR(CLK_TOP_MEDMCUPLL, "medmcupll_ck",
+ "medmcupll", 1, 1),
+ FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck",
+ "sgmiipll", 1, 1),
+ FACTOR(CLK_TOP_F26M, "f26m_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_FRTC, "frtc_ck",
+ "clk32k", 1, 1),
+ FACTOR(CLK_TOP_AXI, "axi_ck",
+ "axi_sel", 1, 1),
+ FACTOR(CLK_TOP_SPM, "spm_ck",
+ "spm_sel", 1, 1),
+ FACTOR(CLK_TOP_BUS, "bus_ck",
+ "bus_aximem_sel", 1, 1),
+ FACTOR(CLK_TOP_MM, "mm_ck",
+ "mm_sel", 1, 1),
+ FACTOR(CLK_TOP_MFG_REF, "mfg_ref_ck",
+ "mfg_ref_sel", 1, 1),
+ FACTOR(CLK_TOP_MFG, "mfg_ck",
+ "mfg_sel", 1, 1),
+ FACTOR(CLK_TOP_FUART, "fuart_ck",
+ "uart_sel", 1, 1),
+ FACTOR(CLK_TOP_MSDC50_0_HCLK, "msdc50_0_h_ck",
+ "msdc50_0_h_sel", 1, 1),
+ FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck",
+ "msdc50_0_sel", 1, 1),
+ FACTOR(CLK_TOP_MSDC30_1, "msdc30_1_ck",
+ "msdc30_1_sel", 1, 1),
+ FACTOR(CLK_TOP_AUDIO, "audio_ck",
+ "audio_sel", 1, 1),
+ FACTOR(CLK_TOP_AUD_INTBUS, "aud_intbus_ck",
+ "aud_intbus_sel", 1, 1),
+ FACTOR(CLK_TOP_AUD_ENGEN1, "aud_engen1_ck",
+ "aud_engen1_sel", 1, 1),
+ FACTOR(CLK_TOP_AUD_ENGEN2, "aud_engen2_ck",
+ "aud_engen2_sel", 1, 1),
+ FACTOR(CLK_TOP_AUD_1, "aud_1_ck",
+ "aud_1_sel", 1, 1),
+ FACTOR(CLK_TOP_AUD_2, "aud_2_ck",
+ "aud_2_sel", 1, 1),
+ FACTOR(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_ck",
+ "pwrap_ulposc_sel", 1, 1),
+ FACTOR(CLK_TOP_ATB, "atb_ck",
+ "atb_sel", 1, 1),
+ FACTOR(CLK_TOP_PWRMCU, "pwrmcu_ck",
+ "pwrmcu_sel", 1, 1),
+ FACTOR(CLK_TOP_DBI, "dbi_ck",
+ "dbi_sel", 1, 1),
+ FACTOR(CLK_TOP_FDISP_PWM, "fdisp_pwm_ck",
+ "disp_pwm_sel", 1, 1),
+ FACTOR(CLK_TOP_FUSB_TOP, "fusb_ck",
+ "usb_sel", 1, 1),
+ FACTOR(CLK_TOP_FSSUSB_XHCI, "fssusb_xhci_ck",
+ "ssusb_xhci_sel", 1, 1),
+ FACTOR(CLK_TOP_I2C, "i2c_ck",
+ "i2c_sel", 1, 1),
+ FACTOR(CLK_TOP_TL, "tl_ck",
+ "tl_sel", 1, 1),
+ FACTOR(CLK_TOP_DPMAIF_MAIN, "dpmaif_main_ck",
+ "dpmaif_main_sel", 1, 1),
+ FACTOR(CLK_TOP_PWM, "pwm_ck",
+ "pwm_sel", 1, 1),
+ FACTOR(CLK_TOP_SPMI_M_MST, "spmi_m_mst_ck",
+ "spmi_m_mst_sel", 1, 1),
+ FACTOR(CLK_TOP_SPMI_P_MST, "spmi_p_mst_ck",
+ "spmi_p_mst_sel", 1, 1),
+ FACTOR(CLK_TOP_DVFSRC, "dvfsrc_ck",
+ "dvfsrc_sel", 1, 1),
+ FACTOR(CLK_TOP_MCUPM, "mcupm_ck",
+ "mcupm_sel", 1, 1),
+ FACTOR(CLK_TOP_SFLASH, "sflash_ck",
+ "sflash_sel", 1, 1),
+ FACTOR(CLK_TOP_GCPU, "gcpu_ck",
+ "gcpu_sel", 1, 1),
+ FACTOR(CLK_TOP_SPI, "spi_ck",
+ "spi_sel", 1, 1),
+ FACTOR(CLK_TOP_SPIS, "spis_ck",
+ "spis_sel", 1, 1),
+ FACTOR(CLK_TOP_ECC, "ecc_ck",
+ "ecc_sel", 1, 1),
+ FACTOR(CLK_TOP_NFI1X, "nfi1x_ck",
+ "nfi1x_sel", 1, 1),
+ FACTOR(CLK_TOP_SPINFI_BCLK, "spinfi_bclk_ck",
+ "spinfi_bclk_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS, "netsys_ck",
+ "netsys_sel", 1, 1),
+ FACTOR(CLK_TOP_MEDSYS, "medsys_ck",
+ "medsys_sel", 1, 1),
+ /* HSM isn't in kernel */
+ FACTOR(CLK_TOP_EIP97, "eip97_ck",
+ "eip97_sel", 1, 1),
+ FACTOR(CLK_TOP_SNPS_ETH_312P5M, "snps_eth_312p5m_ck",
+ "snps_eth_312p5m_sel", 1, 1),
+ FACTOR(CLK_TOP_SNPS_ETH_250M, "snps_eth_250m_ck",
+ "snps_eth_250m_sel", 1, 1),
+ FACTOR(CLK_TOP_SNPS_ETH_62P4M_PTP, "snps_ptp_ck",
+ "snps_ptp_sel", 1, 1),
+ FACTOR(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii_ck",
+ "snps_rmii_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m_ck",
+ "netsys_500m_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS_MED_MCU, "netsys_med_mcu_ck",
+ "netsys_med_mcu_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu_ck",
+ "netsys_wed_mcu_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x_ck",
+ "netsys_2x_sel", 1, 1),
+ FACTOR(CLK_TOP_SGMII, "sgmii_ck",
+ "sgmii_sel", 1, 1),
+ FACTOR(CLK_TOP_SGMII_SBUS, "sgmii_sbus_ck",
+ "sgmii_sbus_sel", 1, 1),
+ FACTOR(CLK_TOP_SYS_26M, "sys_26m_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_F_UFS_MP_SAP_CFG, "ufs_cfg_ck",
+ "clk26m", 1, 1),
+ FACTOR(CLK_TOP_F_UFS_TICK1US, "f_ufs_tick1us_ck",
+ "clk26m", 1, 1),
+};
+
+static const char * const axi_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d4",
+ "mainpll_d7_d2",
+ "mainpll_d4_d2",
+ "mainpll_d5_d2",
+ "mainpll_d6_d2",
+ "osc_d4"
+};
+
+static const char * const spm_parents[] = {
+ "tck_26m_mx9_ck",
+ "osc_d10",
+ "mainpll_d7_d4",
+ "clkrtc"
+};
+
+static const char * const bus_aximem_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d7_d2",
+ "mainpll_d4_d2",
+ "mainpll_d5_d2",
+ "mainpll_d6"
+};
+
+static const char * const mm_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d2",
+ "univpll_d7_d2",
+ "mainpll_d6_d2",
+ "univpll_d4_d4"
+};
+
+static const char * const mfg_ref_parents[] = {
+ "tck_26m_mx9_ck",
+ "tck_26m_mx9_ck",
+ "univpll_d6",
+ "mainpll_d5_d2"
+};
+
+static const char * const mfg_parents[] = {
+ "mfg_ref_sel",
+ "mfgpll_ck"
+};
+
+static const char * const uart_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d8"
+};
+
+static const char * const msdc50_0_h_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d2",
+ "mainpll_d6_d2"
+};
+
+static const char * const msdc50_0_parents[] = {
+ "tck_26m_mx9_ck",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "univpll_d4_d4",
+ "mainpll_d6_d2",
+ "univpll_d4_d2"
+};
+
+static const char * const msdc30_1_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d2",
+ "mainpll_d6_d2",
+ "mainpll_d7_d2",
+ "msdcpll_d2"
+};
+
+static const char * const audio_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d5_d8",
+ "mainpll_d7_d8",
+ "mainpll_d4_d16"
+};
+
+static const char * const aud_intbus_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d4",
+ "mainpll_d7_d4"
+};
+
+static const char * const aud_engen1_parents[] = {
+ "tck_26m_mx9_ck",
+ "apll1_d2",
+ "apll1_d4",
+ "apll1_d8"
+};
+
+static const char * const aud_engen2_parents[] = {
+ "tck_26m_mx9_ck",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8"
+};
+
+static const char * const aud_1_parents[] = {
+ "tck_26m_mx9_ck",
+ "apll1_ck"
+};
+
+static const char * const aud_2_parents[] = {
+ "tck_26m_mx9_ck",
+ "apll2_ck"
+};
+
+static const char * const pwrap_ulposc_parents[] = {
+ "osc_d10",
+ "tck_26m_mx9_ck",
+ "osc_d4",
+ "osc_d8",
+ "osc_d16"
+};
+
+static const char * const atb_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d2",
+ "mainpll_d5_d2"
+};
+
+static const char * const pwrmcu_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d5_d2",
+ "univpll_d5_d2",
+ "mainpll_d4_d2",
+ "univpll_d4_d2",
+ "mainpll_d6"
+};
+
+static const char * const dbi_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d5_d4",
+ "univpll_d6_d4",
+ "univpll_d4_d8",
+ "univpll_d6_d8"
+};
+
+static const char * const disp_pwm_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d4",
+ "osc_d2",
+ "osc_d4",
+ "osc_d16"
+};
+
+static const char * const usb_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d5_d4",
+ "univpll_d6_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const ssusb_xhci_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d5_d4",
+ "univpll_d6_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const i2c_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d8",
+ "univpll_d5_d4"
+};
+
+static const char * const tl_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d4",
+ "mainpll_d6_d4"
+};
+
+static const char * const dpmaif_main_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d4_d4",
+ "mainpll_d6",
+ "mainpll_d4_d2",
+ "univpll_d4_d2"
+};
+
+static const char * const pwm_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d4_d8"
+};
+
+static const char * const spmi_m_mst_parents[] = {
+ "tck_26m_mx9_ck",
+ "csw_f26m_d2",
+ "osc_d8",
+ "osc_d10",
+ "osc_d16",
+ "osc_d20",
+ "clkrtc"
+};
+
+static const char * const spmi_p_mst_parents[] = {
+ "tck_26m_mx9_ck",
+ "csw_f26m_d2",
+ "osc_d8",
+ "osc_d10",
+ "osc_d16",
+ "osc_d20",
+ "clkrtc",
+ "mainpll_d7_d8",
+ "mainpll_d5_d8"
+};
+
+static const char * const dvfsrc_parents[] = {
+ "tck_26m_mx9_ck",
+ "osc_d10"
+};
+
+static const char * const mcupm_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d6_d4",
+ "mainpll_d6_d2"
+};
+
+static const char * const sflash_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d7_d8",
+ "univpll_d6_d8",
+ "univpll_d5_d8"
+};
+
+static const char * const gcpu_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6",
+ "mainpll_d6",
+ "univpll_d4_d2",
+ "mainpll_d4_d2",
+ "univpll_d6_d2"
+};
+
+static const char * const spi_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d8",
+ "univpll_d4_d8",
+ "univpll_d6_d4",
+ "univpll_d5_d4",
+ "univpll_d4_d4",
+ "univpll_d7_d2",
+ "univpll_d6_d2"
+};
+
+static const char * const spis_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d8",
+ "univpll_d4_d8",
+ "univpll_d6_d4",
+ "univpll_d4_d4",
+ "univpll_d6_d2",
+ "univpll_d4_d2",
+ "univpll_d6"
+};
+
+static const char * const ecc_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d4_d4",
+ "mainpll_d9",
+ "univpll_d4_d2"
+};
+
+static const char * const nfi1x_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d5_d4",
+ "mainpll_d7_d4",
+ "mainpll_d6_d4",
+ "univpll_d6_d4",
+ "mainpll_d4_d4",
+ "univpll_d4_d4",
+ "mainpll_d6_d2"
+};
+
+static const char * const spinfi_bclk_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d8",
+ "univpll_d5_d8",
+ "mainpll_d4_d8",
+ "univpll_d4_d8",
+ "mainpll_d6_d4",
+ "univpll_d6_d4",
+ "univpll_d5_d4"
+};
+
+static const char * const netsys_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d4_d8",
+ "mainpll_d7_d2",
+ "mainpll_d9",
+ "univpll_d7"
+};
+
+static const char * const medsys_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d4_d8",
+ "mainpll_d7_d2",
+ "mainpll_d9",
+ "univpll_d7"
+};
+
+static const char * const eip97_parents[] = {
+ "tck_26m_mx9_ck",
+ "net2pll_ck",
+ "mainpll_d3",
+ "univpll_d4",
+ "mainpll_d4",
+ "univpll_d5",
+ "mainpll_d6",
+ "mainpll_d5_d2"
+};
+
+static const char * const snps_eth_312p5m_parents[] = {
+ "tck_26m_mx9_ck",
+ "tvdpll_d8"
+};
+
+static const char * const snps_eth_250m_parents[] = {
+ "tck_26m_mx9_ck",
+ "tvdpll_d10"
+};
+
+static const char * const snps_ptp_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d5_d8"
+};
+
+static const char * const snps_rmii_parents[] = {
+ "tck_26m_mx9_ck",
+ "tvdpll_d50"
+};
+
+static const char * const netsys_500m_parents[] = {
+ "tck_26m_mx9_ck",
+ "tvdpll_d5"
+};
+
+static const char * const netsys_med_mcu_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d6_d4",
+ "mainpll_d4_d2",
+ "univpll_d7",
+ "medmcupll_ck"
+};
+
+static const char * const netsys_wed_mcu_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d6_d2",
+ "mainpll_d6",
+ "mainpll_d5",
+ "wedmcupll_ck"
+};
+
+static const char * const netsys_2x_parents[] = {
+ "tck_26m_mx9_ck",
+ "univpll_d5_d4",
+ "mainpll_d4_d2",
+ "mainpll_d4",
+ "net2pll_ck"
+};
+
+static const char * const sgmii_parents[] = {
+ "tck_26m_mx9_ck",
+ "sgmiipll_ck"
+};
+
+static const char * const sgmii_sbus_parents[] = {
+ "tck_26m_mx9_ck",
+ "mainpll_d7_d4"
+};
+
+static const char * const apll_i2s0_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s1_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s2_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s4_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_tdmout_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s5_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s6_mck_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const struct mtk_mux top_muxes[] = {
+#if MT_CCF_MUX_DISABLE
+ /* CLK_CFG_0 */
+ MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL/* dts */, "axi_sel",
+ axi_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AXI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPM_SEL/* dts */, "spm_sel",
+ spm_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SPM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_BUS_AXIMEM_SEL/* dts */, "bus_aximem_sel",
+ bus_aximem_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_BUS_AXIMEM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MM_SEL/* dts */, "mm_sel",
+ mm_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MM_SHIFT/* upd shift */),
+ /* CLK_CFG_1 */
+ MUX_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL/* dts */, "mfg_ref_sel",
+ mfg_ref_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MFG_REF_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MFG_SEL/* dts */, "mfg_sel",
+ mfg_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 2/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, INV_OFS/* upd ofs */,
+ INV_BIT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_UART_SEL/* dts */, "uart_sel",
+ uart_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_UART_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL/* dts */, "msdc50_0_h_sel",
+ msdc50_0_h_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MSDC50_0_HCLK_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL/* dts */, "msdc50_0_sel",
+ msdc50_0_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MSDC50_0_SHIFT/* upd shift */),
+ /* CLK_CFG_2 */
+ MUX_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL/* dts */, "msdc30_1_sel",
+ msdc30_1_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MSDC30_1_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUDIO_SEL/* dts */, "audio_sel",
+ audio_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUDIO_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL/* dts */, "aud_intbus_sel",
+ aud_intbus_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_INTBUS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL/* dts */, "aud_engen1_sel",
+ aud_engen1_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 24/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_ENGEN1_SHIFT/* upd shift */),
+ /* CLK_CFG_3 */
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL/* dts */, "aud_engen2_sel",
+ aud_engen2_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_ENGEN2_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_1_SEL/* dts */, "aud_1_sel",
+ aud_1_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_1_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_2_SEL/* dts */, "aud_2_sel",
+ aud_2_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_2_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL/* dts */, "pwrap_ulposc_sel",
+ pwrap_ulposc_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_PWRAP_ULPOSC_SHIFT/* upd shift */),
+ /* CLK_CFG_4 */
+ MUX_CLR_SET_UPD(CLK_TOP_ATB_SEL/* dts */, "atb_sel",
+ atb_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_ATB_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_PWRMCU_SEL/* dts */, "pwrmcu_sel",
+ pwrmcu_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_PWRMCU_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_DBI_SEL/* dts */, "dbi_sel",
+ dbi_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DBI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL/* dts */, "disp_pwm_sel",
+ disp_pwm_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DISP_PWM_SHIFT/* upd shift */),
+ /* CLK_CFG_5 */
+ MUX_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL/* dts */, "usb_sel",
+ usb_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_USB_TOP_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL/* dts */, "ssusb_xhci_sel",
+ ssusb_xhci_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SSUSB_XHCI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_I2C_SEL/* dts */, "i2c_sel",
+ i2c_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_I2C_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_TL_SEL/* dts */, "tl_sel",
+ tl_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 24/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_TL_SHIFT/* upd shift */),
+ /* CLK_CFG_6 */
+ MUX_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL/* dts */, "dpmaif_main_sel",
+ dpmaif_main_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DPMAIF_MAIN_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_PWM_SEL/* dts */, "pwm_sel",
+ pwm_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_PWM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPMI_M_MST_SEL/* dts */, "spmi_m_mst_sel",
+ spmi_m_mst_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SPMI_M_MST_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPMI_P_MST_SEL/* dts */, "spmi_p_mst_sel",
+ spmi_p_mst_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 24/* lsb */, 4/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SPMI_P_MST_SHIFT/* upd shift */),
+ /* CLK_CFG_7 */
+ MUX_CLR_SET_UPD(CLK_TOP_DVFSRC_SEL/* dts */, "dvfsrc_sel",
+ dvfsrc_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 0/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DVFSRC_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MCUPM_SEL/* dts */, "mcupm_sel",
+ mcupm_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MCUPM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SFLASH_SEL/* dts */, "sflash_sel",
+ sflash_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SFLASH_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_GCPU_SEL/* dts */, "gcpu_sel",
+ gcpu_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_GCPU_SHIFT/* upd shift */),
+ /* CLK_CFG_8 */
+ MUX_CLR_SET_UPD(CLK_TOP_SPI_SEL/* dts */, "spi_sel",
+ spi_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SPI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPIS_SEL/* dts */, "spis_sel",
+ spis_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SPIS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_ECC_SEL/* dts */, "ecc_sel",
+ ecc_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_ECC_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NFI1X_SEL/* dts */, "nfi1x_sel",
+ nfi1x_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NFI1X_SHIFT/* upd shift */),
+ /* CLK_CFG_9 */
+ MUX_CLR_SET_UPD(CLK_TOP_SPINFI_BCLK_SEL/* dts */, "spinfi_bclk_sel",
+ spinfi_bclk_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SPINFI_BCLK_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_SEL/* dts */, "netsys_sel",
+ netsys_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MEDSYS_SEL/* dts */, "medsys_sel",
+ medsys_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_MEDSYS_SHIFT/* upd shift */),
+ /* HSM isn't in kernel */
+ /* CLK_CFG_10 */
+ /* HSM isn't in kernel */
+ MUX_CLR_SET_UPD(CLK_TOP_EIP97_SEL/* dts */, "eip97_sel",
+ eip97_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_EIP97_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_312P5M_SEL/* dts */, "snps_eth_312p5m_sel",
+ snps_eth_312p5m_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_312P5M_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M_SEL/* dts */, "snps_eth_250m_sel",
+ snps_eth_250m_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 24/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_250M_SHIFT/* upd shift */),
+ /* CLK_CFG_11 */
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP_SEL/* dts */, "snps_ptp_sel",
+ snps_ptp_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 0/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII_SEL/* dts */, "snps_rmii_sel",
+ snps_rmii_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_50M_RMII_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL/* dts */, "netsys_500m_sel",
+ netsys_500m_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_500M_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_MED_MCU_SEL/* dts */, "netsys_med_mcu_sel",
+ netsys_med_mcu_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_MED_MCU_SHIFT/* upd shift */),
+ /* CLK_CFG_12 */
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_WED_MCU_SEL/* dts */, "netsys_wed_mcu_sel",
+ netsys_wed_mcu_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_WED_MCU_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL/* dts */, "netsys_2x_sel",
+ netsys_2x_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_2X_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SGMII_SEL/* dts */, "sgmii_sel",
+ sgmii_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SGMII_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SGMII_SBUS_SEL/* dts */, "sgmii_sbus_sel",
+ sgmii_sbus_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 24/* lsb */, 1/* width */,
+ INV_BIT/* pdn bit */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SGMII_SBUS_SHIFT/* upd shift */),
+#else
+ /* CLK_CFG_0 */
+ MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL/* dts */, "axi_sel",
+ axi_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AXI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPM_SEL/* dts */, "spm_sel",
+ spm_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SPM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_BUS_AXIMEM_SEL/* dts */, "bus_aximem_sel",
+ bus_aximem_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_BUS_AXIMEM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MM_SEL/* dts */, "mm_sel",
+ mm_parents/* parent */, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MM_SHIFT/* upd shift */),
+ /* CLK_CFG_1 */
+ MUX_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL/* dts */, "mfg_ref_sel",
+ mfg_ref_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MFG_REF_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MFG_SEL/* dts */, "mfg_sel",
+ mfg_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 2/* lsb */, 1/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MFG_REF_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_UART_SEL/* dts */, "uart_sel",
+ uart_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_UART_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL/* dts */, "msdc50_0_h_sel",
+ msdc50_0_h_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MSDC50_0_HCLK_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL/* dts */, "msdc50_0_sel",
+ msdc50_0_parents/* parent */, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MSDC50_0_SHIFT/* upd shift */),
+ /* CLK_CFG_2 */
+ MUX_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL/* dts */, "msdc30_1_sel",
+ msdc30_1_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MSDC30_1_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUDIO_SEL/* dts */, "audio_sel",
+ audio_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUDIO_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL/* dts */, "aud_intbus_sel",
+ aud_intbus_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_INTBUS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL/* dts */, "aud_engen1_sel",
+ aud_engen1_parents/* parent */, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR/* set parent */, 24/* lsb */, 2/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_ENGEN1_SHIFT/* upd shift */),
+ /* CLK_CFG_3 */
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL/* dts */, "aud_engen2_sel",
+ aud_engen2_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_ENGEN2_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_1_SEL/* dts */, "aud_1_sel",
+ aud_1_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_1_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_AUD_2_SEL/* dts */, "aud_2_sel",
+ aud_2_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_AUD_2_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL/* dts */, "pwrap_ulposc_sel",
+ pwrap_ulposc_parents/* parent */, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_PWRAP_ULPOSC_SHIFT/* upd shift */),
+ /* CLK_CFG_4 */
+ MUX_CLR_SET_UPD(CLK_TOP_ATB_SEL/* dts */, "atb_sel",
+ atb_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_ATB_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_PWRMCU_SEL/* dts */, "pwrmcu_sel",
+ pwrmcu_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_PWRMCU_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_DBI_SEL/* dts */, "dbi_sel",
+ dbi_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DBI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL/* dts */, "disp_pwm_sel",
+ disp_pwm_parents/* parent */, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DISP_PWM_SHIFT/* upd shift */),
+ /* CLK_CFG_5 */
+ MUX_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL/* dts */, "usb_sel",
+ usb_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 0/* lsb */, 2/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_USB_TOP_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL/* dts */, "ssusb_xhci_sel",
+ ssusb_xhci_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SSUSB_XHCI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_I2C_SEL/* dts */, "i2c_sel",
+ i2c_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_I2C_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_TL_SEL/* dts */, "tl_sel",
+ tl_parents/* parent */, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR/* set parent */, 24/* lsb */, 2/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_TL_SHIFT/* upd shift */),
+ /* CLK_CFG_6 */
+ MUX_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL/* dts */, "dpmaif_main_sel",
+ dpmaif_main_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DPMAIF_MAIN_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_PWM_SEL/* dts */, "pwm_sel",
+ pwm_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_PWM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPMI_M_MST_SEL/* dts */, "spmi_m_mst_sel",
+ spmi_m_mst_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SPMI_M_MST_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPMI_P_MST_SEL/* dts */, "spmi_p_mst_sel",
+ spmi_p_mst_parents/* parent */, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR/* set parent */, 24/* lsb */, 4/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SPMI_P_MST_SHIFT/* upd shift */),
+ /* CLK_CFG_7 */
+ MUX_CLR_SET_UPD(CLK_TOP_DVFSRC_SEL/* dts */, "dvfsrc_sel",
+ dvfsrc_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 0/* lsb */, 1/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_DVFSRC_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MCUPM_SEL/* dts */, "mcupm_sel",
+ mcupm_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 8/* lsb */, 2/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_MCUPM_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SFLASH_SEL/* dts */, "sflash_sel",
+ sflash_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE/* upd ofs */,
+ TOP_MUX_SFLASH_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_GCPU_SEL/* dts */, "gcpu_sel",
+ gcpu_parents/* parent */, CLK_CFG_7, CLK_CFG_7_SET,
+ CLK_CFG_7_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ INV_BIT/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_GCPU_SHIFT/* upd shift */),
+ /* CLK_CFG_8 */
+ MUX_CLR_SET_UPD(CLK_TOP_SPI_SEL/* dts */, "spi_sel",
+ spi_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SPI_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SPIS_SEL/* dts */, "spis_sel",
+ spis_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SPIS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_ECC_SEL/* dts */, "ecc_sel",
+ ecc_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 16/* lsb */, 2/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_ECC_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NFI1X_SEL/* dts */, "nfi1x_sel",
+ nfi1x_parents/* parent */, CLK_CFG_8, CLK_CFG_8_SET,
+ CLK_CFG_8_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NFI1X_SHIFT/* upd shift */),
+ /* CLK_CFG_9 */
+ MUX_CLR_SET_UPD(CLK_TOP_SPINFI_BCLK_SEL/* dts */, "spinfi_bclk_sel",
+ spinfi_bclk_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SPINFI_BCLK_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_SEL/* dts */, "netsys_sel",
+ netsys_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_MEDSYS_SEL/* dts */, "medsys_sel",
+ medsys_parents/* parent */, CLK_CFG_9, CLK_CFG_9_SET,
+ CLK_CFG_9_CLR/* set parent */, 16/* lsb */, 3/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_MEDSYS_SHIFT/* upd shift */),
+ /* HSM isn't in kernel. */
+ /* CLK_CFG_10 */
+ MUX_CLR_SET_UPD(CLK_TOP_EIP97_SEL/* dts */, "eip97_sel",
+ eip97_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_EIP97_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_312P5M_SEL/* dts */, "snps_eth_312p5m_sel",
+ snps_eth_312p5m_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_312P5M_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M_SEL/* dts */, "snps_eth_250m_sel",
+ snps_eth_250m_parents/* parent */, CLK_CFG_10, CLK_CFG_10_SET,
+ CLK_CFG_10_CLR/* set parent */, 24/* lsb */, 1/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_250M_SHIFT/* upd shift */),
+ /* CLK_CFG_11 */
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP_SEL/* dts */, "snps_ptp_sel",
+ snps_ptp_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 0/* lsb */, 1/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII_SEL/* dts */, "snps_rmii_sel",
+ snps_rmii_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 8/* lsb */, 1/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SNPS_ETH_50M_RMII_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL/* dts */, "netsys_500m_sel",
+ netsys_500m_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_500M_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_MED_MCU_SEL/* dts */, "netsys_med_mcu_sel",
+ netsys_med_mcu_parents/* parent */, CLK_CFG_11, CLK_CFG_11_SET,
+ CLK_CFG_11_CLR/* set parent */, 24/* lsb */, 3/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_MED_MCU_SHIFT/* upd shift */),
+ /* CLK_CFG_12 */
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_WED_MCU_SEL/* dts */, "netsys_wed_mcu_sel",
+ netsys_wed_mcu_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 0/* lsb */, 3/* width */,
+ 7/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_WED_MCU_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL/* dts */, "netsys_2x_sel",
+ netsys_2x_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 8/* lsb */, 3/* width */,
+ 15/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_NETSYS_2X_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SGMII_SEL/* dts */, "sgmii_sel",
+ sgmii_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 16/* lsb */, 1/* width */,
+ 23/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SGMII_SHIFT/* upd shift */),
+ MUX_CLR_SET_UPD(CLK_TOP_SGMII_SBUS_SEL/* dts */, "sgmii_sbus_sel",
+ sgmii_sbus_parents/* parent */, CLK_CFG_12, CLK_CFG_12_SET,
+ CLK_CFG_12_CLR/* set parent */, 24/* lsb */, 1/* width */,
+ 31/* pdn */, CLK_CFG_UPDATE1/* upd ofs */,
+ TOP_MUX_SGMII_SBUS_SHIFT/* upd shift */),
+#endif /* MT_CCF_MUX_DISABLE */
+};
+
+static const struct mtk_composite top_composites[] = {
+ /* CLK_AUDDIV_0 */
+ MUX(CLK_TOP_APLL_I2S0_MCK_SEL/* dts */, "apll_i2s0_mck_sel",
+ apll_i2s0_mck_parents/* parent */, 0x0320/* ofs */,
+ 16/* lsb */, 1/* width */),
+ MUX(CLK_TOP_APLL_I2S1_MCK_SEL/* dts */, "apll_i2s1_mck_sel",
+ apll_i2s1_mck_parents/* parent */, 0x0320/* ofs */,
+ 17/* lsb */, 1/* width */),
+ MUX(CLK_TOP_APLL_I2S2_MCK_SEL/* dts */, "apll_i2s2_mck_sel",
+ apll_i2s2_mck_parents/* parent */, 0x0320/* ofs */,
+ 18/* lsb */, 1/* width */),
+ MUX(CLK_TOP_APLL_I2S4_MCK_SEL/* dts */, "apll_i2s4_mck_sel",
+ apll_i2s4_mck_parents/* parent */, 0x0320/* ofs */,
+ 19/* lsb */, 1/* width */),
+ MUX(CLK_TOP_APLL_TDMOUT_MCK_SEL/* dts */, "apll_tdmout_mck_sel",
+ apll_tdmout_mck_parents/* parent */, 0x0320/* ofs */,
+ 20/* lsb */, 1/* width */),
+ MUX(CLK_TOP_APLL_I2S5_MCK_SEL/* dts */, "apll_i2s5_mck_sel",
+ apll_i2s5_mck_parents/* parent */, 0x0320/* ofs */,
+ 21/* lsb */, 1/* width */),
+ MUX(CLK_TOP_APLL_I2S6_MCK_SEL/* dts */, "apll_i2s6_mck_sel",
+ apll_i2s6_mck_parents/* parent */, 0x0320/* ofs */,
+ 22/* lsb */, 1/* width */),
+#if MT_CCF_MUX_DISABLE
+ /* CLK_AUDDIV_2 */
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV0/* dts */, "apll12_div0"/* ccf */,
+ "apll_i2s0_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_2/* ofs */, 0/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV1/* dts */, "apll12_div1"/* ccf */,
+ "apll_i2s1_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_2/* ofs */, 8/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV2/* dts */, "apll12_div2"/* ccf */,
+ "apll_i2s2_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_2/* ofs */, 16/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV4/* dts */, "apll12_div4"/* ccf */,
+ "apll_i2s4_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_2/* ofs */, 24/* lsb */,
+ 8/* width */),
+ /* CLK_AUDDIV_3 */
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_M/* dts */, "apll12_div_tdmout_m"/* ccf */,
+ "apll_tdmout_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_3/* ofs */, 0/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_B/* dts */, "apll12_div_tdmout_b"/* ccf */,
+ "apll_tdmout_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_3/* ofs */, 8/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV5/* dts */, "apll12_div5"/* ccf */,
+ "apll_i2s5_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_3/* ofs */, 16/* lsb */,
+ 8/* width */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV6/* dts */, "apll12_div6"/* ccf */,
+ "apll_i2s6_mck_sel"/* parent */, INV_OFS/* pdn ofs */,
+ INV_BIT/* pdn bit */, CLK_AUDDIV_3/* ofs */, 24/* lsb */,
+ 8/* width */),
+#else
+ /* CLK_AUDDIV_2 */
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV0/* dts */, "apll12_div0"/* ccf */,
+ "apll_i2s0_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 0/* pdn bit */, CLK_AUDDIV_2/* ofs */,
+ 8/* width */, 0/* lsb */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV1/* dts */, "apll12_div1"/* ccf */,
+ "apll_i2s1_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 1/* pdn bit */, CLK_AUDDIV_2/* ofs */,
+ 8/* width */, 8/* lsb */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV2/* dts */, "apll12_div2"/* ccf */,
+ "apll_i2s2_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 2/* pdn bit */, CLK_AUDDIV_2/* ofs */,
+ 8/* width */, 16/* lsb */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV4/* dts */, "apll12_div4"/* ccf */,
+ "apll_i2s4_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 3/* pdn bit */, CLK_AUDDIV_2/* ofs */,
+ 8/* width */, 24/* lsb */),
+ /* CLK_AUDDIV_3 */
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_M/* dts */, "apll12_div_tdmout_m"/* ccf */,
+ "apll_tdmout_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 4/* pdn bit */, CLK_AUDDIV_3/* ofs */,
+ 8/* width */, 0/* lsb */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_B/* dts */, "apll12_div_tdmout_b"/* ccf */,
+ "apll_tdmout_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 5/* pdn bit */, CLK_AUDDIV_3/* ofs */,
+ 8/* width */, 8/* lsb */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV5/* dts */, "apll12_div5"/* ccf */,
+ "apll_i2s5_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 6/* pdn bit */, CLK_AUDDIV_3/* ofs */,
+ 8/* width */, 16/* lsb */),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV6/* dts */, "apll12_div6"/* ccf */,
+ "apll_i2s6_mck_sel"/* parent */, 0x0320/* pdn ofs */,
+ 7/* pdn bit */, CLK_AUDDIV_3/* ofs */,
+ 8/* width */, 24/* lsb */),
+#endif /* MT_CCF_MUX_DISABLE */
+};
+
+static const struct mtk_gate_regs ifrao0_cg_regs = {
+ .set_ofs = 0x70,
+ .clr_ofs = 0x70,
+ .sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs ifrao1_cg_regs = {
+ .set_ofs = 0x74,
+ .clr_ofs = 0x74,
+ .sta_ofs = 0x74,
+};
+
+static const struct mtk_gate_regs ifrao2_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs ifrao3_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs ifrao4_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs ifrao5_cg_regs = {
+ .set_ofs = 0xc0,
+ .clr_ofs = 0xc4,
+ .sta_ofs = 0xc8,
+};
+
+static const struct mtk_gate_regs ifrao6_cg_regs = {
+ .set_ofs = 0xe0,
+ .clr_ofs = 0xe4,
+ .sta_ofs = 0xe8,
+};
+
+#define GATE_IFRAO0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_IFRAO1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_IFRAO2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFRAO3(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao3_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFRAO3_I(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao3_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_IFRAO4(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao4_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFRAO5(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao5_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFRAO6(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao6_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFRAO6_I(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifrao6_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate ifrao_clks[] = {
+ /* IFRAO0 */
+ /* IFRAO1 */
+ /* IFRAO2 */
+ GATE_IFRAO2(CLK_IFRAO_PMIC_TMR_SET, "ifrao_pmic_tmr_set",
+ "fpwrap_ulposc_ck"/* parent */, 0),
+ GATE_IFRAO2(CLK_IFRAO_PMIC_AP_SET, "ifrao_pmic_ap_set",
+ "fpwrap_ulposc_ck"/* parent */, 1),
+ GATE_IFRAO2(CLK_IFRAO_PMIC_MD_SET, "ifrao_pmic_md_set",
+ "fpwrap_ulposc_ck"/* parent */, 2),
+ GATE_IFRAO2(CLK_IFRAO_PMIC_CONN_SET, "ifrao_pmic_conn_set",
+ "fpwrap_ulposc_ck"/* parent */, 3),
+ GATE_IFRAO2(CLK_IFRAO_SEJ, "ifrao_sej",
+ "axi_ck"/* parent */, 5),
+ GATE_IFRAO2(CLK_IFRAO_MCUPM, "ifrao_mcupm",
+ "mcupm_ck"/* parent */, 7),
+ GATE_IFRAO2(CLK_IFRAO_GCE, "ifrao_gce",
+ "axi_ck"/* parent */, 8),
+ GATE_IFRAO2(CLK_IFRAO_GCE2, "ifrao_gce2",
+ "axi_ck"/* parent */, 9),
+ GATE_IFRAO2(CLK_IFRAO_THERM, "ifrao_therm",
+ "axi_ck"/* parent */, 10),
+ GATE_IFRAO2(CLK_IFRAO_I2C0, "ifrao_i2c0",
+ "i2c_ck"/* parent */, 11),
+ GATE_IFRAO2(CLK_IFRAO_I2C1, "ifrao_i2c1",
+ "i2c_ck"/* parent */, 12),
+ GATE_IFRAO2(CLK_IFRAO_I2C2, "ifrao_i2c2",
+ "i2c_ck"/* parent */, 13),
+ GATE_IFRAO2(CLK_IFRAO_I2C3, "ifrao_i2c3",
+ "i2c_ck"/* parent */, 14),
+ GATE_IFRAO2(CLK_IFRAO_PWM_HCLK, "ifrao_pwm_hclk",
+ "axi_ck"/* parent */, 15),
+ GATE_IFRAO2(CLK_IFRAO_PWM1, "ifrao_pwm1",
+ "pwm_ck"/* parent */, 16),
+ GATE_IFRAO2(CLK_IFRAO_PWM2, "ifrao_pwm2",
+ "pwm_ck"/* parent */, 17),
+ GATE_IFRAO2(CLK_IFRAO_PWM3, "ifrao_pwm3",
+ "pwm_ck"/* parent */, 18),
+ GATE_IFRAO2(CLK_IFRAO_PWM4, "ifrao_pwm4",
+ "pwm_ck"/* parent */, 19),
+ GATE_IFRAO2(CLK_IFRAO_PWM5, "ifrao_pwm5",
+ "pwm_ck"/* parent */, 20),
+ GATE_IFRAO2(CLK_IFRAO_PWM, "ifrao_pwm",
+ "pwm_ck"/* parent */, 21),
+ GATE_IFRAO2(CLK_IFRAO_UART0, "ifrao_uart0",
+ "fuart_ck"/* parent */, 22),
+ GATE_IFRAO2(CLK_IFRAO_UART1, "ifrao_uart1",
+ "fuart_ck"/* parent */, 23),
+ GATE_IFRAO2(CLK_IFRAO_UART2, "ifrao_uart2",
+ "fuart_ck"/* parent */, 24),
+ GATE_IFRAO2(CLK_IFRAO_UART3, "ifrao_uart3",
+ "fuart_ck"/* parent */, 25),
+ GATE_IFRAO2(CLK_IFRAO_GCE_26M_SET, "ifrao_gce_26m_set",
+ "axi_ck"/* parent */, 27),
+ /* IFRAO3 */
+ GATE_IFRAO3(CLK_IFRAO_SPI0, "ifrao_spi0",
+ "spi_ck"/* parent */, 1),
+ GATE_IFRAO3(CLK_IFRAO_MSDC0, "ifrao_msdc0",
+ "axi_ck"/* parent */, 2),
+ GATE_IFRAO3(CLK_IFRAO_MSDC1, "ifrao_msdc1",
+ "axi_ck"/* parent */, 4),
+ GATE_IFRAO3(CLK_IFRAO_MSDC0_SRC_CLK, "ifrao_msdc0_clk",
+ "msdc50_0_ck"/* parent */, 6),
+ GATE_IFRAO3(CLK_IFRAO_TRNG, "ifrao_trng",
+ "axi_ck"/* parent */, 9),
+ GATE_IFRAO3(CLK_IFRAO_AUXADC, "ifrao_auxadc",
+ "f26m_ck"/* parent */, 10),
+ GATE_IFRAO3(CLK_IFRAO_CPUM, "ifrao_cpum",
+ "axi_ck"/* parent */, 11),
+ GATE_IFRAO3(CLK_IFRAO_CCIF1_AP, "ifrao_ccif1_ap",
+ "axi_ck"/* parent */, 12),
+ GATE_IFRAO3(CLK_IFRAO_CCIF1_MD, "ifrao_ccif1_md",
+ "axi_ck"/* parent */, 13),
+ GATE_IFRAO3(CLK_IFRAO_AUXADC_MD, "ifrao_auxadc_md",
+ "f26m_ck"/* parent */, 14),
+ GATE_IFRAO3(CLK_IFRAO_PCIE_TL_26M, "ifrao_pcie_tl_26m",
+ "axi_ck"/* parent */, 15),
+ GATE_IFRAO3(CLK_IFRAO_MSDC1_SRC_CLK, "ifrao_msdc1_clk",
+ "msdc30_1_ck"/* parent */, 16),
+ GATE_IFRAO3(CLK_IFRAO_PCIE_TL_96M, "ifrao_pcie_tl_96m",
+ "tl_ck"/* parent */, 18),
+ GATE_IFRAO3(CLK_IFRAO_DEVICE_APC, "ifrao_dapc",
+ "axi_ck"/* parent */, 20),
+ GATE_IFRAO3(CLK_IFRAO_CCIF_AP, "ifrao_ccif_ap",
+ "axi_ck"/* parent */, 23),
+ GATE_IFRAO3(CLK_IFRAO_DEBUGSYS, "ifrao_debugsys",
+ "axi_ck"/* parent */, 24),
+ GATE_IFRAO3(CLK_IFRAO_AUDIO, "ifrao_audio",
+ "axi_ck"/* parent */, 25),
+ GATE_IFRAO3(CLK_IFRAO_CCIF_MD, "ifrao_ccif_md",
+ "axi_ck"/* parent */, 26),
+ GATE_IFRAO3(CLK_IFRAO_DEVMPU_BCLK, "ifrao_devmpu_bclk",
+ "axi_ck"/* parent */, 30),
+ /* IFRAO4 */
+ GATE_IFRAO4(CLK_IFRAO_SSUSB, "ifrao_ssusb",
+ "fusb_ck"/* parent */, 1),
+ GATE_IFRAO4(CLK_IFRAO_DISP_PWM, "ifrao_disp_pwm",
+ "axi_ck"/* parent */, 2),
+ GATE_IFRAO4(CLK_IFRAO_CLDMA_BCLK, "ifrao_cldmabclk",
+ "axi_ck"/* parent */, 3),
+ GATE_IFRAO4(CLK_IFRAO_AUDIO_26M_BCLK, "ifrao_audio26m",
+ "f26m_ck"/* parent */, 4),
+ GATE_IFRAO4(CLK_IFRAO_MODEM_TEMP_SHARE, "ifrao_mdtemp",
+ "f26m_ck"/* parent */, 5),
+ GATE_IFRAO4(CLK_IFRAO_SPI1, "ifrao_spi1",
+ "spi_ck"/* parent */, 6),
+ GATE_IFRAO4(CLK_IFRAO_I2C4, "ifrao_i2c4",
+ "i2c_ck"/* parent */, 7),
+ GATE_IFRAO4(CLK_IFRAO_SPI2, "ifrao_spi2",
+ "spi_ck"/* parent */, 9),
+ GATE_IFRAO4(CLK_IFRAO_SPI3, "ifrao_spi3",
+ "spi_ck"/* parent */, 10),
+ GATE_IFRAO4(CLK_IFRAO_UNIPRO_TICK, "ifrao_unipro_tick",
+ "f26m_ck"/* parent */, 12),
+ GATE_IFRAO4(CLK_IFRAO_UFS_MP_SAP_BCLK, "ifrao_ufs_bclk",
+ "f26m_ck"/* parent */, 13),
+ GATE_IFRAO4(CLK_IFRAO_MD32_BCLK, "ifrao_md32_bclk",
+ "axi_ck"/* parent */, 14),
+ GATE_IFRAO4(CLK_IFRAO_UNIPRO_MBIST, "ifrao_unipro_mbist",
+ "axi_ck"/* parent */, 16),
+ GATE_IFRAO4(CLK_IFRAO_PWM6, "ifrao_pwm6",
+ "i2c_ck"/* parent */, 18),
+ GATE_IFRAO4(CLK_IFRAO_PWM7, "ifrao_pwm7",
+ "i2c_ck"/* parent */, 19),
+ GATE_IFRAO4(CLK_IFRAO_I2C_SLAVE, "ifrao_i2c_slave",
+ "i2c_ck"/* parent */, 20),
+ GATE_IFRAO4(CLK_IFRAO_I2C1_ARBITER, "ifrao_i2c1a",
+ "i2c_ck"/* parent */, 21),
+ GATE_IFRAO4(CLK_IFRAO_I2C1_IMM, "ifrao_i2c1_imm",
+ "i2c_ck"/* parent */, 22),
+ GATE_IFRAO4(CLK_IFRAO_I2C2_ARBITER, "ifrao_i2c2a",
+ "i2c_ck"/* parent */, 23),
+ GATE_IFRAO4(CLK_IFRAO_I2C2_IMM, "ifrao_i2c2_imm",
+ "i2c_ck"/* parent */, 24),
+ GATE_IFRAO4(CLK_IFRAO_SSUSB_XHCI, "ifrao_ssusb_xhci",
+ "fssusb_xhci_ck"/* parent */, 31),
+ /* IFRAO5 */
+ GATE_IFRAO5(CLK_IFRAO_MSDC0_SELF, "ifrao_msdc0sf",
+ "msdc50_0_ck"/* parent */, 0),
+ GATE_IFRAO5(CLK_IFRAO_MSDC1_SELF, "ifrao_msdc1sf",
+ "msdc50_0_ck"/* parent */, 1),
+ GATE_IFRAO5(CLK_IFRAO_MSDC2_SELF, "ifrao_msdc2sf",
+ "msdc50_0_ck"/* parent */, 2),
+ GATE_IFRAO5(CLK_IFRAO_SSPM_26M_SELF, "ifrao_sspm_26m",
+ "f26m_ck"/* parent */, 3),
+ GATE_IFRAO5(CLK_IFRAO_SSPM_32K_SELF, "ifrao_sspm_32k",
+ "frtc_ck"/* parent */, 4),
+ GATE_IFRAO5(CLK_IFRAO_I2C6, "ifrao_i2c6",
+ "i2c_ck"/* parent */, 6),
+ GATE_IFRAO5(CLK_IFRAO_AP_MSDC0, "ifrao_ap_msdc0",
+ "msdc50_0_ck"/* parent */, 7),
+ GATE_IFRAO5(CLK_IFRAO_MD_MSDC0, "ifrao_md_msdc0",
+ "msdc50_0_ck"/* parent */, 8),
+ GATE_IFRAO5(CLK_IFRAO_CCIF5_AP, "ifrao_ccif5_ap",
+ "axi_ck"/* parent */, 9),
+ GATE_IFRAO5(CLK_IFRAO_CCIF5_MD, "ifrao_ccif5_md",
+ "axi_ck"/* parent */, 10),
+ GATE_IFRAO5(CLK_IFRAO_PCIE_TOP_HCLK_133M, "ifrao_pcie_h_133m",
+ "axi_ck"/* parent */, 11),
+ GATE_IFRAO5(CLK_IFRAO_SPIS_HCLK_66M, "ifrao_spis_h_66m",
+ "axi_ck"/* parent */, 14),
+ GATE_IFRAO5(CLK_IFRAO_PCIE_PERI_26M, "ifrao_pcie_peri_26m",
+ "f26m_ck"/* parent */, 15),
+ GATE_IFRAO5(CLK_IFRAO_CCIF2_AP, "ifrao_ccif2_ap",
+ "axi_ck"/* parent */, 16),
+ GATE_IFRAO5(CLK_IFRAO_CCIF2_MD, "ifrao_ccif2_md",
+ "axi_ck"/* parent */, 17),
+ GATE_IFRAO5(CLK_IFRAO_SEJ_F13M, "ifrao_sej_f13m",
+ "f26m_ck"/* parent */, 20),
+ GATE_IFRAO5(CLK_IFRAO_AES, "ifrao_aes",
+ "axi_ck"/* parent */, 21),
+ GATE_IFRAO5(CLK_IFRAO_I2C7, "ifrao_i2c7",
+ "i2c_ck"/* parent */, 22),
+ GATE_IFRAO5(CLK_IFRAO_I2C8, "ifrao_i2c8",
+ "i2c_ck"/* parent */, 23),
+ GATE_IFRAO5(CLK_IFRAO_FBIST2FPC, "ifrao_fbist2fpc",
+ "msdc50_0_ck"/* parent */, 24),
+ GATE_IFRAO5(CLK_IFRAO_DPMAIF_MAIN, "ifrao_dpmaif_main",
+ "dpmaif_main_ck"/* parent */, 26),
+ GATE_IFRAO5(CLK_IFRAO_PCIE_TL_32K, "ifrao_pcie_tl_32k",
+ "frtc_ck"/* parent */, 27),
+ GATE_IFRAO5(CLK_IFRAO_CCIF4_AP, "ifrao_ccif4_ap",
+ "axi_ck"/* parent */, 28),
+ GATE_IFRAO5(CLK_IFRAO_CCIF4_MD, "ifrao_ccif4_md",
+ "axi_ck"/* parent */, 29),
+ /* IFRAO6 */
+ GATE_IFRAO6(CLK_IFRAO_133M_MCLK_CK, "ifrao_133m_mclk_ck",
+ "axi_ck"/* parent */, 0),
+ GATE_IFRAO6(CLK_IFRAO_66M_MCLK_CK, "ifrao_66m_mclk_ck",
+ "axi_ck"/* parent */, 1),
+ GATE_IFRAO6(CLK_IFRAO_66M_PERI_BUS_MCLK_CK, "ifrao_66m_peri_mclk",
+ "axi_ck"/* parent */, 2),
+ GATE_IFRAO6(CLK_IFRAO_INFRA_FREE_DCM_133M, "ifrao_infra_133m",
+ "axi_ck"/* parent */, 3),
+ GATE_IFRAO6(CLK_IFRAO_INFRA_FREE_DCM_66M, "ifrao_infra_66m",
+ "axi_ck"/* parent */, 4),
+ GATE_IFRAO6(CLK_IFRAO_PERU_BUS_DCM_133M, "ifrao_peru_bus_133m",
+ "axi_ck"/* parent */, 5),
+ GATE_IFRAO6(CLK_IFRAO_PERU_BUS_DCM_66M, "ifrao_peru_bus_66m",
+ "axi_ck"/* parent */, 6),
+ GATE_IFRAO6(CLK_IFRAO_RG_133M_CLDMA_TOP, "ifrao_133m_cldma_top",
+ "axi_ck"/* parent */, 7),
+ GATE_IFRAO6(CLK_IFRAO_RG_ECC_TOP, "ifrao_ecc_top",
+ "axi_ck"/* parent */, 8),
+ GATE_IFRAO6(CLK_IFRAO_RG_133M_DWC_ETHER, "ifrao_133m_dwc_ether",
+ "axi_ck"/* parent */, 11),
+ GATE_IFRAO6(CLK_IFRAO_RG_133M_FLASHIF, "ifrao_133m_flashif",
+ "axi_ck"/* parent */, 12),
+ GATE_IFRAO6(CLK_IFRAO_RG_133M_PCIE_P0, "ifrao_133m_pcie_p0",
+ "axi_ck"/* parent */, 13),
+ GATE_IFRAO6_I(CLK_IFRAO_RG_133M_PCIE_P1, "ifrao_133m_pcie_p1",
+ "axi_ck"/* parent */, 14),
+ GATE_IFRAO6_I(CLK_IFRAO_RG_133M_PCIE_P2, "ifrao_133m_pcie_p2",
+ "axi_ck"/* parent */, 15),
+ GATE_IFRAO6_I(CLK_IFRAO_RG_133M_PCIE_P3, "ifrao_133m_pcie_p3",
+ "axi_ck"/* parent */, 16),
+ GATE_IFRAO6(CLK_IFRAO_RG_MMW_DPMAIF_TOP_CK, "ifrao_mmw_dpmaif_ck",
+ "axi_ck"/* parent */, 17),
+ GATE_IFRAO6(CLK_IFRAO_RG_NFI, "ifrao_nfi",
+ "nfi1x_ck"/* parent */, 18),
+ GATE_IFRAO6(CLK_IFRAO_RG_FPINFI_BCLK_CK, "ifrao_fpinfi_bclk_ck",
+ "spinfi_bclk_ck"/* parent */, 19),
+ GATE_IFRAO6(CLK_IFRAO_RG_66M_NFI_HCLK_CK, "ifrao_66m_nfi_h_ck",
+ "axi_ck"/* parent */, 20),
+ GATE_IFRAO6(CLK_IFRAO_RG_FSPIS_CK, "ifrao_fspis_ck",
+ "spis_ck"/* parent */, 21),
+ GATE_IFRAO6(CLK_IFRAO_RG_PCIE_PERI_26M_P1, "ifrao_26m_p1",
+ "axi_ck"/* parent */, 25),
+ GATE_IFRAO6(CLK_IFRAO_RG_PCIE_PERI_26M_P2, "ifrao_26m_p2",
+ "axi_ck"/* parent */, 26),
+ GATE_IFRAO6(CLK_IFRAO_RG_PCIE_PERI_26M_P3, "ifrao_26m_p3",
+ "axi_ck"/* parent */, 27),
+ GATE_IFRAO6(CLK_IFRAO_RG_FLASHIF_PERI_26M, "ifrao_flash_26m",
+ "axi_ck"/* parent */, 30),
+ GATE_IFRAO6(CLK_IFRAO_RG_FLASHIF_SFLASH, "ifrao_sflash_ck",
+ "axi_ck"/* parent */, 31),
+};
+
+
+
+static const struct mtk_gate_regs peri_cg_regs = {
+ .set_ofs = 0x20c,
+ .clr_ofs = 0x20c,
+ .sta_ofs = 0x20c,
+};
+
+#define GATE_PERI(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate peri_clks[] = {
+};
+
+static const struct mtk_gate_regs apmixed_cg_regs = {
+ .set_ofs = 0x14,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x14,
+};
+#define GATE_APMIXED(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &apmixed_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate apmixed_clks[] = {
+};
+
+#define MT6890_PLL_FMAX (3800UL * MHZ)
+#define MT6890_PLL_FMIN (1500UL * MHZ)
+#define MT6890_INTEGER_BITS 8
+
+#if MT_CCF_PLL_DISABLE
+#define PLL_CFLAGS PLL_AO
+#else
+#define PLL_CFLAGS (0)
+#endif
+
+#define PLL_B(_id, _name, _reg, _en_reg, _en_mask, _pwr_reg, \
+ _iso_mask, _pwron_mask, _flags, _rst_bar_reg, \
+ _rst_bar_mask, _pd_reg, _pd_shift, _tuner_reg, \
+ _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
+ _pcw_shift, _pcwbits, _div_table) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .en_reg = _en_reg, \
+ .en_mask = _en_mask, \
+ .pwr_reg = _pwr_reg, \
+ .iso_mask = _iso_mask, \
+ .pwron_mask = _pwron_mask, \
+ .flags = (_flags | PLL_CFLAGS), \
+ .rst_bar_reg = _rst_bar_reg, \
+ .rst_bar_mask = _rst_bar_mask, \
+ .fmax = MT6890_PLL_FMAX, \
+ .fmin = MT6890_PLL_FMIN, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .tuner_en_reg = _tuner_en_reg, \
+ .tuner_en_bit = _tuner_en_bit, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcw_chg_reg = _reg + 0x8, /* always CON2 */ \
+ .pcwbits = _pcwbits, \
+ .pcwibits = MT6890_INTEGER_BITS, \
+ .div_table = _div_table, \
+ }
+
+#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pwr_reg, \
+ _iso_mask, _pwron_mask, _flags, _rst_bar_reg, \
+ _rst_bar_mask, _pd_reg, _pd_shift, _tuner_reg, \
+ _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
+ _pcw_shift, _pcwbits) \
+ PLL_B(_id, _name, _reg, _en_reg, _en_mask, _pwr_reg, \
+ _iso_mask, _pwron_mask, _flags, _rst_bar_reg, \
+ _rst_bar_mask, _pd_reg, _pd_shift, _tuner_reg, \
+ _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
+ _pcw_shift, _pcwbits, NULL) \
+
+static const struct mtk_pll_data plls[] = {
+ PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", ARMPLL_LL_CON0/*base*/,
+ ARMPLL_LL_CON0, 0x0200/*en*/,
+ ARMPLL_LL_CON4, 0x0002, 0x0001/*pwr*/,
+ PLL_AO, 0, BIT(0)/*rstb*/,
+ 0x020C, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ ARMPLL_LL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_CCIPLL, "ccipll", CCIPLL_CON0/*base*/,
+ CCIPLL_CON0, 0x0200/*en*/,
+ CCIPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ PLL_AO, 0, BIT(0)/*rstb*/,
+ 0x0220, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ CCIPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_MPLL, "mpll", MPLL_CON0/*base*/,
+ MPLL_CON0, 0x0200/*en*/,
+ MPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ PLL_AO, 0, BIT(0)/*rstb*/,
+ 0x060C, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ MPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0/*base*/,
+ MAINPLL_CON0, 0x0200/*en*/,
+ MAINPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ HAVE_RST_BAR|PLL_AO, 0x0404, BIT(23)/*rstb*/,
+ 0x040C, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ MAINPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0/*base*/,
+ UNIVPLL_CON0, 0x0200/*en*/,
+ UNIVPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ HAVE_RST_BAR, 0x0418, BIT(23)/*rstb*/,
+ 0x0420, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ UNIVPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0/*base*/,
+ MSDCPLL_CON0, 0x0200/*en*/,
+ MSDCPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x234, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ MSDCPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_MMPLL, "mmpll", MMPLL_CON0/*base*/,
+ MMPLL_CON0, 0x0200/*en*/,
+ MMPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ HAVE_RST_BAR, 0x042C, BIT(23)/*rstb*/,
+ 0x0434, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ MMPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_MFGPLL, "mfgpll", MFGPLL_CON0/*base*/,
+ MFGPLL_CON0, 0x0200/*en*/,
+ MFGPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x0620, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ MFGPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_APLL1, "apll1", APLL1_CON0/*base*/,
+ APLL1_CON0, 0x0200/*en*/,
+ APLL1_CON5, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x045C, 24/*pd*/,
+ APLL1_TUNER_CON0, AP_PLL_CON0, 12/*tuner*/,
+ APLL1_CON3, 0, 32/*pcw*/),
+ PLL(CLK_APMIXED_APLL2, "apll2", APLL2_CON0/*base*/,
+ APLL2_CON0, 0x0200/*en*/,
+ APLL2_CON5, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x0474, 24/*pd*/,
+ APLL2_TUNER_CON0, AP_PLL_CON0, 13/*tuner*/,
+ APLL2_CON3, 0, 32/*pcw*/),
+ PLL(CLK_APMIXED_NET1PLL, "net1pll", NET1PLL_CON0/*base*/,
+ NET1PLL_CON0, 0x0200/*en*/,
+ NET1PLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x080C, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ NET1PLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_NET2PLL, "net2pll", NET2PLL_CON0/*base*/,
+ NET2PLL_CON0, 0x0200/*en*/,
+ NET2PLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x0820, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ NET2PLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", WEDMCUPLL_CON0/*base*/,
+ WEDMCUPLL_CON0, 0x0200/*en*/,
+ WEDMCUPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x0834, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ WEDMCUPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_MEDMCUPLL, "medmcupll", MEDMCUPLL_CON0/*base*/,
+ MEDMCUPLL_CON0, 0x0200/*en*/,
+ MEDMCUPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x0848, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ MEDMCUPLL_CON2, 0, 22/*pcw*/),
+ PLL(CLK_APMIXED_SGMIIPLL, "sgmiipll", SGMIIPLL_CON0/*base*/,
+ SGMIIPLL_CON0, 0x0200/*en*/,
+ SGMIIPLL_CON4, 0x0002, 0x0001/*pwr*/,
+ 0, 0, BIT(0)/*rstb*/,
+ 0x0248, 24/*pd*/,
+ 0, 0, 0/*tuner*/,
+ SGMIIPLL_CON2, 0, 22/*pcw*/),
+};
+
+static int clk_mt6890_apmixed_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ void __iomem *base;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base)) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return PTR_ERR(base);
+ }
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+ clk_data);
+
+ mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ apmixed_base = base;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static int clk_mt6890_ifrao_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_IFRAO_NR_CLK);
+
+ mtk_clk_register_gates(node, ifrao_clks, ARRAY_SIZE(ifrao_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static int clk_mt6890_peri_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+ mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+static struct clk_onecell_data *mt6890_top_clk_data;
+
+static int clk_mt6890_top_probe(struct platform_device *pdev)
+{
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ void __iomem *base;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+#if MT_CCF_BRINGUP
+ pr_notice("%s init begin\n", __func__);
+#endif
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base)) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return PTR_ERR(base);
+ }
+
+ mt6890_top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
+ mt6890_top_clk_data);
+
+ mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
+ &mt6890_clk_lock, mt6890_top_clk_data);
+
+ mtk_clk_register_composites(top_composites, ARRAY_SIZE(top_composites),
+ base, &mt6890_clk_lock, mt6890_top_clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get,
+ mt6890_top_clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+/*
+ mtk_clk_check_muxes(top_muxes, ARRAY_SIZE(top_muxes),
+ mt6890_top_clk_data);
+*/
+#if MT_CCF_BRINGUP
+ pr_notice("%s init end\n", __func__);
+#endif
+
+ return r;
+}
+
+/* for suspend LDVT only */
+void pll_force_off(void)
+{
+ void __iomem *rst_reg, *en_reg, *pwr_reg;
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(plls); i++) {
+ /* do not pwrdn the AO PLLs */
+ if ((plls[i].flags & PLL_AO) == PLL_AO)
+ continue;
+
+ if ((plls[i].flags & HAVE_RST_BAR) == HAVE_RST_BAR) {
+ rst_reg = apmixed_base + plls[i].rst_bar_reg;
+ writel(readl(rst_reg) & ~plls[i].rst_bar_mask,
+ rst_reg);
+ }
+
+ en_reg = apmixed_base + plls[i].en_reg;
+
+ pwr_reg = apmixed_base + plls[i].pwr_reg;
+
+ writel(readl(en_reg) & ~plls[i].en_mask,
+ en_reg);
+ writel(readl(pwr_reg) | plls[i].iso_mask,
+ pwr_reg);
+ writel(readl(pwr_reg) & ~plls[i].pwron_mask,
+ pwr_reg);
+ }
+}
+
+static struct generic_pm_domain **get_all_genpd(void)
+{
+ static struct generic_pm_domain *pds[31];
+ static int num_pds;
+ const size_t maxpd = ARRAY_SIZE(pds);
+ struct device_node *node;
+ struct platform_device *pdev;
+ int r;
+ if (num_pds != 0)
+ goto out;
+ node = of_find_node_with_property(NULL, "#power-domain-cells");
+ if (node == NULL)
+ return NULL;
+ pdev = platform_device_alloc("traverse", 0);
+ for (num_pds = 0; num_pds < maxpd; num_pds++) {
+ struct of_phandle_args pa;
+ pa.np = node;
+ pa.args[0] = num_pds;
+ pa.args_count = 1;
+ r = of_genpd_add_device(&pa, &pdev->dev);
+ if (r == -EINVAL)
+ continue;
+ else if (r != 0)
+ pr_warn("%s(): of_genpd_add_device(%d)\n", __func__, r);
+ pds[num_pds] = pd_to_genpd(pdev->dev.pm_domain);
+ //r = pm_genpd_remove_device(pds[num_pds], &pdev->dev);
+ r = pm_genpd_remove_device(&pdev->dev);
+ if (r != 0)
+ pr_warn("%s(): pm_genpd_remove_device(%d)\n",
+ __func__, r);
+ if (IS_ERR(pds[num_pds])) {
+ pds[num_pds] = NULL;
+ break;
+ }
+ }
+ platform_device_put(pdev);
+out:
+ return pds;
+}
+
+void subsys_force_off(void)
+{
+ struct generic_pm_domain *genpd;
+ int (*gpd_op)(struct generic_pm_domain *);
+ int r = 0;
+ struct generic_pm_domain **pds = get_all_genpd();
+ for (; *pds != NULL; pds++) {
+ genpd = *pds;
+ if (IS_ERR_OR_NULL(genpd))
+ continue;
+ if((genpd->flags & GENPD_FLAG_ALWAYS_ON)|(genpd->status == GPD_STATE_POWER_OFF))
+ continue;
+ gpd_op = genpd->power_off;
+ r |= gpd_op(genpd);
+ }
+}
+
+void pll_if_on(void)
+{
+ void __iomem *en_reg;
+ u32 i;
+ for (i = 0; i < ARRAY_SIZE(plls); i++) {
+
+ en_reg = apmixed_base + plls[i].en_reg;
+
+ if (readl(en_reg) & plls[i].en_mask)
+ pr_notice("suspend warning : %s is on !!!\n",plls[i].name);
+
+ }
+}
+
+void subsys_if_on(void)
+{
+ static const char * const pwr_names[] = {
+ [0] = "MD1",
+ [1] = "CONN",
+ [2] = "MFG0",
+ [3] = "PEXTP_D_2LX1_PHY",
+ [4] = "PEXTP_R_2LX1_PHY",
+ [5] = "PEXTP_R_1LX2_0P_PHY",
+ [6] = "PEXTP_R_1LX2_1P_PHY",
+ [7] = "SSUSB_PHY",
+ [8] = "SGMII_0_PHY",
+ [9] = "IFR",
+ [10] = "SGMII_1_PHY",
+ [11] = "DPY",
+ [12] = "PEXTP_D_2LX1",
+ [13] = "PEXTP_R_2LX1",
+ [14] = "PEXTP_R_1LX2",
+ [15] = "ETH",
+ [16] = "SSUSB",
+ [17] = "SGMII_0_TOP",
+ [18] = "SGMII_1_TOP",
+ [19] = "NETSYS",
+ [20] = "DIS",
+ [21] = "AUDIO",
+ [22] = "EIP97",
+ [23] = "HSMTOP",
+ [24] = "DRAMC_MD32",
+ [25] = "(Reserved)",
+ [26] = "(Reserved)",
+ [27] = "(Reserved)",
+ [28] = "DPY2",
+ [29] = "MCUPM",
+ [30] = "MSDC",
+ [31] = "PERI",
+ };
+ u32 val = 0,i;
+ static void __iomem *scpsys_base, *pwr_sta, *pwr_sta_2nd;
+
+ scpsys_base = ioremap(0x10006000, PAGE_SIZE);
+ pwr_sta = scpsys_base + 0x16c;
+ pwr_sta_2nd = scpsys_base + 0x170;
+ val = readl(pwr_sta) & readl(pwr_sta_2nd);
+
+ for (i = 0; i < 32; i++) {
+ if((val & BIT(i)) != 0U)
+ pr_notice("suspend warning: %s is on!!\n",pwr_names[i]);
+ }
+}
+
+static int pll_status_cmd(struct seq_file *s, void *v)
+{
+ seq_printf(s, "Call pll_if_on \n");
+ pll_if_on();
+ return 0;
+}
+
+static int mtcmos_status_cmd(struct seq_file *s, void *v)
+{
+ seq_printf(s, "Call subsys_if_on \n");
+ subsys_if_on();
+ return 0;
+}
+
+static int pll_off_cmd(struct seq_file *s, void *v)
+{
+ seq_printf(s, "Call pll_force_off \n");
+ pll_force_off();
+ return 0;
+}
+
+static int mtcmos_off_cmd(struct seq_file *s, void *v)
+{
+ seq_printf(s, "Call subsys_force_off \n");
+ subsys_force_off();
+ return 0;
+}
+
+static int all_off_cmd(struct seq_file *s, void *v)
+{
+ seq_printf(s, "Call pll/mtcmos off and status \n");
+ pll_force_off();
+ subsys_force_off();
+ pll_if_on();
+ subsys_if_on();
+ return 0;
+}
+
+static const struct cmd_fn cmds[] = {
+ CMDFN("pll_status", pll_status_cmd),
+ CMDFN("mtcmos_status", mtcmos_status_cmd),
+ CMDFN("pll_off", pll_off_cmd),
+ CMDFN("mtcmos_off", mtcmos_off_cmd),
+ CMDFN("all_off", all_off_cmd),
+ {}
+};
+
+static const struct of_device_id of_match_clk_mt6890[] = {
+ {
+ .compatible = "mediatek,mt6890-apmixedsys",
+ .data = clk_mt6890_apmixed_probe,
+ }, {
+ .compatible = "mediatek,mt6890-infracfg_ao",
+ .data = clk_mt6890_ifrao_probe,
+ }, {
+ .compatible = "mediatek,mt6890-pericfg",
+ .data = clk_mt6890_peri_probe,
+ }, {
+ .compatible = "mediatek,mt6890-topckgen",
+ .data = clk_mt6890_top_probe,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt6890_probe(struct platform_device *pdev)
+{
+ int (*clk_probe)(struct platform_device *pd);
+ int r;
+
+ clk_probe = of_device_get_match_data(&pdev->dev);
+ if (!clk_probe)
+ return -EINVAL;
+
+ r = clk_probe(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ set_custom_cmds(cmds);
+ return r;
+}
+
+static struct platform_driver clk_mt6890_drv = {
+ .probe = clk_mt6890_probe,
+ .driver = {
+ .name = "clk-mt6890",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_clk_mt6890,
+ },
+};
+
+static int __init clk_mt6890_init(void)
+{
+ return platform_driver_register(&clk_mt6890_drv);
+}
+
+arch_initcall_sync(clk_mt6890_init);
+
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7622-aud.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7622-aud.c
new file mode 100644
index 0000000..4f3d47b
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7622-aud.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ * Sean Wang <sean.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt7622-clk.h>
+
+#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audio0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audio1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_AUDIO2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audio2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_AUDIO3(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &audio3_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+static const struct mtk_gate_regs audio0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs audio1_cg_regs = {
+ .set_ofs = 0x10,
+ .clr_ofs = 0x10,
+ .sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs audio2_cg_regs = {
+ .set_ofs = 0x14,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x14,
+};
+
+static const struct mtk_gate_regs audio3_cg_regs = {
+ .set_ofs = 0x634,
+ .clr_ofs = 0x634,
+ .sta_ofs = 0x634,
+};
+
+static const struct mtk_gate audio_clks[] = {
+ /* AUDIO0 */
+ GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
+ GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
+ GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
+ GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
+ /* AUDIO1 */
+ GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
+ GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
+ GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
+ GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
+ GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
+ GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
+ GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
+ GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
+ GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
+ GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
+ GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
+ GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
+ GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
+ GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
+ GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
+ GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23),
+ /* AUDIO2 */
+ GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
+ GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
+ GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
+ GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
+ GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
+ GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
+ GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
+ GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
+ GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
+ GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
+ GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
+ GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
+ GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
+ GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
+ GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
+ GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
+ GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
+ GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
+ /* AUDIO3 */
+ GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
+ GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
+ GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
+ GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
+ GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
+ GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
+ GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
+ GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
+ GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
+};
+
+static int clk_mt7622_audiosys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
+
+ mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r) {
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ goto err_clk_provider;
+ }
+
+ r = devm_of_platform_populate(&pdev->dev);
+ if (r)
+ goto err_plat_populate;
+
+ return 0;
+
+err_plat_populate:
+ of_clk_del_provider(node);
+err_clk_provider:
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt7622_aud[] = {
+ {
+ .compatible = "mediatek,mt7622-audsys",
+ .data = clk_mt7622_audiosys_init,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt7622_aud_probe(struct platform_device *pdev)
+{
+ int (*clk_init)(struct platform_device *);
+ int r;
+
+ clk_init = of_device_get_match_data(&pdev->dev);
+ if (!clk_init)
+ return -EINVAL;
+
+ r = clk_init(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt7622_aud_drv = {
+ .probe = clk_mt7622_aud_probe,
+ .driver = {
+ .name = "clk-mt7622-aud",
+ .of_match_table = of_match_clk_mt7622_aud,
+ },
+};
+
+builtin_platform_driver(clk_mt7622_aud_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7622-eth.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7622-eth.c
new file mode 100644
index 0000000..6328127
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ * Sean Wang <sean.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt7622-clk.h>
+
+#define GATE_ETH(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = ð_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate_regs eth_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+static const struct mtk_gate eth_clks[] = {
+ GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
+ GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
+ GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
+};
+
+static const struct mtk_gate_regs sgmii_cg_regs = {
+ .set_ofs = 0xE4,
+ .clr_ofs = 0xE4,
+ .sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &sgmii_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate sgmii_clks[] = {
+ GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
+ "ssusb_tx250m", 2),
+ GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
+ "ssusb_eq_rx250m", 3),
+ GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
+ "ssusb_cdr_ref", 4),
+ GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
+ "ssusb_cdr_fb", 5),
+};
+
+static int clk_mt7622_ethsys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
+
+ mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ mtk_register_reset_controller(node, 1, 0x34);
+
+ return r;
+}
+
+static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
+
+ mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt7622_eth[] = {
+ {
+ .compatible = "mediatek,mt7622-ethsys",
+ .data = clk_mt7622_ethsys_init,
+ }, {
+ .compatible = "mediatek,mt7622-sgmiisys",
+ .data = clk_mt7622_sgmiisys_init,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt7622_eth_probe(struct platform_device *pdev)
+{
+ int (*clk_init)(struct platform_device *);
+ int r;
+
+ clk_init = of_device_get_match_data(&pdev->dev);
+ if (!clk_init)
+ return -EINVAL;
+
+ r = clk_init(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt7622_eth_drv = {
+ .probe = clk_mt7622_eth_probe,
+ .driver = {
+ .name = "clk-mt7622-eth",
+ .of_match_table = of_match_clk_mt7622_eth,
+ },
+};
+
+builtin_platform_driver(clk_mt7622_eth_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7622-hif.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7622-hif.c
new file mode 100644
index 0000000..a6e8534
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ * Sean Wang <sean.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt7622-clk.h>
+
+#define GATE_PCIE(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &pcie_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_SSUSB(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ssusb_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate_regs pcie_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+static const struct mtk_gate_regs ssusb_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+static const struct mtk_gate ssusb_clks[] = {
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
+ "to_u2_phy_1p", 0),
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
+ GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
+ GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
+ GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7),
+ GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8),
+};
+
+static const struct mtk_gate pcie_clks[] = {
+ GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
+ GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
+ GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14),
+ GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15),
+ GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
+ GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
+ GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
+ GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
+ GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20),
+ GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21),
+ GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
+ GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
+ GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26),
+ GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27),
+ GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28),
+ GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29),
+ GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
+};
+
+static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+
+ mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ mtk_register_reset_controller(node, 1, 0x34);
+
+ return r;
+}
+
+static int clk_mt7622_pciesys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+
+ mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ mtk_register_reset_controller(node, 1, 0x34);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt7622_hif[] = {
+ {
+ .compatible = "mediatek,mt7622-pciesys",
+ .data = clk_mt7622_pciesys_init,
+ }, {
+ .compatible = "mediatek,mt7622-ssusbsys",
+ .data = clk_mt7622_ssusbsys_init,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt7622_hif_probe(struct platform_device *pdev)
+{
+ int (*clk_init)(struct platform_device *);
+ int r;
+
+ clk_init = of_device_get_match_data(&pdev->dev);
+ if (!clk_init)
+ return -EINVAL;
+
+ r = clk_init(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt7622_hif_drv = {
+ .probe = clk_mt7622_hif_probe,
+ .driver = {
+ .name = "clk-mt7622-hif",
+ .of_match_table = of_match_clk_mt7622_hif,
+ },
+};
+
+builtin_platform_driver(clk_mt7622_hif_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7622.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7622.c
new file mode 100644
index 0000000..a8aecef
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7622.c
@@ -0,0 +1,780 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ * Sean Wang <sean.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+#include "clk-cpumux.h"
+
+#include <dt-bindings/clock/mt7622-clk.h>
+#include <linux/clk.h> /* for consumer */
+
+#define MT7622_PLL_FMAX (2500UL * MHZ)
+#define CON0_MT7622_RST_BAR BIT(27)
+
+#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
+ _pcw_shift, _div_table, _parent_name) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .flags = _flags, \
+ .rst_bar_mask = CON0_MT7622_RST_BAR, \
+ .fmax = MT7622_PLL_FMAX, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .div_table = _div_table, \
+ .parent_name = _parent_name, \
+ }
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
+ _pcw_shift) \
+ PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
+ NULL, "clkxtal")
+
+#define GATE_APMIXED(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &apmixed_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_INFRA(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_TOP0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_TOP1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_PERI0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_PERI1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static DEFINE_SPINLOCK(mt7622_clk_lock);
+
+static const char * const infra_mux1_parents[] = {
+ "clkxtal",
+ "armpll",
+ "main_core_en",
+ "armpll"
+};
+
+static const char * const axi_parents[] = {
+ "clkxtal",
+ "syspll1_d2",
+ "syspll_d5",
+ "syspll1_d4",
+ "univpll_d5",
+ "univpll2_d2",
+ "univpll_d7"
+};
+
+static const char * const mem_parents[] = {
+ "clkxtal",
+ "dmpll_ck"
+};
+
+static const char * const ddrphycfg_parents[] = {
+ "clkxtal",
+ "syspll1_d8"
+};
+
+static const char * const eth_parents[] = {
+ "clkxtal",
+ "syspll1_d2",
+ "univpll1_d2",
+ "syspll1_d4",
+ "univpll_d5",
+ "clk_null",
+ "univpll_d7"
+};
+
+static const char * const pwm_parents[] = {
+ "clkxtal",
+ "univpll2_d4"
+};
+
+static const char * const f10m_ref_parents[] = {
+ "clkxtal",
+ "syspll4_d16"
+};
+
+static const char * const nfi_infra_parents[] = {
+ "clkxtal",
+ "clkxtal",
+ "clkxtal",
+ "clkxtal",
+ "clkxtal",
+ "clkxtal",
+ "clkxtal",
+ "clkxtal",
+ "univpll2_d8",
+ "syspll1_d8",
+ "univpll1_d8",
+ "syspll4_d2",
+ "univpll2_d4",
+ "univpll3_d2",
+ "syspll1_d4"
+};
+
+static const char * const flash_parents[] = {
+ "clkxtal",
+ "univpll_d80_d4",
+ "syspll2_d8",
+ "syspll3_d4",
+ "univpll3_d4",
+ "univpll1_d8",
+ "syspll2_d4",
+ "univpll2_d4"
+};
+
+static const char * const uart_parents[] = {
+ "clkxtal",
+ "univpll2_d8"
+};
+
+static const char * const spi0_parents[] = {
+ "clkxtal",
+ "syspll3_d2",
+ "clkxtal",
+ "syspll2_d4",
+ "syspll4_d2",
+ "univpll2_d4",
+ "univpll1_d8",
+ "clkxtal"
+};
+
+static const char * const spi1_parents[] = {
+ "clkxtal",
+ "syspll3_d2",
+ "clkxtal",
+ "syspll4_d4",
+ "syspll4_d2",
+ "univpll2_d4",
+ "univpll1_d8",
+ "clkxtal"
+};
+
+static const char * const msdc30_0_parents[] = {
+ "clkxtal",
+ "univpll2_d16",
+ "univ48m"
+};
+
+static const char * const a1sys_hp_parents[] = {
+ "clkxtal",
+ "aud1pll_ck",
+ "aud2pll_ck",
+ "clkxtal"
+};
+
+static const char * const intdir_parents[] = {
+ "clkxtal",
+ "syspll_d2",
+ "univpll_d2",
+ "sgmiipll_ck"
+};
+
+static const char * const aud_intbus_parents[] = {
+ "clkxtal",
+ "syspll1_d4",
+ "syspll4_d2",
+ "syspll3_d2"
+};
+
+static const char * const pmicspi_parents[] = {
+ "clkxtal",
+ "clk_null",
+ "clk_null",
+ "clk_null",
+ "clk_null",
+ "univpll2_d16"
+};
+
+static const char * const atb_parents[] = {
+ "clkxtal",
+ "syspll1_d2",
+ "syspll_d5"
+};
+
+static const char * const audio_parents[] = {
+ "clkxtal",
+ "syspll3_d4",
+ "syspll4_d4",
+ "univpll1_d16"
+};
+
+static const char * const usb20_parents[] = {
+ "clkxtal",
+ "univpll3_d4",
+ "syspll1_d8",
+ "clkxtal"
+};
+
+static const char * const aud1_parents[] = {
+ "clkxtal",
+ "aud1pll_ck"
+};
+
+static const char * const aud2_parents[] = {
+ "clkxtal",
+ "aud2pll_ck"
+};
+
+static const char * const asm_l_parents[] = {
+ "clkxtal",
+ "syspll_d5",
+ "univpll2_d2",
+ "univpll2_d4"
+};
+
+static const char * const apll1_ck_parents[] = {
+ "aud1_sel",
+ "aud2_sel"
+};
+
+static const char * const peribus_ck_parents[] = {
+ "syspll1_d8",
+ "syspll1_d4"
+};
+
+static const struct mtk_gate_regs apmixed_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x8,
+};
+
+static const struct mtk_gate_regs infra_cg_regs = {
+ .set_ofs = 0x40,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x48,
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x120,
+ .clr_ofs = 0x120,
+ .sta_ofs = 0x120,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x128,
+ .clr_ofs = 0x128,
+ .sta_ofs = 0x128,
+};
+
+static const struct mtk_gate_regs peri0_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x10,
+ .sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs peri1_cg_regs = {
+ .set_ofs = 0xC,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x1C,
+};
+
+static const struct mtk_pll_data plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
+ PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
+ HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
+ PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
+ HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
+ PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
+ 0, 21, 0x0300, 1, 0, 0x0304, 0),
+ PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
+ 0, 21, 0x0314, 1, 0, 0x0318, 0),
+ PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
+ 0, 31, 0x0324, 1, 0, 0x0328, 0),
+ PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
+ 0, 31, 0x0334, 1, 0, 0x0338, 0),
+ PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
+ 0, 21, 0x0344, 1, 0, 0x0348, 0),
+ PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
+ 0, 21, 0x0358, 1, 0, 0x035C, 0),
+};
+
+static const struct mtk_gate apmixed_clks[] = {
+ GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
+};
+
+static const struct mtk_gate infra_clks[] = {
+ GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
+ GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
+ GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
+ GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
+ GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
+ GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
+};
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
+ 31250000),
+ FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
+ 31250000),
+ FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
+ 125000000),
+ FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
+ 125000000),
+ FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
+ 250000000),
+ FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
+ 250000000),
+ FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
+ 33333333),
+ FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
+ 50000000),
+ FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
+ 50000000),
+ FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
+ 50000000),
+};
+
+static const struct mtk_fixed_factor top_divs[] = {
+ FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
+ FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
+ FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
+ FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
+ FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
+ FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
+ FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
+ FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
+ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
+ FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
+ FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
+ FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
+ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
+ FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
+ FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
+ FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
+ FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
+ FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
+ FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
+ FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
+ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
+ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
+ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
+ FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
+ FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
+ FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
+ FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
+ FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
+ FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
+ FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
+ FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
+ FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
+ FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
+ FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
+ FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
+ FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
+ FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
+ FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
+};
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
+ GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
+ GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
+ 2),
+ GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
+ 3),
+ GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
+ 4),
+ GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
+ 5),
+
+ /* TOP1 */
+ GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
+ GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
+};
+
+static const struct mtk_clk_divider top_adj_divs[] = {
+ DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
+ 0x120, 24, 3),
+ DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
+ 0x120, 28, 3),
+ DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
+ 0x124, 0, 7),
+ DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
+ 0x124, 8, 7),
+ DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
+ 0x124, 16, 7),
+ DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
+ 0x124, 24, 7),
+ DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
+ 0x128, 8, 7),
+ DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
+ 0x128, 24, 7),
+};
+
+static const struct mtk_gate peri_clks[] = {
+ /* PERI0 */
+ GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
+ GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
+ GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
+ GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
+ GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
+ GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
+ GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
+ GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
+ GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
+ GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
+ GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
+ GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
+ GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
+ GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
+ GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
+ GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
+ GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
+ GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
+ GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
+ GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
+ GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
+ GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
+ GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
+ GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
+ GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
+ GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
+ GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
+
+ /* PERI1 */
+ GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
+ GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
+};
+
+static struct mtk_composite infra_muxes[] = {
+ MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
+ 0x000, 2, 2),
+};
+
+static struct mtk_composite top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
+ 0x040, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
+ 0x040, 8, 1, 15),
+ MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
+ 0x040, 16, 1, 23),
+ MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
+ 0x040, 24, 3, 31),
+
+ /* CLK_CFG_1 */
+ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
+ 0x050, 0, 2, 7),
+ MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
+ 0x050, 8, 1, 15),
+ MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
+ 0x050, 16, 4, 23),
+ MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
+ 0x050, 24, 3, 31),
+
+ /* CLK_CFG_2 */
+ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
+ 0x060, 0, 1, 7),
+ MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
+ 0x060, 8, 3, 15),
+ MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
+ 0x060, 16, 3, 23),
+ MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
+ 0x060, 24, 3, 31),
+
+ /* CLK_CFG_3 */
+ MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
+ 0x070, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
+ 0x070, 8, 3, 15),
+ MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
+ 0x070, 16, 2, 23),
+ MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
+ 0x070, 24, 2, 31),
+
+ /* CLK_CFG_4 */
+ MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
+ 0x080, 0, 2, 7),
+ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
+ 0x080, 8, 2, 15),
+ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
+ 0x080, 16, 3, 23),
+ MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
+ 0x080, 24, 2, 31),
+
+ /* CLK_CFG_5 */
+ MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
+ 0x090, 0, 2, 7),
+ MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
+ 0x090, 8, 3, 15),
+ MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
+ 0x090, 16, 2, 23),
+ MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
+ 0x090, 24, 2, 31),
+
+ /* CLK_CFG_6 */
+ MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
+ 0x0A0, 0, 1, 7),
+ MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
+ 0x0A0, 8, 1, 15),
+ MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
+ 0x0A0, 16, 1, 23),
+ MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
+ 0x0A0, 24, 1, 31),
+
+ /* CLK_CFG_7 */
+ MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
+ 0x0B0, 0, 2, 7),
+ MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
+ 0x0B0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
+ 0x0B0, 16, 2, 23),
+
+ /* CLK_AUDDIV_0 */
+ MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
+ 0x120, 6, 1),
+ MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
+ 0x120, 7, 1),
+ MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
+ 0x120, 8, 1),
+ MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
+ 0x120, 9, 1),
+ MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
+ 0x120, 10, 1),
+ MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
+ 0x120, 11, 1),
+};
+
+static struct mtk_composite peri_muxes[] = {
+ /* PERI_GLOBALCON_CKSEL */
+ MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
+};
+
+static int mtk_topckgen_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ void __iomem *base;
+ struct device_node *node = pdev->dev.of_node;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ clk_data);
+
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
+ clk_data);
+
+ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
+ base, &mt7622_clk_lock, clk_data);
+
+ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ base, &mt7622_clk_lock, clk_data);
+
+ mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+ clk_data);
+
+ clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
+ clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
+ clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static int mtk_infrasys_init(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+
+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+ clk_data);
+
+ mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get,
+ clk_data);
+ if (r)
+ return r;
+
+ mtk_register_reset_controller(node, 1, 0x30);
+
+ return 0;
+}
+
+static int mtk_apmixedsys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+ clk_data);
+
+ mtk_clk_register_gates(node, apmixed_clks,
+ ARRAY_SIZE(apmixed_clks), clk_data);
+
+ clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
+ clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static int mtk_pericfg_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ void __iomem *base;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+ mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+ clk_data);
+
+ mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
+ &mt7622_clk_lock, clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ return r;
+
+ clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
+
+ mtk_register_reset_controller(node, 2, 0x0);
+
+ return 0;
+}
+
+static const struct of_device_id of_match_clk_mt7622[] = {
+ {
+ .compatible = "mediatek,mt7622-apmixedsys",
+ .data = mtk_apmixedsys_init,
+ }, {
+ .compatible = "mediatek,mt7622-infracfg",
+ .data = mtk_infrasys_init,
+ }, {
+ .compatible = "mediatek,mt7622-topckgen",
+ .data = mtk_topckgen_init,
+ }, {
+ .compatible = "mediatek,mt7622-pericfg",
+ .data = mtk_pericfg_init,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt7622_probe(struct platform_device *pdev)
+{
+ int (*clk_init)(struct platform_device *);
+ int r;
+
+ clk_init = of_device_get_match_data(&pdev->dev);
+ if (!clk_init)
+ return -EINVAL;
+
+ r = clk_init(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt7622_drv = {
+ .probe = clk_mt7622_probe,
+ .driver = {
+ .name = "clk-mt7622",
+ .of_match_table = of_match_clk_mt7622,
+ },
+};
+
+static int clk_mt7622_init(void)
+{
+ return platform_driver_register(&clk_mt7622_drv);
+}
+
+arch_initcall(clk_mt7622_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7629-eth.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7629-eth.c
new file mode 100644
index 0000000..88279d0
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
+ * Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt7629-clk.h>
+
+#define GATE_ETH(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = ð_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate_regs eth_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+static const struct mtk_gate eth_clks[] = {
+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6),
+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
+ GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
+ GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
+};
+
+static const struct mtk_gate_regs sgmii_cg_regs = {
+ .set_ofs = 0xE4,
+ .clr_ofs = 0xE4,
+ .sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &sgmii_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate sgmii_clks[2][4] = {
+ {
+ GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en",
+ "ssusb_tx250m", 2),
+ GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en",
+ "ssusb_eq_rx250m", 3),
+ GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
+ "ssusb_cdr_ref", 4),
+ GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
+ "ssusb_cdr_fb", 5),
+ }, {
+ GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1",
+ "ssusb_tx250m", 2),
+ GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1",
+ "ssusb_eq_rx250m", 3),
+ GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1",
+ "ssusb_cdr_ref", 4),
+ GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1",
+ "ssusb_cdr_fb", 5),
+ }
+};
+
+static int clk_mt7629_ethsys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
+
+ mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ mtk_register_reset_controller(node, 1, 0x34);
+
+ return r;
+}
+
+static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ static int id;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
+
+ mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt7629_eth[] = {
+ {
+ .compatible = "mediatek,mt7629-ethsys",
+ .data = clk_mt7629_ethsys_init,
+ }, {
+ .compatible = "mediatek,mt7629-sgmiisys",
+ .data = clk_mt7629_sgmiisys_init,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt7629_eth_probe(struct platform_device *pdev)
+{
+ int (*clk_init)(struct platform_device *);
+ int r;
+
+ clk_init = of_device_get_match_data(&pdev->dev);
+ if (!clk_init)
+ return -EINVAL;
+
+ r = clk_init(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt7629_eth_drv = {
+ .probe = clk_mt7629_eth_probe,
+ .driver = {
+ .name = "clk-mt7629-eth",
+ .of_match_table = of_match_clk_mt7629_eth,
+ },
+};
+
+builtin_platform_driver(clk_mt7629_eth_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7629-hif.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7629-hif.c
new file mode 100644
index 0000000..5c5b372
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
+ * Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt7629-clk.h>
+
+#define GATE_PCIE(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &pcie_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_SSUSB(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ssusb_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate_regs pcie_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+static const struct mtk_gate_regs ssusb_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+static const struct mtk_gate ssusb_clks[] = {
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
+ "to_u2_phy_1p", 0),
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
+ GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
+ GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
+ GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "to_usb3_mcu", 7),
+ GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "to_usb3_dma", 8),
+};
+
+static const struct mtk_gate pcie_clks[] = {
+ GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
+ GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
+ GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "from_top_ahb", 14),
+ GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "from_top_axi", 15),
+ GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
+ GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
+ GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
+ GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
+ GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "from_top_ahb", 20),
+ GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "from_top_axi", 21),
+ GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
+ GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
+};
+
+static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+
+ mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ mtk_register_reset_controller(node, 1, 0x34);
+
+ return r;
+}
+
+static int clk_mt7629_pciesys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+
+ mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ mtk_register_reset_controller(node, 1, 0x34);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt7629_hif[] = {
+ {
+ .compatible = "mediatek,mt7629-pciesys",
+ .data = clk_mt7629_pciesys_init,
+ }, {
+ .compatible = "mediatek,mt7629-ssusbsys",
+ .data = clk_mt7629_ssusbsys_init,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt7629_hif_probe(struct platform_device *pdev)
+{
+ int (*clk_init)(struct platform_device *);
+ int r;
+
+ clk_init = of_device_get_match_data(&pdev->dev);
+ if (!clk_init)
+ return -EINVAL;
+
+ r = clk_init(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt7629_hif_drv = {
+ .probe = clk_mt7629_hif_probe,
+ .driver = {
+ .name = "clk-mt7629-hif",
+ .of_match_table = of_match_clk_mt7629_hif,
+ },
+};
+
+builtin_platform_driver(clk_mt7629_hif_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7629.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7629.c
new file mode 100644
index 0000000..d623399
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt7629.c
@@ -0,0 +1,723 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
+ * Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+#include "clk-cpumux.h"
+
+#include <dt-bindings/clock/mt7629-clk.h>
+
+#define MT7629_PLL_FMAX (2500UL * MHZ)
+#define CON0_MT7629_RST_BAR BIT(24)
+
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
+ _pcw_shift, _div_table, _parent_name) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .flags = _flags, \
+ .rst_bar_mask = CON0_MT7629_RST_BAR, \
+ .fmax = MT7629_PLL_FMAX, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .div_table = _div_table, \
+ .parent_name = _parent_name, \
+ }
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
+ _pcw_shift) \
+ PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
+ NULL, "clk20m")
+
+#define GATE_APMIXED(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &apmixed_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_INFRA(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_PERI0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_PERI1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static DEFINE_SPINLOCK(mt7629_clk_lock);
+
+static const char * const axi_parents[] = {
+ "clkxtal",
+ "syspll1_d2",
+ "syspll_d5",
+ "syspll1_d4",
+ "univpll_d5",
+ "univpll2_d2",
+ "univpll_d7",
+ "dmpll_ck"
+};
+
+static const char * const mem_parents[] = {
+ "clkxtal",
+ "dmpll_ck"
+};
+
+static const char * const ddrphycfg_parents[] = {
+ "clkxtal",
+ "syspll1_d8"
+};
+
+static const char * const eth_parents[] = {
+ "clkxtal",
+ "syspll1_d2",
+ "univpll1_d2",
+ "syspll1_d4",
+ "univpll_d5",
+ "sgmiipll_d2",
+ "univpll_d7",
+ "dmpll_ck"
+};
+
+static const char * const pwm_parents[] = {
+ "clkxtal",
+ "univpll2_d4"
+};
+
+static const char * const f10m_ref_parents[] = {
+ "clkxtal",
+ "sgmiipll_d2"
+};
+
+static const char * const nfi_infra_parents[] = {
+ "clkxtal",
+ "clkxtal",
+ "clkxtal",
+ "clkxtal",
+ "clkxtal",
+ "clkxtal",
+ "univpll2_d8",
+ "univpll3_d4",
+ "syspll1_d8",
+ "univpll1_d8",
+ "syspll4_d2",
+ "syspll2_d4",
+ "univpll2_d4",
+ "univpll3_d2",
+ "syspll1_d4",
+ "syspll_d7"
+};
+
+static const char * const flash_parents[] = {
+ "clkxtal",
+ "univpll_d80_d4",
+ "syspll2_d8",
+ "syspll3_d4",
+ "univpll3_d4",
+ "univpll1_d8",
+ "syspll2_d4",
+ "univpll2_d4"
+};
+
+static const char * const uart_parents[] = {
+ "clkxtal",
+ "univpll2_d8"
+};
+
+static const char * const spi0_parents[] = {
+ "clkxtal",
+ "syspll3_d2",
+ "clkxtal",
+ "syspll2_d4",
+ "syspll4_d2",
+ "univpll2_d4",
+ "univpll1_d8",
+ "clkxtal"
+};
+
+static const char * const spi1_parents[] = {
+ "clkxtal",
+ "syspll3_d2",
+ "clkxtal",
+ "syspll4_d4",
+ "syspll4_d2",
+ "univpll2_d4",
+ "univpll1_d8",
+ "clkxtal"
+};
+
+static const char * const msdc30_0_parents[] = {
+ "clkxtal",
+ "univpll2_d16",
+ "univ48m"
+};
+
+static const char * const msdc30_1_parents[] = {
+ "clkxtal",
+ "univpll2_d16",
+ "univ48m",
+ "syspll2_d4",
+ "univpll2_d4",
+ "syspll_d7",
+ "syspll2_d2",
+ "univpll2_d2"
+};
+
+static const char * const ap2wbmcu_parents[] = {
+ "clkxtal",
+ "syspll1_d2",
+ "univ48m",
+ "syspll1_d8",
+ "univpll2_d4",
+ "syspll_d7",
+ "syspll2_d2",
+ "univpll2_d2"
+};
+
+static const char * const audio_parents[] = {
+ "clkxtal",
+ "syspll3_d4",
+ "syspll4_d4",
+ "syspll1_d16"
+};
+
+static const char * const aud_intbus_parents[] = {
+ "clkxtal",
+ "syspll1_d4",
+ "syspll4_d2",
+ "dmpll_d4"
+};
+
+static const char * const pmicspi_parents[] = {
+ "clkxtal",
+ "syspll1_d8",
+ "syspll3_d4",
+ "syspll1_d16",
+ "univpll3_d4",
+ "clkxtal",
+ "univpll2_d4",
+ "dmpll_d8"
+};
+
+static const char * const scp_parents[] = {
+ "clkxtal",
+ "syspll1_d8",
+ "univpll2_d2",
+ "univpll2_d4"
+};
+
+static const char * const atb_parents[] = {
+ "clkxtal",
+ "syspll1_d2",
+ "syspll_d5"
+};
+
+static const char * const hif_parents[] = {
+ "clkxtal",
+ "syspll1_d2",
+ "univpll1_d2",
+ "syspll1_d4",
+ "univpll_d5",
+ "clk_null",
+ "univpll_d7"
+};
+
+static const char * const sata_parents[] = {
+ "clkxtal",
+ "univpll2_d4"
+};
+
+static const char * const usb20_parents[] = {
+ "clkxtal",
+ "univpll3_d4",
+ "syspll1_d8"
+};
+
+static const char * const aud1_parents[] = {
+ "clkxtal"
+};
+
+static const char * const irrx_parents[] = {
+ "clkxtal",
+ "syspll4_d16"
+};
+
+static const char * const crypto_parents[] = {
+ "clkxtal",
+ "univpll_d3",
+ "univpll1_d2",
+ "syspll1_d2",
+ "univpll_d5",
+ "syspll_d5",
+ "univpll2_d2",
+ "syspll_d2"
+};
+
+static const char * const gpt10m_parents[] = {
+ "clkxtal",
+ "clkxtal_d4"
+};
+
+static const char * const peribus_ck_parents[] = {
+ "syspll1_d8",
+ "syspll1_d4"
+};
+
+static const char * const infra_mux1_parents[] = {
+ "clkxtal",
+ "armpll",
+ "main_core_en",
+ "armpll"
+};
+
+static const struct mtk_gate_regs apmixed_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x8,
+};
+
+static const struct mtk_gate_regs infra_cg_regs = {
+ .set_ofs = 0x40,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x48,
+};
+
+static const struct mtk_gate_regs peri0_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x10,
+ .sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs peri1_cg_regs = {
+ .set_ofs = 0xC,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x1C,
+};
+
+static const struct mtk_pll_data plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
+ 0, 21, 0x0204, 24, 0, 0x0204, 0),
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
+ HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
+ PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
+ HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
+ PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
+ 0, 21, 0x0300, 1, 0, 0x0304, 0),
+ PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
+ 0, 21, 0x0314, 1, 0, 0x0318, 0),
+ PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
+ 0, 21, 0x0358, 1, 0, 0x035C, 0),
+};
+
+static const struct mtk_gate apmixed_clks[] = {
+ GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
+};
+
+static const struct mtk_gate infra_clks[] = {
+ GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "hd_faxi", 0),
+ GATE_INFRA(CLK_INFRA_TRNG_PD, "infra_trng_pd", "hd_faxi", 2),
+ GATE_INFRA(CLK_INFRA_DEVAPC_PD, "infra_devapc_pd", "hd_faxi", 4),
+ GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "infrao_10m", 18),
+ GATE_INFRA(CLK_INFRA_SEJ_PD, "infra_sej_pd", "infrao_10m", 19),
+};
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
+ 31250000),
+ FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
+ 31250000),
+ FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
+ 125000000),
+ FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
+ 125000000),
+ FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
+ 250000000),
+ FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
+ 250000000),
+ FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
+ 33333333),
+ FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
+ 50000000),
+ FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
+ 50000000),
+ FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
+ 50000000),
+};
+
+static const struct mtk_fixed_factor top_divs[] = {
+ FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
+ FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
+ FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
+ FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
+ FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
+ FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
+ FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
+ FACTOR(CLK_TOP_PWM_QTR_26M, "pwm_qtr_26m", "clkxtal", 1, 1),
+ FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "cpum_tck", 1, 1),
+ FACTOR(CLK_TOP_TO_USB3_DA_TOP, "to_usb3_da_top", "clkxtal", 1, 1),
+ FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
+ FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
+ FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "mempll", 1, 4),
+ FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "mempll", 1, 8),
+ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
+ FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
+ FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
+ FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6),
+ FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
+ FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
+ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
+ FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
+ FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
+ FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
+ FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
+ FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
+ FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
+ FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
+ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
+ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
+ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
+ FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
+ FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
+ FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
+ FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
+ FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
+ FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
+ FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
+ FACTOR(CLK_TOP_CLKXTAL_D4, "clkxtal_d4", "clkxtal", 1, 4),
+ FACTOR(CLK_TOP_HD_FAXI, "hd_faxi", "axi_sel", 1, 1),
+ FACTOR(CLK_TOP_FAXI, "faxi", "axi_sel", 1, 1),
+ FACTOR(CLK_TOP_F_FAUD_INTBUS, "f_faud_intbus", "aud_intbus_sel", 1, 1),
+ FACTOR(CLK_TOP_AP2WBHIF_HCLK, "ap2wbhif_hclk", "syspll1_d8", 1, 1),
+ FACTOR(CLK_TOP_10M_INFRAO, "infrao_10m", "gpt10m_sel", 1, 1),
+ FACTOR(CLK_TOP_MSDC30_1, "msdc30_1", "msdc30_1_sel", 1, 1),
+ FACTOR(CLK_TOP_SPI, "spi", "spi0_sel", 1, 1),
+ FACTOR(CLK_TOP_SF, "sf", "nfi_infra_sel", 1, 1),
+ FACTOR(CLK_TOP_FLASH, "flash", "flash_sel", 1, 1),
+ FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "sata_sel", 1, 4),
+ FACTOR(CLK_TOP_TO_USB3_MCU, "to_usb3_mcu", "axi_sel", 1, 1),
+ FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1),
+ FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1),
+ FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1),
+ FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "sata_sel", 1, 1),
+ FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "sata_sel", 1, 1),
+};
+
+static const struct mtk_gate peri_clks[] = {
+ /* PERI0 */
+ GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "pwm_qtr_26m", 2),
+ GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "pwm_qtr_26m", 3),
+ GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "pwm_qtr_26m", 4),
+ GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "pwm_qtr_26m", 5),
+ GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "pwm_qtr_26m", 6),
+ GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "pwm_qtr_26m", 7),
+ GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "pwm_qtr_26m", 8),
+ GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9),
+ GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12),
+ GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1", 14),
+ GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17),
+ GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18),
+ GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19),
+ GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20),
+ GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "faxi", 22),
+ GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "faxi", 23),
+ GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi", 28),
+ GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "sf", 29),
+ GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "faxi", 30),
+ GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "faxi", 31),
+ /* PERI1 */
+ GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash", 1),
+};
+
+static struct mtk_composite infra_muxes[] = {
+ /* INFRA_TOPCKGEN_CKMUXSEL */
+ MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000,
+ 2, 2),
+};
+
+static struct mtk_composite top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
+ 0x040, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
+ 0x040, 8, 1, 15),
+ MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
+ 0x040, 16, 1, 23),
+ MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
+ 0x040, 24, 3, 31),
+ /* CLK_CFG_1 */
+ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
+ 0x050, 0, 2, 7),
+ MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
+ 0x050, 8, 1, 15),
+ MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
+ 0x050, 16, 4, 23),
+ MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
+ 0x050, 24, 3, 31),
+ /* CLK_CFG_2 */
+ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
+ 0x060, 0, 1, 7),
+ MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
+ 0x060, 8, 3, 15),
+ MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
+ 0x060, 16, 3, 23),
+ MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
+ 0x060, 24, 3, 31),
+ /* CLK_CFG_3 */
+ MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
+ 0x070, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
+ 0x070, 8, 3, 15),
+ MUX_GATE(CLK_TOP_AP2WBMCU_SEL, "ap2wbmcu_sel", ap2wbmcu_parents,
+ 0x070, 16, 3, 23),
+ MUX_GATE(CLK_TOP_AP2WBHIF_SEL, "ap2wbhif_sel", ap2wbmcu_parents,
+ 0x070, 24, 3, 31),
+ /* CLK_CFG_4 */
+ MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
+ 0x080, 0, 2, 7),
+ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
+ 0x080, 8, 2, 15),
+ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
+ 0x080, 16, 3, 23),
+ MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
+ 0x080, 24, 2, 31),
+ /* CLK_CFG_5 */
+ MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
+ 0x090, 0, 2, 7),
+ MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents,
+ 0x090, 8, 3, 15),
+ MUX_GATE(CLK_TOP_SATA_SEL, "sata_sel", sata_parents,
+ 0x090, 16, 1, 23),
+ MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
+ 0x090, 24, 2, 31),
+ /* CLK_CFG_6 */
+ MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
+ 0x0A0, 0, 1, 7),
+ MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud1_parents,
+ 0x0A0, 8, 1, 15),
+ MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", irrx_parents,
+ 0x0A0, 16, 1, 23),
+ MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", irrx_parents,
+ 0x0A0, 24, 1, 31),
+ /* CLK_CFG_7 */
+ MUX_GATE(CLK_TOP_SATA_MCU_SEL, "sata_mcu_sel", scp_parents,
+ 0x0B0, 0, 2, 7),
+ MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, "pcie0_mcu_sel", scp_parents,
+ 0x0B0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, "pcie1_mcu_sel", scp_parents,
+ 0x0B0, 16, 2, 23),
+ MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, "ssusb_mcu_sel", scp_parents,
+ 0x0B0, 24, 2, 31),
+ /* CLK_CFG_8 */
+ MUX_GATE(CLK_TOP_CRYPTO_SEL, "crypto_sel", crypto_parents,
+ 0x0C0, 0, 3, 7),
+ MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, "sgmii_ref_1_sel", f10m_ref_parents,
+ 0x0C0, 8, 1, 15),
+ MUX_GATE(CLK_TOP_10M_SEL, "gpt10m_sel", gpt10m_parents,
+ 0x0C0, 16, 1, 23),
+};
+
+static struct mtk_composite peri_muxes[] = {
+ /* PERI_GLOBALCON_CKSEL */
+ MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
+};
+
+static int mtk_topckgen_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ void __iomem *base;
+ struct device_node *node = pdev->dev.of_node;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ clk_data);
+
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
+ clk_data);
+
+ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
+ base, &mt7629_clk_lock, clk_data);
+
+ clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
+ clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
+ clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static int mtk_infrasys_init(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+
+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+ clk_data);
+
+ mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get,
+ clk_data);
+ if (r)
+ return r;
+
+ return 0;
+}
+
+static int mtk_pericfg_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ void __iomem *base;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+ mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+ clk_data);
+
+ mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
+ &mt7629_clk_lock, clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ return r;
+
+ clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
+
+ return 0;
+}
+
+static int mtk_apmixedsys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+ clk_data);
+
+ mtk_clk_register_gates(node, apmixed_clks,
+ ARRAY_SIZE(apmixed_clks), clk_data);
+
+ clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
+ clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+
+static const struct of_device_id of_match_clk_mt7629[] = {
+ {
+ .compatible = "mediatek,mt7629-apmixedsys",
+ .data = mtk_apmixedsys_init,
+ }, {
+ .compatible = "mediatek,mt7629-infracfg",
+ .data = mtk_infrasys_init,
+ }, {
+ .compatible = "mediatek,mt7629-topckgen",
+ .data = mtk_topckgen_init,
+ }, {
+ .compatible = "mediatek,mt7629-pericfg",
+ .data = mtk_pericfg_init,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt7629_probe(struct platform_device *pdev)
+{
+ int (*clk_init)(struct platform_device *);
+ int r;
+
+ clk_init = of_device_get_match_data(&pdev->dev);
+ if (!clk_init)
+ return -EINVAL;
+
+ r = clk_init(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt7629_drv = {
+ .probe = clk_mt7629_probe,
+ .driver = {
+ .name = "clk-mt7629",
+ .of_match_table = of_match_clk_mt7629,
+ },
+};
+
+static int clk_mt7629_init(void)
+{
+ return platform_driver_register(&clk_mt7629_drv);
+}
+
+arch_initcall(clk_mt7629_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8135.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8135.c
new file mode 100644
index 0000000..07c21e4
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8135.c
@@ -0,0 +1,645 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/mfd/syscon.h>
+#include <dt-bindings/clock/mt8135-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static DEFINE_SPINLOCK(mt8135_clk_lock);
+
+static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
+ FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
+ FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
+ FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
+ FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
+};
+
+static const struct mtk_fixed_factor top_divs[] __initconst = {
+ FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
+ FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3),
+ FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5),
+ FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7),
+
+ FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
+ FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
+ FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
+ FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
+
+ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
+ FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
+ FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
+ FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
+ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2),
+ FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2),
+
+ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1),
+ FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3),
+ FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5),
+ FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6),
+ FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8),
+ FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12),
+
+ FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1),
+
+ FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1),
+ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
+
+ FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1),
+
+ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
+ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
+
+ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
+ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
+
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
+
+ FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1),
+ FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4),
+ FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8),
+ FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16),
+ FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24),
+
+ FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
+ FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
+ FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
+
+ FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1),
+ FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1),
+
+ FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1),
+
+ FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2),
+ FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3),
+
+ FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2),
+ FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4),
+
+ FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
+};
+
+static const char * const axi_parents[] __initconst = {
+ "clk26m",
+ "syspll_d3",
+ "syspll_d4",
+ "syspll_d6",
+ "univpll_d5",
+ "univpll2_d2",
+ "syspll_d3p5"
+};
+
+static const char * const smi_parents[] __initconst = {
+ "clk26m",
+ "clkph_mck",
+ "syspll_d2p5",
+ "syspll_d3",
+ "syspll_d8",
+ "univpll_d5",
+ "univpll1_d2",
+ "univpll1_d6",
+ "mmpll_d3",
+ "mmpll_d4",
+ "mmpll_d5",
+ "mmpll_d6",
+ "mmpll_d7",
+ "vdecpll",
+ "lvdspll"
+};
+
+static const char * const mfg_parents[] __initconst = {
+ "clk26m",
+ "univpll1_d4",
+ "syspll_d2",
+ "syspll_d2p5",
+ "syspll_d3",
+ "univpll_d5",
+ "univpll1_d2",
+ "mmpll_d2",
+ "mmpll_d3",
+ "mmpll_d4",
+ "mmpll_d5",
+ "mmpll_d6",
+ "mmpll_d7"
+};
+
+static const char * const irda_parents[] __initconst = {
+ "clk26m",
+ "univpll2_d8",
+ "univpll1_d6"
+};
+
+static const char * const cam_parents[] __initconst = {
+ "clk26m",
+ "syspll_d3",
+ "syspll_d3p5",
+ "syspll_d4",
+ "univpll_d5",
+ "univpll2_d2",
+ "univpll_d7",
+ "univpll1_d4"
+};
+
+static const char * const aud_intbus_parents[] __initconst = {
+ "clk26m",
+ "syspll_d6",
+ "univpll_d10"
+};
+
+static const char * const jpg_parents[] __initconst = {
+ "clk26m",
+ "syspll_d5",
+ "syspll_d4",
+ "syspll_d3",
+ "univpll_d7",
+ "univpll2_d2",
+ "univpll_d5"
+};
+
+static const char * const disp_parents[] __initconst = {
+ "clk26m",
+ "syspll_d3p5",
+ "syspll_d3",
+ "univpll2_d2",
+ "univpll_d5",
+ "univpll1_d2",
+ "lvdspll",
+ "vdecpll"
+};
+
+static const char * const msdc30_parents[] __initconst = {
+ "clk26m",
+ "syspll_d6",
+ "syspll_d5",
+ "univpll1_d4",
+ "univpll2_d4",
+ "msdcpll"
+};
+
+static const char * const usb20_parents[] __initconst = {
+ "clk26m",
+ "univpll2_d6",
+ "univpll1_d10"
+};
+
+static const char * const venc_parents[] __initconst = {
+ "clk26m",
+ "syspll_d3",
+ "syspll_d8",
+ "univpll_d5",
+ "univpll1_d6",
+ "mmpll_d4",
+ "mmpll_d5",
+ "mmpll_d6"
+};
+
+static const char * const spi_parents[] __initconst = {
+ "clk26m",
+ "syspll_d6",
+ "syspll_d8",
+ "syspll_d10",
+ "univpll1_d6",
+ "univpll1_d8"
+};
+
+static const char * const uart_parents[] __initconst = {
+ "clk26m",
+ "univpll2_d8"
+};
+
+static const char * const mem_parents[] __initconst = {
+ "clk26m",
+ "clkph_mck"
+};
+
+static const char * const camtg_parents[] __initconst = {
+ "clk26m",
+ "univpll_d26",
+ "univpll1_d6",
+ "syspll_d16",
+ "syspll_d8"
+};
+
+static const char * const audio_parents[] __initconst = {
+ "clk26m",
+ "syspll_d24"
+};
+
+static const char * const fix_parents[] __initconst = {
+ "rtc32k",
+ "clk26m",
+ "univpll_d5",
+ "univpll_d7",
+ "univpll1_d2",
+ "univpll1_d4",
+ "univpll1_d6",
+ "univpll1_d8"
+};
+
+static const char * const vdec_parents[] __initconst = {
+ "clk26m",
+ "vdecpll",
+ "clkph_mck",
+ "syspll_d2p5",
+ "syspll_d3",
+ "syspll_d3p5",
+ "syspll_d4",
+ "syspll_d5",
+ "syspll_d6",
+ "syspll_d8",
+ "univpll1_d2",
+ "univpll2_d2",
+ "univpll_d7",
+ "univpll_d10",
+ "univpll2_d4",
+ "lvdspll"
+};
+
+static const char * const ddrphycfg_parents[] __initconst = {
+ "clk26m",
+ "axi_sel",
+ "syspll_d12"
+};
+
+static const char * const dpilvds_parents[] __initconst = {
+ "clk26m",
+ "lvdspll",
+ "lvdspll_d2",
+ "lvdspll_d4",
+ "lvdspll_d8"
+};
+
+static const char * const pmicspi_parents[] __initconst = {
+ "clk26m",
+ "univpll2_d6",
+ "syspll_d8",
+ "syspll_d10",
+ "univpll1_d10",
+ "mempll_mck_d4",
+ "univpll_d26",
+ "syspll_d24"
+};
+
+static const char * const smi_mfg_as_parents[] __initconst = {
+ "clk26m",
+ "smi_sel",
+ "mfg_sel",
+ "mem_sel"
+};
+
+static const char * const gcpu_parents[] __initconst = {
+ "clk26m",
+ "syspll_d4",
+ "univpll_d7",
+ "syspll_d5",
+ "syspll_d6"
+};
+
+static const char * const dpi1_parents[] __initconst = {
+ "clk26m",
+ "tvhdmi_h_ck",
+ "tvhdmi_d2",
+ "tvhdmi_d4"
+};
+
+static const char * const cci_parents[] __initconst = {
+ "clk26m",
+ "mainpll_537p3m",
+ "univpll_d3",
+ "syspll_d2p5",
+ "syspll_d3",
+ "syspll_d5"
+};
+
+static const char * const apll_parents[] __initconst = {
+ "clk26m",
+ "apll_ck",
+ "apll_d4",
+ "apll_d8",
+ "apll_d16",
+ "apll_d24"
+};
+
+static const char * const hdmipll_parents[] __initconst = {
+ "clk26m",
+ "hdmitx_clkdig_cts",
+ "hdmitx_clkdig_d2",
+ "hdmitx_clkdig_d3"
+};
+
+static const struct mtk_composite top_muxes[] __initconst = {
+ /* CLK_CFG_0 */
+ MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
+ 0x0140, 0, 3, INVALID_MUX_GATE_BIT),
+ MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
+ MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
+ MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
+ /* CLK_CFG_1 */
+ MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
+ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
+ 0x0144, 8, 2, 15),
+ MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
+ MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
+ /* CLK_CFG_2 */
+ MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
+ MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
+ MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31),
+ /* CLK_CFG_3 */
+ MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
+ /* CLK_CFG_4 */
+ MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
+ MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
+ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
+ /* CLK_CFG_6 */
+ MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
+ MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
+ MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31),
+ /* CLK_CFG_7 */
+ MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
+ MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
+ MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
+ 0x015c, 16, 2, 23),
+ MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
+ /* CLK_CFG_8 */
+ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
+ MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents,
+ 0x0164, 16, 2, 23),
+ MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31),
+ /* CLK_CFG_9 */
+ MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7),
+ MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15),
+ MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
+ MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),
+};
+
+static const struct mtk_gate_regs infra_cg_regs = {
+ .set_ofs = 0x0040,
+ .clr_ofs = 0x0044,
+ .sta_ofs = 0x0048,
+};
+
+#define GATE_ICG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate infra_clks[] __initconst = {
+ GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
+ GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
+ GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21),
+ GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20),
+ GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
+ GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
+ GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
+ GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7),
+ GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6),
+ GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
+ GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2),
+ GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
+ GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
+};
+
+static const struct mtk_gate_regs peri0_cg_regs = {
+ .set_ofs = 0x0008,
+ .clr_ofs = 0x0010,
+ .sta_ofs = 0x0018,
+};
+
+static const struct mtk_gate_regs peri1_cg_regs = {
+ .set_ofs = 0x000c,
+ .clr_ofs = 0x0014,
+ .sta_ofs = 0x001c,
+};
+
+#define GATE_PERI0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_PERI1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate peri_gates[] __initconst = {
+ /* PERI0 */
+ GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
+ GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
+ GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
+ GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
+ GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
+ GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
+ GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
+ GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
+ GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
+ GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
+ GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
+ GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
+ GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
+ GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
+ GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
+ GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
+ GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
+ GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
+ GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
+ GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
+ GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
+ GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
+ GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
+ GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
+ GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
+ GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
+ GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
+ GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
+ GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
+ GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
+ GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
+ GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
+ /* PERI1 */
+ GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
+ GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
+ GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
+ GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
+ GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
+ GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
+ GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
+ GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
+ GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
+};
+
+static const char * const uart_ck_sel_parents[] __initconst = {
+ "clk26m",
+ "uart_sel",
+};
+
+static const struct mtk_composite peri_clks[] __initconst = {
+ MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
+ MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
+ MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
+ MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
+};
+
+static void __init mtk_topckgen_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ void __iomem *base;
+ int r;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return;
+ }
+
+ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+ mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
+ &mt8135_clk_lock, clk_data);
+
+ clk_prepare_enable(clk_data->clks[CLK_TOP_CCI_SEL]);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init);
+
+static void __init mtk_infrasys_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+
+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+ clk_data);
+
+ clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ mtk_register_reset_controller(node, 2, 0x30);
+}
+CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
+
+static void __init mtk_pericfg_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ void __iomem *base;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return;
+ }
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+ mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
+ clk_data);
+ mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
+ &mt8135_clk_lock, clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ mtk_register_reset_controller(node, 2, 0);
+}
+CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
+
+#define MT8135_PLL_FMAX (2000 * MHZ)
+#define CON0_MT8135_RST_BAR BIT(27)
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .flags = _flags, \
+ .rst_bar_mask = CON0_MT8135_RST_BAR, \
+ .fmax = MT8135_PLL_FMAX, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ }
+
+static const struct mtk_pll_data plls[] = {
+ PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
+ PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
+ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
+ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
+ PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
+ PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
+ PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
+};
+
+static void __init mtk_apmixedsys_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+ if (!clk_data)
+ return;
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+}
+CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys",
+ mtk_apmixedsys_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-apu.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-apu.c
new file mode 100644
index 0000000..62717e7
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-apu.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8168-clk.h>
+
+static const struct mtk_gate_regs apu_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_APU(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &apu_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate apu_clks[] = {
+ GATE_APU(CLK_APU_AHB, "apu_ahb", "ifr_apu_axi", 5),
+ GATE_APU(CLK_APU_EDMA, "apu_edma", "apu_sel", 4),
+ GATE_APU(CLK_APU_IF_CK, "apu_if_ck", "apu_if_sel", 3),
+ GATE_APU(CLK_APU_JTAG, "apu_jtag", "clk26m_ck", 2),
+ GATE_APU(CLK_APU_AXI, "apu_axi", "apu_sel", 1),
+ GATE_APU(CLK_APU_IPU_CK, "apu_ck", "apu_sel", 0),
+};
+
+static int clk_mt8168_apu_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APU_NR_CLK);
+
+ mtk_clk_register_gates(node, apu_clks, ARRAY_SIZE(apu_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt8168_apu[] = {
+ { .compatible = "mediatek,mt8168-apu", },
+ {}
+};
+
+static struct platform_driver clk_mt8168_apu_drv = {
+ .probe = clk_mt8168_apu_probe,
+ .driver = {
+ .name = "clk-mt8168-apu",
+ .of_match_table = of_match_clk_mt8168_apu,
+ },
+};
+
+builtin_platform_driver(clk_mt8168_apu_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-cam.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-cam.c
new file mode 100644
index 0000000..a64a9b9
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-cam.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8168-clk.h>
+
+static const struct mtk_gate_regs cam_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_CAM(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cam_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate cam_clks[] = {
+ GATE_CAM(CLK_CAM_LARB2, "cam_larb2", "mm_sel", 0),
+ GATE_CAM(CLK_CAM, "cam", "mm_sel", 6),
+ GATE_CAM(CLK_CAMTG, "camtg", "mm_sel", 7),
+ GATE_CAM(CLK_CAM_SENIF, "cam_senif", "mm_sel", 8),
+ GATE_CAM(CLK_CAMSV0, "camsv0", "mm_sel", 9),
+ GATE_CAM(CLK_CAMSV1, "camsv1", "mm_sel", 10),
+ GATE_CAM(CLK_CAM_FDVT, "cam_fdvt", "mm_sel", 11),
+ GATE_CAM(CLK_CAM_WPE, "cam_wpe", "mm_sel", 12),
+};
+
+static int clk_mt8168_cam_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
+
+ mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks), clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt8168_cam[] = {
+ { .compatible = "mediatek,mt8168-imgsys", },
+ {}
+};
+
+static struct platform_driver clk_mt8168_cam_drv = {
+ .probe = clk_mt8168_cam_probe,
+ .driver = {
+ .name = "clk-mt8168-cam",
+ .of_match_table = of_match_clk_mt8168_cam,
+ },
+};
+
+builtin_platform_driver(clk_mt8168_cam_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-img.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-img.c
new file mode 100644
index 0000000..d1ea413
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-img.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8168-clk.h>
+
+static const struct mtk_gate_regs img_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &img_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate img_clks[] = {
+ GATE_IMG(CLK_IMG_LARB2, "img_larb2", "mm_sel", 0),
+ GATE_IMG(CLK_IMG_CAM, "img_cam", "mm_sel", 6),
+ GATE_IMG(CLK_IMG_CAMTG, "img_camtg", "mm_sel", 7),
+ GATE_IMG(CLK_IMG_SENIF, "img_senif", "mm_sel", 8),
+ GATE_IMG(CLK_IMG_CAMSV0, "img_camsv0", "mm_sel", 9),
+ GATE_IMG(CLK_IMG_CAMSV1, "img_camsv1", "mm_sel", 10),
+ GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),
+ GATE_IMG(CLK_IMG_CAM_WPE, "img_cam_wpe", "mm_sel", 12),
+};
+
+static int clk_mt8168_img_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
+
+ mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt8168_img[] = {
+ { .compatible = "mediatek,mt8168-imgsys", },
+ {}
+};
+
+static struct platform_driver clk_mt8168_img_drv = {
+ .probe = clk_mt8168_img_probe,
+ .driver = {
+ .name = "clk-mt8168-img",
+ .of_match_table = of_match_clk_mt8168_img,
+ },
+};
+
+builtin_platform_driver(clk_mt8168_img_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-mfg.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-mfg.c
new file mode 100644
index 0000000..c992cb2
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-mfg.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8168-clk.h>
+
+static const struct mtk_gate_regs mfg0_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs mfg1_cg_regs = {
+ .set_ofs = 0x280,
+ .clr_ofs = 0x280,
+ .sta_ofs = 0x280,
+};
+
+#define GATE_MFG0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mfg0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_MFG1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mfg1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+static const struct mtk_gate mfg_clks[] = {
+ /* MFG0 */
+ GATE_MFG0(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
+ /* MFG1 */
+ GATE_MFG1(CLK_MFG_MBIST_DIAG, "mfg_mbist_diag", "mbist_diag_sel", 24),
+};
+
+static int clk_mt8168_mfg_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
+
+ mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt8168_mfg[] = {
+ { .compatible = "mediatek,mt8168-mfgcfg", },
+ {}
+};
+
+static struct platform_driver clk_mt8168_mfg_drv = {
+ .probe = clk_mt8168_mfg_probe,
+ .driver = {
+ .name = "clk-mt8168-mfg",
+ .of_match_table = of_match_clk_mt8168_mfg,
+ },
+};
+
+builtin_platform_driver(clk_mt8168_mfg_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-mm.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-mm.c
new file mode 100644
index 0000000..7ac7f43
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-mm.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8168-clk.h>
+
+static const struct mtk_gate_regs mm0_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mm1_cg_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+
+#define GATE_MM0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_MM1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate mm_clks[] = {
+ /* MM0 */
+ GATE_MM0(CLK_MM_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 0),
+ GATE_MM0(CLK_MM_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_sel", 1),
+ GATE_MM0(CLK_MM_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 2),
+ GATE_MM0(CLK_MM_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 3),
+ GATE_MM0(CLK_MM_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 4),
+ GATE_MM0(CLK_MM_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 5),
+ GATE_MM0(CLK_MM_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_sel", 6),
+ GATE_MM0(CLK_MM_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 7),
+ GATE_MM0(CLK_MM_MM_DISP_OVL0_21, "mm_disp_ovl0_21", "mm_sel", 8),
+ GATE_MM0(CLK_MM_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_sel", 9),
+ GATE_MM0(CLK_MM_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 10),
+ GATE_MM0(CLK_MM_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 11),
+ GATE_MM0(CLK_MM_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 12),
+ GATE_MM0(CLK_MM_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 13),
+ GATE_MM0(CLK_MM_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 14),
+ GATE_MM0(CLK_MM_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 15),
+ GATE_MM0(CLK_MM_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 16),
+ GATE_MM0(CLK_MM_MM_DSI0, "mm_dsi0", "mm_sel", 17),
+ GATE_MM0(CLK_MM_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 18),
+ GATE_MM0(CLK_MM_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 19),
+ GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20),
+ GATE_MM0(CLK_MM_MM_FAKE, "mm_fake", "mm_sel", 21),
+ GATE_MM0(CLK_MM_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 22),
+ GATE_MM0(CLK_MM_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 23),
+ GATE_MM0(CLK_MM_MM_SMI_COMM0, "mm_smi_comm0", "mm_sel", 24),
+ GATE_MM0(CLK_MM_MM_SMI_COMM1, "mm_smi_comm1", "mm_sel", 25),
+ GATE_MM0(CLK_MM_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 26),
+ GATE_MM0(CLK_MM_MM_SMI_IMG, "mm_smi_img", "mm_sel", 27),
+ GATE_MM0(CLK_MM_MM_SMI_CAM, "mm_smi_cam", "mm_sel", 28),
+ GATE_MM0(CLK_MM_IMG_IMG_DL_RELAY, "mm_dl_relay", "mm_sel", 29),
+ GATE_MM0(CLK_MM_IMG_IMG_DL_ASYNC_TOP, "mm_dl_async_top", "mm_sel", 30),
+ GATE_MM0(CLK_MM_DSI0_DIG_DSI, "mm_dsi0_dig_dsi", "dsi0_lntc_dsick", 31),
+ /* MM1 */
+ GATE_MM1(CLK_MM_26M_HRTWT, "mm_f26m_hrtwt", "clk26m_ck", 0),
+ GATE_MM1(CLK_MM_MM_DPI0, "mm_dpi0", "mm_sel", 1),
+ GATE_MM1(CLK_MM_LVDSTX_PXL, "mm_flvdstx_pxl", "vpll_dpix", 2),
+ GATE_MM1(CLK_MM_LVDSTX_CTS, "mm_flvdstx_cts", "lvdstx_dig_cts", 3),
+};
+
+static int clk_mt8168_mm_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+
+ mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt8168_mm[] = {
+ { .compatible = "mediatek,mt8168-mmsys", },
+ {}
+};
+
+static struct platform_driver clk_mt8168_mm_drv = {
+ .probe = clk_mt8168_mm_probe,
+ .driver = {
+ .name = "clk-mt8168-mm",
+ .of_match_table = of_match_clk_mt8168_mm,
+ },
+};
+
+builtin_platform_driver(clk_mt8168_mm_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-vdec.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-vdec.c
new file mode 100644
index 0000000..865ad31
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-vdec.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8168-clk.h>
+
+static const struct mtk_gate_regs vdec0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs vdec1_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0x8,
+};
+
+#define GATE_VDEC0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vdec0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VDEC1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vdec1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate vdec_clks[] = {
+ /* VDEC0 */
+ GATE_VDEC0(CLK_VDEC_VDEC, "vdec_fvdec_ck", "mm_sel", 0),
+ /* VDEC1 */
+ GATE_VDEC1(CLK_VDEC_LARB1, "vdec_flarb1_ck", "mm_sel", 0),
+};
+
+static int clk_mt8168_vdec_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
+
+ mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt8168_vdec[] = {
+ { .compatible = "mediatek,mt8168-vdecsys", },
+ {}
+};
+
+static struct platform_driver clk_mt8168_vdec_drv = {
+ .probe = clk_mt8168_vdec_probe,
+ .driver = {
+ .name = "clk-mt8168-vdec",
+ .of_match_table = of_match_clk_mt8168_vdec,
+ },
+};
+
+builtin_platform_driver(clk_mt8168_vdec_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-venc.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-venc.c
new file mode 100644
index 0000000..8aed37b
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168-venc.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8168-clk.h>
+
+static const struct mtk_gate_regs venc_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_VENC(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &venc_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate venc_clks[] = {
+ /* VENC */
+ GATE_VENC(CLK_VENC, "venc_fvenc_ck", "mm_sel", 4),
+ GATE_VENC(CLK_VENC_JPGENC, "venc_jpgenc_ck", "mm_sel", 8),
+};
+
+static int clk_mt8168_venc_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
+
+ mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt8168_venc[] = {
+ { .compatible = "mediatek,mt8168-vencsys", },
+ {}
+};
+
+static struct platform_driver clk_mt8168_venc_drv = {
+ .probe = clk_mt8168_venc_probe,
+ .driver = {
+ .name = "clk-mt8168-venc",
+ .of_match_table = of_match_clk_mt8168_venc,
+ },
+};
+
+builtin_platform_driver(clk_mt8168_venc_drv);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168.c
new file mode 100644
index 0000000..05a32e1
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8168.c
@@ -0,0 +1,1192 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8168-clk.h>
+
+#define CLK_CFG_UPDATE 0x004
+#define CLK_CFG_UPDATE1 0x008
+static DEFINE_SPINLOCK(mt8168_clk_lock);
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
+ FIXED_CLK(CLK_TOP_I2S0_BCK, "i2s0_bck", "clk_null", 26000000),
+ FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m",
+ 75000000),
+ FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000),
+ FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m",
+ 52500000),
+};
+
+static const struct mtk_fixed_factor top_divs[] = {
+ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
+ FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
+ FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
+ FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
+ FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6),
+ FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
+ FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
+ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
+ FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
+ FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
+ FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
+ FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
+ FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
+ FACTOR(CLK_TOP_UNIVPLL, "univpll", "univpll2", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
+ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
+ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
+ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
+ FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll", 1, 96),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
+ FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
+ FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
+ FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
+ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
+ FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
+ FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
+ FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
+ FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
+ FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", "lvdspll", 1, 16),
+ FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "univpll", 1, 1),
+ FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4),
+ FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8),
+ FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", "usb20_192m_ck",
+ 1, 16),
+ FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", "usb20_192m_ck",
+ 1, 32),
+ FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
+ FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
+ FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
+ FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8),
+ FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4),
+ FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8),
+ FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
+ FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
+ FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", "dsppll", 1, 1),
+ FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", "dsppll", 1, 2),
+ FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", "dsppll", 1, 4),
+ FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", "dsppll", 1, 8),
+ FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 1),
+ FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52),
+};
+
+static const char * const axi_parents[] = {
+ "clk26m_ck",
+ "syspll_d7",
+ "syspll1_d4",
+ "syspll3_d2"
+};
+
+static const char * const mem_parents[] = {
+ "clk26m_ck",
+ "mmpll_ck",
+ "syspll_d3",
+ "syspll1_d2"
+};
+
+static const char * const mm_parents[] = {
+ "clk26m_ck",
+ "mmpll_ck",
+ "syspll1_d2",
+ "syspll_d5",
+ "syspll1_d4",
+ "univpll_d5",
+ "univpll1_d2",
+ "mmpll_d2"
+};
+
+static const char * const scp_parents[] = {
+ "clk26m_ck",
+ "syspll4_d2",
+ "univpll2_d2",
+ "syspll1_d2",
+ "univpll1_d2",
+ "syspll_d3",
+ "univpll_d3"
+};
+
+static const char * const mfg_parents[] = {
+ "clk26m_ck",
+ "mfgpll_ck",
+ "syspll_d3",
+ "univpll_d3"
+};
+
+static const char * const atb_parents[] = {
+ "clk26m_ck",
+ "syspll1_d4",
+ "syspll1_d2"
+};
+
+static const char * const camtg_parents[] = {
+ "clk26m_ck",
+ "usb20_192m_d8",
+ "univpll2_d8",
+ "usb20_192m_d4",
+ "univpll2_d32",
+ "usb20_192m_d16",
+ "usb20_192m_d32"
+};
+
+static const char * const uart_parents[] = {
+ "clk26m_ck",
+ "univpll2_d8"
+};
+
+static const char * const spi_parents[] = {
+ "clk26m_ck",
+ "univpll2_d2",
+ "univpll2_d4",
+ "univpll2_d8"
+};
+
+static const char * const msdc50_0_hc_parents[] = {
+ "clk26m_ck",
+ "syspll1_d2",
+ "univpll1_d4",
+ "syspll2_d2"
+};
+
+static const char * const msdc50_0_parents[] = {
+ "clk26m_ck",
+ "msdcpll_ck",
+ "univpll1_d2",
+ "syspll1_d2",
+ "univpll_d5",
+ "syspll2_d2",
+ "univpll1_d4",
+ "syspll4_d2"
+};
+
+static const char * const msdc50_2_parents[] = {
+ "clk26m_ck",
+ "msdcpll_ck",
+ "univpll_d3",
+ "univpll1_d2",
+ "syspll1_d2",
+ "univpll2_d2",
+ "syspll2_d2",
+ "univpll1_d4"
+};
+
+static const char * const msdc30_1_parents[] = {
+ "clk26m_ck",
+ "msdcpll_d2",
+ "univpll2_d2",
+ "syspll2_d2",
+ "univpll1_d4",
+ "syspll1_d4",
+ "syspll2_d4",
+ "univpll2_d8"
+};
+
+static const char * const audio_parents[] = {
+ "clk26m_ck",
+ "syspll3_d4",
+ "syspll4_d4",
+ "syspll1_d16"
+};
+
+static const char * const aud_intbus_parents[] = {
+ "clk26m_ck",
+ "syspll1_d4",
+ "syspll4_d2"
+};
+
+static const char * const aud_1_parents[] = {
+ "clk26m_ck",
+ "apll1_ck"
+};
+
+static const char * const aud_2_parents[] = {
+ "clk26m_ck",
+ "apll2_ck"
+};
+
+static const char * const aud_engen1_parents[] = {
+ "clk26m_ck",
+ "apll1_d2",
+ "apll1_d4",
+ "apll1_d8"
+};
+
+static const char * const aud_engen2_parents[] = {
+ "clk26m_ck",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8"
+};
+
+static const char * const aud_spdif_parents[] = {
+ "clk26m_ck",
+ "univpll_d2"
+};
+
+static const char * const disp_pwm_parents[] = {
+ "clk26m_ck",
+ "univpll2_d4"
+};
+
+static const char * const dxcc_parents[] = {
+ "clk26m_ck",
+ "syspll1_d2",
+ "syspll1_d4",
+ "syspll1_d8"
+};
+
+static const char * const ssusb_sys_parents[] = {
+ "clk26m_ck",
+ "univpll3_d4",
+ "univpll2_d4",
+ "univpll3_d2"
+};
+
+static const char * const spm_parents[] = {
+ "clk26m_ck",
+ "syspll1_d8"
+};
+
+static const char * const i2c_parents[] = {
+ "clk26m_ck",
+ "univpll3_d4",
+ "univpll3_d2",
+ "syspll1_d8",
+ "syspll2_d8"
+};
+
+static const char * const pwm_parents[] = {
+ "clk26m_ck",
+ "univpll3_d4",
+ "syspll1_d8"
+};
+
+static const char * const senif_parents[] = {
+ "clk26m_ck",
+ "univpll1_d4",
+ "univpll1_d2",
+ "univpll2_d2"
+};
+
+static const char * const aes_fde_parents[] = {
+ "clk26m_ck",
+ "msdcpll_ck",
+ "univpll_d3",
+ "univpll2_d2",
+ "univpll1_d2",
+ "syspll1_d2"
+};
+
+static const char * const dpi0_parents[] = {
+ "clk26m_ck",
+ "lvdspll_d2",
+ "lvdspll_d4",
+ "lvdspll_d8",
+ "lvdspll_d16"
+};
+
+static const char * const dsp_parents[] = {
+ "clk26m_ck",
+ "sys_26m_d2",
+ "dsppll_ck",
+ "dsppll_d2",
+ "dsppll_d4",
+ "dsppll_d8"
+};
+
+static const char * const nfi2x_parents[] = {
+ "clk26m_ck",
+ "syspll2_d2",
+ "syspll_d7",
+ "syspll_d3",
+ "syspll2_d4",
+ "msdcpll_d2",
+ "univpll1_d2",
+ "univpll_d5"
+};
+
+static const char * const nfiecc_parents[] = {
+ "clk26m_ck",
+ "syspll4_d2",
+ "univpll2_d4",
+ "syspll_d7",
+ "univpll1_d2",
+ "syspll1_d2",
+ "univpll2_d2",
+ "syspll_d5"
+};
+
+static const char * const ecc_parents[] = {
+ "clk26m_ck",
+ "univpll2_d2",
+ "univpll1_d2",
+ "univpll_d3",
+ "syspll_d2"
+};
+
+static const char * const eth_parents[] = {
+ "clk26m_ck",
+ "univpll2_d8",
+ "syspll4_d4",
+ "syspll1_d8",
+ "syspll4_d2"
+};
+
+static const char * const gcpu_parents[] = {
+ "clk26m_ck",
+ "univpll_d3",
+ "univpll2_d2",
+ "syspll_d3",
+ "syspll2_d2"
+};
+
+static const char * const gcpu_cpm_parents[] = {
+ "clk26m_ck",
+ "univpll2_d2",
+ "syspll2_d2"
+};
+
+static const char * const apu_parents[] = {
+ "clk26m_ck",
+ "univpll_d2",
+ "apupll_ck",
+ "mmpll_ck",
+ "syspll_d3",
+ "univpll1_d2",
+ "syspll1_d2",
+ "syspll1_d4"
+};
+
+static const char * const mbist_diag_parents[] = {
+ "clk26m_ck",
+ "syspll4_d4",
+ "univpll2_d8"
+};
+
+static const char * const apll_i2s0_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static struct mtk_composite top_misc_muxes[] = {
+ /* CLK_CFG_11 */
+ MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents,
+ 0x0ec, 0, 2, 7),
+ /* CLK_AUDDIV_0 */
+ MUX(CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", apll_i2s0_parents,
+ 0x320, 11, 1),
+ MUX(CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", apll_i2s0_parents,
+ 0x320, 12, 1),
+ MUX(CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", apll_i2s0_parents,
+ 0x320, 13, 1),
+ MUX(CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", apll_i2s0_parents,
+ 0x320, 14, 1),
+ MUX(CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", apll_i2s0_parents,
+ 0x320, 15, 1),
+ MUX(CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", apll_i2s0_parents,
+ 0x320, 16, 1),
+ MUX(CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", apll_i2s0_parents,
+ 0x320, 17, 1),
+};
+
+static const struct mtk_mux top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
+ 0x040, 0x044, 0x048, 0, 2, 7,
+ CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
+ 0x040, 0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
+ 0x040, 0x044, 0x048, 16, 3, 23, CLK_CFG_UPDATE, 2),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
+ 0x040, 0x044, 0x048, 24, 3, 31, CLK_CFG_UPDATE, 3),
+ /* CLK_CFG_1 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
+ 0x050, 0x054, 0x058, 0, 2, 7, CLK_CFG_UPDATE, 4),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
+ 0x050, 0x054, 0x058, 8, 2, 15, CLK_CFG_UPDATE, 5),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
+ 0x050, 0x054, 0x058, 16, 3, 23, CLK_CFG_UPDATE, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
+ 0x050, 0x054, 0x058, 24, 3, 31, CLK_CFG_UPDATE, 7),
+ /* CLK_CFG_2 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
+ 0x060, 0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
+ 0x060, 0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel",
+ msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2, 23,
+ CLK_CFG_UPDATE, 10),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel",
+ msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2, 31,
+ CLK_CFG_UPDATE, 11),
+ /* CLK_CFG_3 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
+ msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7,
+ CLK_CFG_UPDATE, 12),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel",
+ msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15,
+ CLK_CFG_UPDATE, 13),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
+ msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23,
+ CLK_CFG_UPDATE, 14),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
+ 0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE, 15),
+ /* CLK_CFG_4 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
+ aud_intbus_parents, 0x080, 0x084, 0x088, 0, 2, 7,
+ CLK_CFG_UPDATE, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
+ 0x080, 0x084, 0x088, 8, 1, 15, CLK_CFG_UPDATE, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents,
+ 0x080, 0x084, 0x088, 16, 1, 23, CLK_CFG_UPDATE, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
+ aud_engen1_parents, 0x080, 0x084, 0x088, 24, 2, 31,
+ CLK_CFG_UPDATE, 19),
+ /* CLK_CFG_5 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
+ aud_engen2_parents, 0x090, 0x094, 0x098, 0, 2, 7,
+ CLK_CFG_UPDATE, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SPDIF_SEL, "aud_spdif_sel",
+ aud_spdif_parents, 0x090, 0x094, 0x098, 8, 1, 15,
+ CLK_CFG_UPDATE, 21),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", disp_pwm_parents,
+ 0x090, 0x094, 0x098, 16, 2, 23, CLK_CFG_UPDATE, 22),
+ /* CLK_CFG_6 */
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
+ 0x0a0, 0x0a4, 0x0a8, 0, 2, 7,
+ CLK_CFG_UPDATE, 24, CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_SYS_SEL, "ssusb_sys_sel",
+ ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15,
+ CLK_CFG_UPDATE, 25),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
+ ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23,
+ CLK_CFG_UPDATE, 26),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents,
+ 0x0a0, 0x0a4, 0x0a8, 24, 1, 31,
+ CLK_CFG_UPDATE, 27, CLK_IS_CRITICAL),
+ /* CLK_CFG_7 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
+ 0x0b0, 0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
+ 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, CLK_CFG_UPDATE, 29),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SENIF_SEL, "senif_sel", senif_parents,
+ 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, CLK_CFG_UPDATE, 30),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel", aes_fde_parents,
+ 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, CLK_CFG_UPDATE, 31),
+ /* CLK_CFG_8 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", senif_parents,
+ 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, CLK_CFG_UPDATE1, 0),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
+ 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, CLK_CFG_UPDATE1, 1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi0_parents,
+ 0x0c0, 0x0c4, 0x0c8, 16, 3, 23, CLK_CFG_UPDATE1, 2),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents,
+ 0x0c0, 0x0c4, 0x0c8, 24, 3, 31, CLK_CFG_UPDATE1, 3),
+ /* CLK_CFG_9 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
+ 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, CLK_CFG_UPDATE1, 4),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
+ 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, CLK_CFG_UPDATE1, 5),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", ecc_parents,
+ 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, CLK_CFG_UPDATE1, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
+ 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, CLK_CFG_UPDATE1, 7),
+ /* CLK_CFG_10 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents,
+ 0x0e0, 0x0e4, 0x0e8, 0, 3, 7, CLK_CFG_UPDATE1, 8),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_CPM_SEL, "gcpu_cpm_sel", gcpu_cpm_parents,
+ 0x0e0, 0x0e4, 0x0e8, 8, 2, 15, CLK_CFG_UPDATE1, 9),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_SEL, "apu_sel", apu_parents,
+ 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, CLK_CFG_UPDATE1, 10),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_IF_SEL, "apu_if_sel", apu_parents,
+ 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, CLK_CFG_UPDATE1, 11),
+};
+
+static const char * const mcu_bus_parents[] = {
+ "clk26m_ck",
+ "armpll",
+ "mainpll",
+ "univpll_d2"
+};
+
+static struct mtk_composite mcu_muxes[] = {
+ /* bus_pll_divider_cfg */
+ MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
+ 9, 2, -1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
+};
+
+#define DIV_ADJ_F(_id, _name, _parent, _reg, _shift, _width, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .div_reg = _reg, \
+ .div_shift = _shift, \
+ .div_width = _width, \
+ .clk_divider_flags = _flags, \
+}
+
+static const struct mtk_clk_divider top_adj_divs[] = {
+ DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "apll_i2s0_sel",
+ 0x324, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
+ DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "apll_i2s1_sel",
+ 0x324, 8, 8, CLK_DIVIDER_ROUND_CLOSEST),
+ DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "apll_i2s2_sel",
+ 0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
+ DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "apll_i2s3_sel",
+ 0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
+ DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "apll_spdif_sel",
+ 0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
+};
+
+#define DIV_FIXUP(_id, _name, _parent, _reg, _reg_fixup, _shift, _width,\
+ _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .div_reg = _reg, \
+ .div_reg_fixup = _reg_fixup, \
+ .div_shift = _shift, \
+ .div_width = _width, \
+ .clk_divider_flags = _flags, \
+}
+
+static const struct mtk_clk_divider top_fixup_divs[] = {
+ DIV_FIXUP(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "apll_tdmout_sel",
+ 0x328, 0x500, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
+ DIV_FIXUP(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_ck_div4",
+ 0x328, 0x500, 8, 8, CLK_DIVIDER_ROUND_CLOSEST),
+ DIV_FIXUP(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "apll_tdmin_sel",
+ 0x328, 0x500, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
+ DIV_FIXUP(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_ck_div5",
+ 0x328, 0x500, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x104,
+ .sta_ofs = 0x104,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+ .set_ofs = 0x320,
+ .clr_ofs = 0x320,
+ .sta_ofs = 0x320,
+};
+
+#define GATE_TOP0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_TOP0_I(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_TOP1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_TOP1_I(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_TOP2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10),
+ GATE_TOP0(CLK_TOP_CONN_26M, "conn_26m", "clk26m_ck", 11),
+ GATE_TOP0(CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 16),
+ GATE_TOP0(CLK_TOP_DSP_26M, "dsp_26m", "clk26m_ck", 17),
+ /* TOP1 */
+ GATE_TOP1_I(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 8),
+ GATE_TOP1_I(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4",
+ 9),
+ GATE_TOP1_I(CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts",
+ 20),
+ GATE_TOP1_I(CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 21),
+ GATE_TOP1_I(CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", "clk_null", 22),
+ GATE_TOP1_I(CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", "clk_null", 23),
+ /* TOP2 */
+ GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0),
+ GATE_TOP2(CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 1),
+ GATE_TOP2(CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 2),
+ GATE_TOP2(CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 3),
+ GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 4),
+ GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b",
+ 5),
+ GATE_TOP2(CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 6),
+ GATE_TOP2(CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 7),
+ GATE_TOP2(CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 8),
+
+};
+
+static const struct mtk_gate_regs ifr0_cg_regs = {
+ .set_ofs = 0x200,
+ .clr_ofs = 0x200,
+ .sta_ofs = 0x200,
+};
+
+static const struct mtk_gate_regs ifr1_cg_regs = {
+ .set_ofs = 0x74,
+ .clr_ofs = 0x74,
+ .sta_ofs = 0x74,
+};
+
+static const struct mtk_gate_regs ifr2_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs ifr3_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs ifr4_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs ifr5_cg_regs = {
+ .set_ofs = 0xc0,
+ .clr_ofs = 0xc4,
+ .sta_ofs = 0xc8,
+};
+
+static const struct mtk_gate_regs ifr6_cg_regs = {
+ .set_ofs = 0xd0,
+ .clr_ofs = 0xd4,
+ .sta_ofs = 0xd8,
+};
+
+#define GATE_IFR0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifr0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_IFR1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifr1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_IFR2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifr2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFR3(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifr3_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFR4(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifr4_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFR5(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifr5_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IFR6(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ifr6_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate ifr_clks[] = {
+ /* IFR2 */
+ GATE_IFR2(CLK_IFR_PMIC_TMR, "ifr_pmic_tmr", "clk26m_ck", 0),
+ GATE_IFR2(CLK_IFR_PMIC_AP, "ifr_pmic_ap", "clk26m_ck", 1),
+ GATE_IFR2(CLK_IFR_PMIC_MD, "ifr_pmic_md", "clk26m_ck", 2),
+ GATE_IFR2(CLK_IFR_PMIC_CONN, "ifr_pmic_conn", "clk26m_ck", 3),
+ GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_sel", 8),
+ GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_sel", 9),
+ GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_sel", 10),
+ GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_sel", 15),
+ GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "pwm_sel", 16),
+ GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "pwm_sel", 17),
+ GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "pwm_sel", 18),
+ GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "pwm_sel", 19),
+ GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "pwm_sel", 20),
+ GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "pwm_sel", 21),
+ GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "uart_sel", 22),
+ GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "uart_sel", 23),
+ GATE_IFR2(CLK_IFR_UART2, "ifr_uart2", "uart_sel", 24),
+ GATE_IFR2(CLK_IFR_DSP_UART, "ifr_dsp_uart", "uart_sel", 26),
+ GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "clk26m_ck", 27),
+ GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_cq_dma_fpc", "axi_sel", 28),
+ GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_sel", 31),
+ /* IFR3 */
+ GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_sel", 1),
+ GATE_IFR3(CLK_IFR_MSDC0_HCLK, "ifr_msdc0", "msdc50_0_hc_sel", 2),
+ GATE_IFR3(CLK_IFR_MSDC2_HCLK, "ifr_msdc2", "msdc2_2_hc_sel", 3),
+ GATE_IFR3(CLK_IFR_MSDC1_HCLK, "ifr_msdc1", "axi_sel", 4),
+ GATE_IFR3(CLK_IFR_DVFSRC, "ifr_dvfsrc", "clk26m_ck", 7),
+ GATE_IFR3(CLK_IFR_GCPU, "ifr_gcpu", "axi_sel", 8),
+ GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_sel", 9),
+ GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "clk26m_ck", 10),
+ GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "clk26m_ck", 14),
+ GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_sel", 18),
+ GATE_IFR3(CLK_IFR_DEBUGSYS, "ifr_debugsys", "axi_sel", 24),
+ GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_sel", 25),
+ /* IFR4 */
+ GATE_IFR4(CLK_IFR_PWM_FBCLK6, "ifr_pwm_fbclk6", "pwm_sel", 0),
+ GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "disp_pwm_sel", 2),
+ GATE_IFR4(CLK_IFR_AUD_26M_BK, "ifr_aud_26m_bk", "clk26m_ck", 4),
+ GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_sel", 27),
+ /* IFR5 */
+ GATE_IFR5(CLK_IFR_MSDC0_SF, "ifr_msdc0_sf", "msdc50_0_sel", 0),
+ GATE_IFR5(CLK_IFR_MSDC1_SF, "ifr_msdc1_sf", "msdc50_0_sel", 1),
+ GATE_IFR5(CLK_IFR_MSDC2_SF, "ifr_msdc2_sf", "msdc50_0_sel", 2),
+ GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_sel", 7),
+ GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_sel", 8),
+ GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_src", "msdc50_0_sel", 9),
+ GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_src", "msdc30_1_sel", 10),
+ GATE_IFR5(CLK_IFR_MSDC2_SRC, "ifr_msdc2_src", "msdc50_2_sel", 11),
+ GATE_IFR5(CLK_IFR_PWRAP_TMR, "ifr_pwrap_tmr", "clk26m_ck", 12),
+ GATE_IFR5(CLK_IFR_PWRAP_SPI, "ifr_pwrap_spi", "clk26m_ck", 13),
+ GATE_IFR5(CLK_IFR_PWRAP_SYS, "ifr_pwrap_sys", "clk26m_ck", 14),
+ GATE_IFR5(CLK_IFR_IRRX_26M, "ifr_irrx_26m", "clk26m_ck", 22),
+ GATE_IFR5(CLK_IFR_IRRX_32K, "ifr_irrx_32k", "clk32k", 23),
+ GATE_IFR5(CLK_IFR_I2C0_AXI, "ifr_i2c0_axi", "i2c_sel", 24),
+ GATE_IFR5(CLK_IFR_I2C1_AXI, "ifr_i2c1_axi", "i2c_sel", 25),
+ GATE_IFR5(CLK_IFR_I2C2_AXI, "ifr_i2c2_axi", "i2c_sel", 26),
+ GATE_IFR5(CLK_IFR_I2C3_AXI, "ifr_i2c3_axi", "i2c_sel", 27),
+ GATE_IFR5(CLK_IFR_NIC_AXI, "ifr_nic_axi", "axi_sel", 28),
+ GATE_IFR5(CLK_IFR_NIC_SLV_AXI, "ifr_nic_slv_axi", "axi_sel", 29),
+ GATE_IFR5(CLK_IFR_APU_AXI, "ifr_apu_axi", "axi_sel", 30),
+ /* IFR6 */
+ GATE_IFR6(CLK_IFR_NFIECC, "ifr_nfiecc", "nfiecc_sel", 0),
+ GATE_IFR6(CLK_IFR_NFI1X_BK, "ifr_nfi1x_bk", "nfi2x_sel", 1),
+ GATE_IFR6(CLK_IFR_NFIECC_BK, "ifr_nfiecc_bk", "nfi2x_sel", 2),
+ GATE_IFR6(CLK_IFR_NFI_BK, "ifr_nfi_bk", "axi_sel", 3),
+ GATE_IFR6(CLK_IFR_MSDC2_AP_BK, "ifr_msdc2_ap_bk", "axi_sel", 4),
+ GATE_IFR6(CLK_IFR_MSDC2_MD_BK, "ifr_msdc2_md_bk", "axi_sel", 5),
+ GATE_IFR6(CLK_IFR_MSDC2_BK, "ifr_msdc2_bk", "axi_sel", 6),
+ GATE_IFR6(CLK_IFR_SUSB_133_BK, "ifr_susb_133_bk", "axi_sel", 7),
+ GATE_IFR6(CLK_IFR_SUSB_66_BK, "ifr_susb_66_bk", "axi_sel", 8),
+ GATE_IFR6(CLK_IFR_SSUSB_SYS, "ifr_ssusb_sys", "ssusb_sys_sel", 9),
+ GATE_IFR6(CLK_IFR_SSUSB_REF, "ifr_ssusb_ref", "ssusb_sys_sel", 10),
+ GATE_IFR6(CLK_IFR_SSUSB_XHCI, "ifr_ssusb_xhci", "ssusb_xhci_sel", 11),
+
+};
+
+static const struct mtk_gate_regs peri_cg_regs = {
+ .set_ofs = 0x20c,
+ .clr_ofs = 0x20c,
+ .sta_ofs = 0x20c,
+};
+
+#define GATE_PERI(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate peri_clks[] = {
+ GATE_PERI(CLK_PERIAXI, "periaxi", "axi_sel", 31),
+};
+
+#define MT8168_PLL_FMAX (3800UL * MHZ)
+#define MT8168_PLL_FMIN (1500UL * MHZ)
+#define CON0_MT8168_RST_BAR BIT(23)
+
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
+ _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table, \
+ _rst_bar_mask, _pcw_chg_reg) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .flags = _flags, \
+ .rst_bar_mask = _rst_bar_mask, \
+ .fmax = MT8168_PLL_FMAX, \
+ .fmin = MT8168_PLL_FMIN, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = 8, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .tuner_en_reg = _tuner_en_reg, \
+ .tuner_en_bit = _tuner_en_bit, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcw_chg_reg = _pcw_chg_reg, \
+ .div_table = _div_table, \
+ }
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, \
+ _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
+ _pcw_shift, _rst_bar_mask, _pcw_chg_reg) \
+ PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
+ _pcwbits, _pd_reg, _pd_shift, \
+ _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
+ _pcw_reg, _pcw_shift, NULL, _rst_bar_mask, \
+ _pcw_chg_reg) \
+
+static const struct mtk_pll_div_table armpll_div_table[] = {
+ { .div = 0, .freq = MT8168_PLL_FMAX },
+ { .div = 1, .freq = 1500000000 },
+ { .div = 2, .freq = 750000000 },
+ { .div = 3, .freq = 375000000 },
+ { .div = 4, .freq = 182500000 },
+ { } /* sentinel */
+};
+static const struct mtk_pll_div_table mfgpll_div_table[] = {
+ { .div = 0, .freq = MT8168_PLL_FMAX },
+ { .div = 1, .freq = 1600000000 },
+ { .div = 2, .freq = 800000000 },
+ { .div = 3, .freq = 400000000 },
+ { .div = 4, .freq = 200000000 },
+ { } /* sentinel */
+};
+static const struct mtk_pll_div_table dsppll_div_table[] = {
+ { .div = 0, .freq = MT8168_PLL_FMAX },
+ { .div = 1, .freq = 1600000000 },
+ { .div = 2, .freq = 600000000 },
+ { .div = 3, .freq = 400000000 },
+ { .div = 4, .freq = 200000000 },
+ { } /* sentinel */
+};
+
+static const struct mtk_pll_data plls[] = {
+ PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, 0, 22,
+ 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0),
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001,
+ HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0,
+ CON0_MT8168_RST_BAR, 0),
+ PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001,
+ HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0,
+ CON0_MT8168_RST_BAR, 0),
+ PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0218, 0x0224, 0x00000001, 0, 22,
+ 0x021C, 24, 0, 0, 0, 0x021C, 0, mfgpll_div_table, 0, 0),
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22,
+ 0x0354, 24, 0, 0, 0, 0x0354, 0, 0, 0),
+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22,
+ 0x0334, 24, 0, 0, 0, 0x0334, 0, 0, 0),
+ PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32,
+ 0x0320, 24, 0x0040, 0x000C, 0, 0x0324, 0, 0, 0x0320),
+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32,
+ 0x0364, 24, 0x004C, 0x000C, 5, 0x0368, 0, 0, 0x0364),
+ PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22,
+ 0x0378, 24, 0, 0, 0, 0x0378, 0, 0, 0),
+ PLL_B(CLK_APMIXED_DSPPLL, "dsppll", 0x0390, 0x039C, 0x00000001, 0, 22,
+ 0x0394, 24, 0, 0, 0, 0x0394, 0, dsppll_div_table, 0, 0),
+ PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22,
+ 0x03A4, 24, 0, 0, 0, 0x03A4, 0, 0, 0),
+};
+
+static const struct mtk_fixed_factor top_early_divs[] = {
+ FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", "clk26m", 1, 2),
+};
+
+static struct clk_onecell_data *top_clk_data;
+
+static void clk_mt8168_top_init_early(struct device_node *node)
+{
+ int r, i;
+
+ if (!top_clk_data) {
+ top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+ for (i = 0; i < CLK_TOP_NR_CLK; i++)
+ top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
+ }
+
+ mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
+ top_clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+
+CLK_OF_DECLARE_DRIVER(mt8168_topckgen, "mediatek,mt8168-topckgen",
+ clk_mt8168_top_init_early);
+
+static int clk_mt8168_top_probe(struct platform_device *pdev)
+{
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+ void __iomem *base;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base)) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return PTR_ERR(base);
+ }
+
+ if (!top_clk_data)
+ top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ top_clk_data);
+ mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
+ top_clk_data);
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
+ mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
+ node, &mt8168_clk_lock, top_clk_data);
+ mtk_clk_register_composites(top_misc_muxes, ARRAY_SIZE(top_misc_muxes),
+ base, &mt8168_clk_lock, top_clk_data);
+ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
+ &mt8168_clk_lock, top_clk_data);
+ mtk_clk_register_fixup_dividers(top_fixup_divs,
+ ARRAY_SIZE(top_fixup_divs), base,
+ &mt8168_clk_lock, top_clk_data);
+ mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+ top_clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static int clk_mt8168_infra_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
+
+ mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static int clk_mt8168_peri_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+ mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static int clk_mt8168_apmixed_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+ void __iomem *base;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base)) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return PTR_ERR(base);
+ }
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static int clk_mt8168_mcu_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+ void __iomem *base;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base)) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return PTR_ERR(base);
+ }
+
+ clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
+
+ mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes),
+ base, &mt8168_clk_lock, clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt8168[] = {
+ {
+ .compatible = "mediatek,mt8168-apmixedsys",
+ .data = clk_mt8168_apmixed_probe,
+ }, {
+ .compatible = "mediatek,mt8168-topckgen",
+ .data = clk_mt8168_top_probe,
+ }, {
+ .compatible = "mediatek,mt8168-infracfg",
+ .data = clk_mt8168_infra_probe,
+ }, {
+ .compatible = "mediatek,mt8168-pericfg",
+ .data = clk_mt8168_peri_probe,
+ }, {
+ .compatible = "mediatek,mt8168-mcucfg",
+ .data = clk_mt8168_mcu_probe,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt8168_probe(struct platform_device *pdev)
+{
+ int (*clk_probe)(struct platform_device *p);
+ int r;
+
+ clk_probe = of_device_get_match_data(&pdev->dev);
+ if (!clk_probe)
+ return -EINVAL;
+
+ r = clk_probe(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt8168_drv = {
+ .probe = clk_mt8168_probe,
+ .driver = {
+ .name = "clk-mt8168",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_clk_mt8168,
+ },
+};
+
+static int __init clk_mt8168_init(void)
+{
+ return platform_driver_register(&clk_mt8168_drv);
+}
+
+arch_initcall(clk_mt8168_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8173.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8173.c
new file mode 100644
index 0000000..96c292c
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mt8173.c
@@ -0,0 +1,1221 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+#include "clk-cpumux.h"
+
+#include <dt-bindings/clock/mt8173-clk.h>
+
+/*
+ * For some clocks, we don't care what their actual rates are. And these
+ * clocks may change their rate on different products or different scenarios.
+ * So we model these clocks' rate as 0, to denote it's not an actual rate.
+ */
+#define DUMMY_RATE 0
+
+static DEFINE_SPINLOCK(mt8173_clk_lock);
+
+static const struct mtk_fixed_clk fixed_clks[] __initconst = {
+ FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE),
+ FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
+ FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE),
+ FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE),
+ FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", DUMMY_RATE),
+ FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE),
+};
+
+static const struct mtk_fixed_factor top_divs[] __initconst = {
+ FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),
+ FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),
+
+ FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
+ FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
+ FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5),
+ FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7),
+
+ FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
+ FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
+
+ FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2),
+ FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3),
+ FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5),
+ FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7),
+ FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26),
+
+ FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
+ FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
+ FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
+
+ FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
+ FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),
+
+ FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1),
+ FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1),
+
+ FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
+ FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
+
+ FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),
+ FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
+ FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
+ FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
+ FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16),
+
+ FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
+ FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
+ FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
+
+ FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
+ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
+
+ FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
+ FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
+ FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1),
+ FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
+ FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
+
+ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1),
+ FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8),
+ FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16),
+ FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1),
+ FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1),
+ FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4),
+ FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1),
+ FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
+ FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4),
+
+ FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
+ FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
+ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),
+ FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
+ FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
+
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2),
+
+ FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
+ FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
+
+ FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
+ FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2),
+ FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4),
+};
+
+static const char * const axi_parents[] __initconst = {
+ "clk26m",
+ "syspll1_d2",
+ "syspll_d5",
+ "syspll1_d4",
+ "univpll_d5",
+ "univpll2_d2",
+ "dmpll_d2",
+ "dmpll_d4"
+};
+
+static const char * const mem_parents[] __initconst = {
+ "clk26m",
+ "dmpll_ck"
+};
+
+static const char * const ddrphycfg_parents[] __initconst = {
+ "clk26m",
+ "syspll1_d8"
+};
+
+static const char * const mm_parents[] __initconst = {
+ "clk26m",
+ "vencpll_d2",
+ "main_h364m",
+ "syspll1_d2",
+ "syspll_d5",
+ "syspll1_d4",
+ "univpll1_d2",
+ "univpll2_d2",
+ "dmpll_d2"
+};
+
+static const char * const pwm_parents[] __initconst = {
+ "clk26m",
+ "univpll2_d4",
+ "univpll3_d2",
+ "univpll1_d4"
+};
+
+static const char * const vdec_parents[] __initconst = {
+ "clk26m",
+ "vcodecpll_ck",
+ "tvdpll_445p5m",
+ "univpll_d3",
+ "vencpll_d2",
+ "syspll_d3",
+ "univpll1_d2",
+ "mmpll_d2",
+ "dmpll_d2",
+ "dmpll_d4"
+};
+
+static const char * const venc_parents[] __initconst = {
+ "clk26m",
+ "vcodecpll_ck",
+ "tvdpll_445p5m",
+ "univpll_d3",
+ "vencpll_d2",
+ "syspll_d3",
+ "univpll1_d2",
+ "univpll2_d2",
+ "dmpll_d2",
+ "dmpll_d4"
+};
+
+static const char * const mfg_parents[] __initconst = {
+ "clk26m",
+ "mmpll_ck",
+ "dmpll_ck",
+ "clk26m",
+ "clk26m",
+ "clk26m",
+ "clk26m",
+ "clk26m",
+ "clk26m",
+ "syspll_d3",
+ "syspll1_d2",
+ "syspll_d5",
+ "univpll_d3",
+ "univpll1_d2",
+ "univpll_d5",
+ "univpll2_d2"
+};
+
+static const char * const camtg_parents[] __initconst = {
+ "clk26m",
+ "univpll_d26",
+ "univpll2_d2",
+ "syspll3_d2",
+ "syspll3_d4",
+ "univpll1_d4"
+};
+
+static const char * const uart_parents[] __initconst = {
+ "clk26m",
+ "univpll2_d8"
+};
+
+static const char * const spi_parents[] __initconst = {
+ "clk26m",
+ "syspll3_d2",
+ "syspll1_d4",
+ "syspll4_d2",
+ "univpll3_d2",
+ "univpll2_d4",
+ "univpll1_d8"
+};
+
+static const char * const usb20_parents[] __initconst = {
+ "clk26m",
+ "univpll1_d8",
+ "univpll3_d4"
+};
+
+static const char * const usb30_parents[] __initconst = {
+ "clk26m",
+ "univpll3_d2",
+ "usb_syspll_125m",
+ "univpll2_d4"
+};
+
+static const char * const msdc50_0_h_parents[] __initconst = {
+ "clk26m",
+ "syspll1_d2",
+ "syspll2_d2",
+ "syspll4_d2",
+ "univpll_d5",
+ "univpll1_d4"
+};
+
+static const char * const msdc50_0_parents[] __initconst = {
+ "clk26m",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "univpll1_d4",
+ "syspll2_d2",
+ "syspll_d7",
+ "msdcpll_d4",
+ "vencpll_d4",
+ "tvdpll_ck",
+ "univpll_d2",
+ "univpll1_d2",
+ "mmpll_ck",
+ "msdcpll2_ck",
+ "msdcpll2_d2",
+ "msdcpll2_d4"
+};
+
+static const char * const msdc30_1_parents[] __initconst = {
+ "clk26m",
+ "univpll2_d2",
+ "msdcpll_d4",
+ "univpll1_d4",
+ "syspll2_d2",
+ "syspll_d7",
+ "univpll_d7",
+ "vencpll_d4"
+};
+
+static const char * const msdc30_2_parents[] __initconst = {
+ "clk26m",
+ "univpll2_d2",
+ "msdcpll_d4",
+ "univpll1_d4",
+ "syspll2_d2",
+ "syspll_d7",
+ "univpll_d7",
+ "vencpll_d2"
+};
+
+static const char * const msdc30_3_parents[] __initconst = {
+ "clk26m",
+ "msdcpll2_ck",
+ "msdcpll2_d2",
+ "univpll2_d2",
+ "msdcpll2_d4",
+ "msdcpll_d4",
+ "univpll1_d4",
+ "syspll2_d2",
+ "syspll_d7",
+ "univpll_d7",
+ "vencpll_d4",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "msdcpll_d4"
+};
+
+static const char * const audio_parents[] __initconst = {
+ "clk26m",
+ "syspll3_d4",
+ "syspll4_d4",
+ "syspll1_d16"
+};
+
+static const char * const aud_intbus_parents[] __initconst = {
+ "clk26m",
+ "syspll1_d4",
+ "syspll4_d2",
+ "univpll3_d2",
+ "univpll2_d8",
+ "dmpll_d4",
+ "dmpll_d8"
+};
+
+static const char * const pmicspi_parents[] __initconst = {
+ "clk26m",
+ "syspll1_d8",
+ "syspll3_d4",
+ "syspll1_d16",
+ "univpll3_d4",
+ "univpll_d26",
+ "dmpll_d8",
+ "dmpll_d16"
+};
+
+static const char * const scp_parents[] __initconst = {
+ "clk26m",
+ "syspll1_d2",
+ "univpll_d5",
+ "syspll_d5",
+ "dmpll_d2",
+ "dmpll_d4"
+};
+
+static const char * const atb_parents[] __initconst = {
+ "clk26m",
+ "syspll1_d2",
+ "univpll_d5",
+ "dmpll_d2"
+};
+
+static const char * const venc_lt_parents[] __initconst = {
+ "clk26m",
+ "univpll_d3",
+ "vcodecpll_ck",
+ "tvdpll_445p5m",
+ "vencpll_d2",
+ "syspll_d3",
+ "univpll1_d2",
+ "univpll2_d2",
+ "syspll1_d2",
+ "univpll_d5",
+ "vcodecpll_370p5",
+ "dmpll_ck"
+};
+
+static const char * const dpi0_parents[] __initconst = {
+ "clk26m",
+ "tvdpll_d2",
+ "tvdpll_d4",
+ "clk26m",
+ "clk26m",
+ "tvdpll_d8",
+ "tvdpll_d16"
+};
+
+static const char * const irda_parents[] __initconst = {
+ "clk26m",
+ "univpll2_d4",
+ "syspll2_d4"
+};
+
+static const char * const cci400_parents[] __initconst = {
+ "clk26m",
+ "vencpll_ck",
+ "armca7pll_754m",
+ "armca7pll_502m",
+ "univpll_d2",
+ "syspll_d2",
+ "msdcpll_ck",
+ "dmpll_ck"
+};
+
+static const char * const aud_1_parents[] __initconst = {
+ "clk26m",
+ "apll1_ck",
+ "univpll2_d4",
+ "univpll2_d8"
+};
+
+static const char * const aud_2_parents[] __initconst = {
+ "clk26m",
+ "apll2_ck",
+ "univpll2_d4",
+ "univpll2_d8"
+};
+
+static const char * const mem_mfg_in_parents[] __initconst = {
+ "clk26m",
+ "mmpll_ck",
+ "dmpll_ck",
+ "clk26m"
+};
+
+static const char * const axi_mfg_in_parents[] __initconst = {
+ "clk26m",
+ "axi_sel",
+ "dmpll_d2"
+};
+
+static const char * const scam_parents[] __initconst = {
+ "clk26m",
+ "syspll3_d2",
+ "univpll2_d4",
+ "dmpll_d4"
+};
+
+static const char * const spinfi_ifr_parents[] __initconst = {
+ "clk26m",
+ "univpll2_d8",
+ "univpll3_d4",
+ "syspll4_d2",
+ "univpll2_d4",
+ "univpll3_d2",
+ "syspll1_d4",
+ "univpll1_d4"
+};
+
+static const char * const hdmi_parents[] __initconst = {
+ "clk26m",
+ "hdmitx_dig_cts",
+ "hdmitxpll_d2",
+ "hdmitxpll_d3"
+};
+
+static const char * const dpilvds_parents[] __initconst = {
+ "clk26m",
+ "lvdspll",
+ "lvdspll_d2",
+ "lvdspll_d4",
+ "lvdspll_d8",
+ "fpc_ck"
+};
+
+static const char * const msdc50_2_h_parents[] __initconst = {
+ "clk26m",
+ "syspll1_d2",
+ "syspll2_d2",
+ "syspll4_d2",
+ "univpll_d5",
+ "univpll1_d4"
+};
+
+static const char * const hdcp_parents[] __initconst = {
+ "clk26m",
+ "syspll4_d2",
+ "syspll3_d4",
+ "univpll2_d4"
+};
+
+static const char * const hdcp_24m_parents[] __initconst = {
+ "clk26m",
+ "univpll_d26",
+ "univpll_d52",
+ "univpll2_d8"
+};
+
+static const char * const rtc_parents[] __initconst = {
+ "clkrtc_int",
+ "clkrtc_ext",
+ "clk26m",
+ "univpll3_d8"
+};
+
+static const char * const i2s0_m_ck_parents[] __initconst = {
+ "apll1_div1",
+ "apll2_div1"
+};
+
+static const char * const i2s1_m_ck_parents[] __initconst = {
+ "apll1_div2",
+ "apll2_div2"
+};
+
+static const char * const i2s2_m_ck_parents[] __initconst = {
+ "apll1_div3",
+ "apll2_div3"
+};
+
+static const char * const i2s3_m_ck_parents[] __initconst = {
+ "apll1_div4",
+ "apll2_div4"
+};
+
+static const char * const i2s3_b_ck_parents[] __initconst = {
+ "apll1_div5",
+ "apll2_div5"
+};
+
+static const char * const ca53_parents[] __initconst = {
+ "clk26m",
+ "armca7pll",
+ "mainpll",
+ "univpll"
+};
+
+static const char * const ca57_parents[] __initconst = {
+ "clk26m",
+ "armca15pll",
+ "mainpll",
+ "univpll"
+};
+
+static const struct mtk_composite cpu_muxes[] __initconst = {
+ MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
+ MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
+};
+
+static const struct mtk_composite top_muxes[] __initconst = {
+ /* CLK_CFG_0 */
+ MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
+ MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1),
+ MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
+ MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
+ /* CLK_CFG_1 */
+ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
+ MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
+ MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
+ MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),
+ /* CLK_CFG_2 */
+ MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),
+ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
+ MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
+ MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),
+ /* CLK_CFG_3 */
+ MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),
+ MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15),
+ MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23),
+ MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31),
+ /* CLK_CFG_4 */
+ MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x0080, 8, 4, 15),
+ MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0080, 16, 2, 23),
+ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31),
+ /* CLK_CFG_5 */
+ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0090, 0, 3, 7 /* 7:5 */),
+ MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
+ MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
+ MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),
+ /* CLK_CFG_6 */
+ /*
+ * The dpi0_sel clock should not propagate rate changes to its parent
+ * clock so the dpi driver can have full control over PLL and divider.
+ */
+ MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7, 0),
+ MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
+ MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
+ /* CLK_CFG_7 */
+ MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
+ MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, 0x00b0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 0x00b0, 16, 2, 23),
+ MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
+ /* CLK_CFG_12 */
+ MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7),
+ MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31),
+ /* CLK_CFG_13 */
+ MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
+ MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, 16, 2, 23),
+ MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2),
+
+ DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
+ DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
+ DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),
+ DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16),
+ DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),
+ DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),
+
+ DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
+ DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
+ DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8),
+ DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16),
+ DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),
+ DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),
+
+ MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1),
+ MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1),
+ MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1),
+ MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1),
+ MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
+};
+
+static const struct mtk_gate_regs infra_cg_regs __initconst = {
+ .set_ofs = 0x0040,
+ .clr_ofs = 0x0044,
+ .sta_ofs = 0x0048,
+};
+
+#define GATE_ICG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate infra_clks[] __initconst = {
+ GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
+ GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
+ GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
+ GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
+ GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
+ GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
+ GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),
+ GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
+ GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18),
+ GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22),
+ GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
+};
+
+static const struct mtk_fixed_factor infra_divs[] __initconst = {
+ FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
+};
+
+static const struct mtk_gate_regs peri0_cg_regs __initconst = {
+ .set_ofs = 0x0008,
+ .clr_ofs = 0x0010,
+ .sta_ofs = 0x0018,
+};
+
+static const struct mtk_gate_regs peri1_cg_regs __initconst = {
+ .set_ofs = 0x000c,
+ .clr_ofs = 0x0014,
+ .sta_ofs = 0x001c,
+};
+
+#define GATE_PERI0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_PERI1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate peri_gates[] __initconst = {
+ /* PERI0 */
+ GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
+ GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
+ GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
+ GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
+ GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
+ GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
+ GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
+ GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
+ GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
+ GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
+ GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10),
+ GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
+ GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
+ GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
+ GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
+ GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
+ GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
+ GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
+ GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
+ GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
+ GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
+ GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
+ GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
+ GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
+ GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
+ GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
+ GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
+ GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
+ GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
+ GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
+ GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30),
+ GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31),
+ /* PERI1 */
+ GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0),
+ GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1),
+ GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2),
+};
+
+static const char * const uart_ck_sel_parents[] __initconst = {
+ "clk26m",
+ "uart_sel",
+};
+
+static const struct mtk_composite peri_clks[] __initconst = {
+ MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
+ MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
+ MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
+ MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
+};
+
+static const struct mtk_gate_regs cg_regs_4_8_0 __initconst = {
+ .set_ofs = 0x0004,
+ .clr_ofs = 0x0008,
+ .sta_ofs = 0x0000,
+};
+
+#define GATE_IMG(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_4_8_0, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate img_clks[] __initconst = {
+ GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0),
+ GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5),
+ GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6),
+ GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "camtg_sel", 7),
+ GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "mm_sel", 8),
+ GATE_IMG(CLK_IMG_CAM_SV, "img_cam_sv", "mm_sel", 9),
+ GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
+};
+
+static const struct mtk_gate_regs mm0_cg_regs __initconst = {
+ .set_ofs = 0x0104,
+ .clr_ofs = 0x0108,
+ .sta_ofs = 0x0100,
+};
+
+static const struct mtk_gate_regs mm1_cg_regs __initconst = {
+ .set_ofs = 0x0114,
+ .clr_ofs = 0x0118,
+ .sta_ofs = 0x0110,
+};
+
+#define GATE_MM0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_MM1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate mm_clks[] __initconst = {
+ /* MM0 */
+ GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
+ GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
+ GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
+ GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
+ GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
+ GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
+ GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
+ GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
+ GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
+ GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
+ GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
+ GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
+ GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
+ GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
+ GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
+ GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
+ GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
+ GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
+ GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
+ GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
+ GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
+ GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
+ GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
+ GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
+ GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
+ GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
+ GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
+ GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
+ GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
+ GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
+ GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
+ /* MM1 */
+ GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
+ GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
+ GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
+ GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
+ GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
+ GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
+ GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
+ GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
+ GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
+ GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
+ GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10),
+ GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
+ GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12),
+ GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13),
+ GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14),
+ GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15),
+ GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16),
+ GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17),
+ GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
+ GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19),
+ GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20),
+};
+
+static const struct mtk_gate_regs vdec0_cg_regs __initconst = {
+ .set_ofs = 0x0000,
+ .clr_ofs = 0x0004,
+ .sta_ofs = 0x0000,
+};
+
+static const struct mtk_gate_regs vdec1_cg_regs __initconst = {
+ .set_ofs = 0x0008,
+ .clr_ofs = 0x000c,
+ .sta_ofs = 0x0008,
+};
+
+#define GATE_VDEC0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vdec0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VDEC1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vdec1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate vdec_clks[] __initconst = {
+ GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
+ GATE_VDEC1(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", 0),
+};
+
+#define GATE_VENC(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_4_8_0, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate venc_clks[] __initconst = {
+ GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0),
+ GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4),
+ GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8),
+ GATE_VENC(CLK_VENC_CKE3, "venc_cke3", "venc_sel", 12),
+};
+
+#define GATE_VENCLT(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_4_8_0, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+static const struct mtk_gate venclt_clks[] __initconst = {
+ GATE_VENCLT(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0),
+ GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
+};
+
+static struct clk_onecell_data *mt8173_top_clk_data __initdata;
+static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
+
+static void __init mtk_clk_enable_critical(void)
+{
+ if (!mt8173_top_clk_data || !mt8173_pll_clk_data)
+ return;
+
+ clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
+ clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA7PLL]);
+ clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]);
+ clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
+ clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]);
+ clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_RTC_SEL]);
+}
+
+static void __init mtk_topckgen_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ void __iomem *base;
+ int r;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return;
+ }
+
+ mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+ mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data);
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
+ &mt8173_clk_lock, clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ mtk_clk_enable_critical();
+}
+CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
+
+static void __init mtk_infrasys_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+
+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+ clk_data);
+ mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+
+ mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ mtk_register_reset_controller(node, 2, 0x30);
+}
+CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
+
+static void __init mtk_pericfg_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ void __iomem *base;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return;
+ }
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+ mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
+ clk_data);
+ mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
+ &mt8173_clk_lock, clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ mtk_register_reset_controller(node, 2, 0);
+}
+CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
+
+struct mtk_clk_usb {
+ int id;
+ const char *name;
+ const char *parent;
+ u32 reg_ofs;
+};
+
+#define APMIXED_USB(_id, _name, _parent, _reg_ofs) { \
+ .id = _id, \
+ .name = _name, \
+ .parent = _parent, \
+ .reg_ofs = _reg_ofs, \
+ }
+
+static const struct mtk_clk_usb apmixed_usb[] __initconst = {
+ APMIXED_USB(CLK_APMIXED_REF2USB_TX, "ref2usb_tx", "clk26m", 0x8),
+};
+
+#define MT8173_PLL_FMAX (3000UL * MHZ)
+
+#define CON0_MT8173_RST_BAR BIT(24)
+
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
+ _pcw_shift, _div_table) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .flags = _flags, \
+ .rst_bar_mask = CON0_MT8173_RST_BAR, \
+ .fmax = MT8173_PLL_FMAX, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .div_table = _div_table, \
+ }
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
+ _pcw_shift) \
+ PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
+ NULL)
+
+static const struct mtk_pll_div_table mmpll_div_table[] = {
+ { .div = 0, .freq = MT8173_PLL_FMAX },
+ { .div = 1, .freq = 1000000000 },
+ { .div = 2, .freq = 702000000 },
+ { .div = 3, .freq = 253500000 },
+ { .div = 4, .freq = 126750000 },
+ { } /* sentinel */
+};
+
+static const struct mtk_pll_data plls[] = {
+ PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
+ PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
+ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
+ PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
+ PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
+ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
+ PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0),
+ PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0),
+ PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
+ PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
+ PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
+ PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
+};
+
+static void __init mtk_apmixedsys_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ void __iomem *base;
+ struct clk *clk;
+ int r, i;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return;
+ }
+
+ mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+ if (!clk_data) {
+ iounmap(base);
+ return;
+ }
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+
+ for (i = 0; i < ARRAY_SIZE(apmixed_usb); i++) {
+ const struct mtk_clk_usb *cku = &apmixed_usb[i];
+
+ clk = mtk_clk_register_ref2usb_tx(cku->name, cku->parent,
+ base + cku->reg_ofs);
+
+ if (IS_ERR(clk)) {
+ pr_err("Failed to register clk %s: %ld\n", cku->name,
+ PTR_ERR(clk));
+ continue;
+ }
+
+ clk_data->clks[cku->id] = clk;
+ }
+
+ clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
+ base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
+ NULL);
+ clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ mtk_clk_enable_critical();
+}
+CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
+ mtk_apmixedsys_init);
+
+static void __init mtk_imgsys_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
+
+ mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
+
+static void __init mtk_mmsys_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+
+ mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_mmsys, "mediatek,mt8173-mmsys", mtk_mmsys_init);
+
+static void __init mtk_vdecsys_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
+
+ mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init);
+
+static void __init mtk_vencsys_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
+
+ mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init);
+
+static void __init mtk_vencltsys_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK);
+
+ mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_vencltsys, "mediatek,mt8173-vencltsys", mtk_vencltsys_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mtk-v1.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mtk-v1.c
new file mode 100755
index 0000000..a35fabc
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mtk-v1.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2020 MediaTek Inc.
+
+ */
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/clkdev.h>
+#include "clk-mtk-v1.h"
+#if !defined(MT_CCF_DEBUG) || !defined(MT_CCF_BRINGUP)
+#define MT_CCF_DEBUG 0
+#define MT_CCF_BRINGUP 0
+#endif
+static DEFINE_SPINLOCK(clk_ops_lock);
+static DEFINE_SPINLOCK(mtcmos_ops_lock);
+spinlock_t *get_mtk_clk_lock(void)
+{
+ return &clk_ops_lock;
+}
+spinlock_t *get_mtk_mtcmos_lock(void)
+{
+ return &mtcmos_ops_lock;
+}
\ No newline at end of file
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mtk-v1.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mtk-v1.h
new file mode 100755
index 0000000..6883762
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mtk-v1.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+#ifndef __DRV_CLK_MTK_H
+#define __DRV_CLK_MTK_H
+/*
+ * This is a private header file. DO NOT include it except clk-*.c.
+ */
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#define CLK_DEBUG 0
+#define DUMMY_REG_TEST 0
+/* #define Bring_Up */
+#ifdef Bring_Up
+#ifdef pr_debug
+#undef pr_debug
+#define pr_debug pr_warn
+#endif
+#define MT_CCF_DEBUG 1
+#define MT_CCF_BRINGUP 0 /* 1: only for bring up */
+#endif /* Bring_Up */
+extern spinlock_t *get_mtk_clk_lock(void);
+extern spinlock_t *get_mtk_mtcmos_lock(void);
+#define mtk_clk_lock(flags) spin_lock_irqsave(get_mtk_clk_lock(), flags)
+#define mtk_clk_unlock(flags) \
+ spin_unlock_irqrestore(get_mtk_clk_lock(), flags)
+#define mtk_mtcmos_lock(flags) spin_lock_irqsave(get_mtk_mtcmos_lock(), flags)
+#define mtk_mtcmos_unlock(flags) \
+ spin_unlock_irqrestore(get_mtk_mtcmos_lock(), flags)
+#define MAX_MUX_GATE_BIT 31
+#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
+#if 0
+struct clk *mtk_clk_register_mux(
+ const char *name,
+ const char **parent_names,
+ u8 num_parents,
+ void __iomem *base_addr,
+ u8 shift,
+ u8 width,
+ u8 gate_bit);
+#endif
+#endif /* __DRV_CLK_MTK_H */
\ No newline at end of file
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mtk.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mtk.c
new file mode 100644
index 0000000..61d713a
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mtk.c
@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/clkdev.h>
+#include <linux/mfd/syscon.h>
+#include "clk-mtk.h"
+#include "clk-gate.h"
+struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
+{
+ int i;
+ struct clk_onecell_data *clk_data;
+ clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ if (!clk_data)
+ return NULL;
+ clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL);
+ if (!clk_data->clks)
+ goto err_out;
+ clk_data->clk_num = clk_num;
+ for (i = 0; i < clk_num; i++)
+ clk_data->clks[i] = ERR_PTR(-ENOENT);
+ return clk_data;
+err_out:
+ kfree(clk_data);
+ return NULL;
+}
+void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
+ int num, struct clk_onecell_data *clk_data)
+{
+ int i;
+ struct clk *clk;
+ for (i = 0; i < num; i++) {
+ const struct mtk_fixed_clk *rc = &clks[i];
+ if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[rc->id]))
+ continue;
+ clk = clk_register_fixed_rate(NULL, rc->name, rc->parent, 0,
+ rc->rate);
+ if (IS_ERR(clk)) {
+ pr_err("Failed to register clk %s: %ld\n",
+ rc->name, PTR_ERR(clk));
+ continue;
+ }
+ if (clk_data)
+ clk_data->clks[rc->id] = clk;
+ }
+}
+void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
+ int num, struct clk_onecell_data *clk_data)
+{
+ int i;
+ struct clk *clk;
+ for (i = 0; i < num; i++) {
+ const struct mtk_fixed_factor *ff = &clks[i];
+ if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[ff->id]))
+ continue;
+ clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name,
+ CLK_SET_RATE_PARENT, ff->mult, ff->div);
+ if (IS_ERR(clk)) {
+ pr_err("Failed to register clk %s: %ld\n",
+ ff->name, PTR_ERR(clk));
+ continue;
+ }
+ if (clk_data)
+ clk_data->clks[ff->id] = clk;
+ }
+}
+#if defined(CONFIG_MACH_MT6739)
+void __init mtk_clk_register_factors_pdn(
+ const struct mtk_fixed_factor_pdn *clks,
+ int num, struct clk_onecell_data *clk_data, void __iomem *base)
+{
+ int i;
+ struct clk *clk;
+ for (i = 0; i < num; i++) {
+ const struct mtk_fixed_factor_pdn *ff = &clks[i];
+ clk = mtk_clk_register_fixed_factor_pdn(NULL, ff->name,
+ ff->parent_name,
+ CLK_SET_RATE_PARENT, ff->mult, ff->div,
+ ff->shift, ff->pd_reg, base);
+ if (IS_ERR(clk)) {
+ pr_debug("Failed to register clk %s: %ld\n",
+ ff->name, PTR_ERR(clk));
+ continue;
+ }
+ if (clk_data)
+ clk_data->clks[ff->id] = clk;
+ }
+}
+#endif
+int mtk_clk_register_gates(struct device_node *node,
+ const struct mtk_gate *clks,
+ int num, struct clk_onecell_data *clk_data)
+{
+ int i;
+ struct clk *clk;
+ struct regmap *regmap;
+ struct regmap *pwr_regmap;
+ if (!clk_data)
+ return -ENOMEM;
+ regmap = syscon_node_to_regmap(node);
+ if (IS_ERR(regmap)) {
+ pr_err("Cannot find regmap for %pOF: %ld\n", node,
+ PTR_ERR(regmap));
+ return PTR_ERR(regmap);
+ }
+ pwr_regmap = syscon_regmap_lookup_by_phandle(node, "pwr-regmap");
+ if (IS_ERR(pwr_regmap))
+ pwr_regmap = NULL;
+ for (i = 0; i < num; i++) {
+ const struct mtk_gate *gate = &clks[i];
+ if (!IS_ERR_OR_NULL(clk_data->clks[gate->id]))
+ continue;
+ clk = mtk_clk_register_gate(gate->name, gate->parent_name,
+ regmap,
+ gate->regs->set_ofs,
+ gate->regs->clr_ofs,
+ gate->regs->sta_ofs,
+ gate->shift,
+ gate->ops,
+ gate->flags,
+ gate->pwr_stat,
+ pwr_regmap);
+ if (IS_ERR(clk)) {
+ pr_err("Failed to register clk %s: %ld\n",
+ gate->name, PTR_ERR(clk));
+ continue;
+ }
+ clk_data->clks[gate->id] = clk;
+ }
+ return 0;
+}
+struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
+ void __iomem *base, spinlock_t *lock)
+{
+ struct clk *clk;
+ struct clk_mux *mux = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_divider *div = NULL;
+ struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL;
+ const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL;
+ const char * const *parent_names;
+ const char *parent;
+ int num_parents;
+ int ret;
+ if (mc->mux_shift >= 0) {
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+ mux->reg = base + mc->mux_reg;
+ mux->mask = BIT(mc->mux_width) - 1;
+ mux->shift = mc->mux_shift;
+ mux->lock = lock;
+ mux->flags = mc->mux_flags;
+ mux_hw = &mux->hw;
+ mux_ops = &clk_mux_ops;
+ parent_names = mc->parent_names;
+ num_parents = mc->num_parents;
+ } else {
+ parent = mc->parent;
+ parent_names = &parent;
+ num_parents = 1;
+ }
+ if (mc->gate_shift >= 0) {
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ ret = -ENOMEM;
+ goto err_out;
+ }
+ gate->reg = base + mc->gate_reg;
+ gate->bit_idx = mc->gate_shift;
+ gate->flags = CLK_GATE_SET_TO_DISABLE;
+ gate->lock = lock;
+ gate_hw = &gate->hw;
+ gate_ops = &clk_gate_ops;
+ }
+ if (mc->divider_shift >= 0) {
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div) {
+ ret = -ENOMEM;
+ goto err_out;
+ }
+ div->reg = base + mc->divider_reg;
+ div->shift = mc->divider_shift;
+ div->width = mc->divider_width;
+ div->lock = lock;
+ div_hw = &div->hw;
+ div_ops = &clk_divider_ops;
+ }
+ clk = clk_register_composite(NULL, mc->name, parent_names, num_parents,
+ mux_hw, mux_ops,
+ div_hw, div_ops,
+ gate_hw, gate_ops,
+ mc->flags);
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ goto err_out;
+ }
+ return clk;
+err_out:
+ kfree(div);
+ kfree(gate);
+ kfree(mux);
+ return ERR_PTR(ret);
+}
+void mtk_clk_register_composites(const struct mtk_composite *mcs,
+ int num, void __iomem *base, spinlock_t *lock,
+ struct clk_onecell_data *clk_data)
+{
+ struct clk *clk;
+ int i;
+ for (i = 0; i < num; i++) {
+ const struct mtk_composite *mc = &mcs[i];
+ if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mc->id]))
+ continue;
+ clk = mtk_clk_register_composite(mc, base, lock);
+ if (IS_ERR(clk)) {
+ pr_err("Failed to register clk %s: %ld\n",
+ mc->name, PTR_ERR(clk));
+ continue;
+ }
+ if (clk_data)
+ clk_data->clks[mc->id] = clk;
+ }
+}
+void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
+ int num, void __iomem *base, spinlock_t *lock,
+ struct clk_onecell_data *clk_data)
+{
+ struct clk *clk;
+ int i;
+ for (i = 0; i < num; i++) {
+ const struct mtk_clk_divider *mcd = &mcds[i];
+ if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mcd->id]))
+ continue;
+ clk = clk_register_divider(NULL, mcd->name, mcd->parent_name,
+ mcd->flags, base + mcd->div_reg, mcd->div_shift,
+ mcd->div_width, mcd->clk_divider_flags, lock);
+ if (IS_ERR(clk)) {
+ pr_err("Failed to register clk %s: %ld\n",
+ mcd->name, PTR_ERR(clk));
+ continue;
+ }
+ if (clk_data)
+ clk_data->clks[mcd->id] = clk;
+ }
+}
\ No newline at end of file
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mtk.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mtk.h
new file mode 100644
index 0000000..a0eff8d
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mtk.h
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DRV_CLK_MTK_H
+#define __DRV_CLK_MTK_H
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+struct clk;
+struct clk *mtk_clk_register_fixed_factor_pdn(struct device *dev,
+ const char *name,
+ const char *parent_name, unsigned long flags,
+ unsigned int mult, unsigned int div, unsigned int shift,
+ unsigned int pd_reg, void __iomem *base);
+#define MAX_MUX_GATE_BIT 31
+#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
+#define INVALID_OFS -1
+#define INVALID_SHFT -1
+#define INVALID_WIDTH -1
+#define MHZ (1000 * 1000)
+struct mtk_fixed_clk {
+ int id;
+ const char *name;
+ const char *parent;
+ unsigned long rate;
+};
+#define FIXED_CLK(_id, _name, _parent, _rate) { \
+ .id = _id, \
+ .name = _name, \
+ .parent = _parent, \
+ .rate = _rate, \
+ }
+void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
+ int num, struct clk_onecell_data *clk_data);
+struct mtk_fixed_factor {
+ int id;
+ const char *name;
+ const char *parent_name;
+ int mult;
+ int div;
+};
+struct mtk_fixed_factor_pdn {
+ int id;
+ const char *name;
+ const char *parent_name;
+ int mult;
+ int div;
+ int shift;
+ int pd_reg;
+};
+#define FACTOR(_id, _name, _parent, _mult, _div) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .mult = _mult, \
+ .div = _div, \
+ }
+#define FACTOR_PDN(_id, _name, _parent, _mult, _div, _shift, _pd_reg) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .mult = _mult, \
+ .div = _div, \
+ .shift = _shift, \
+ .pd_reg = _pd_reg, \
+ }
+void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
+ int num, struct clk_onecell_data *clk_data);
+void mtk_clk_register_factors_pdn(const struct mtk_fixed_factor_pdn *clks,
+ int num, struct clk_onecell_data *clk_data, void __iomem *base);
+struct mtk_composite {
+ int id;
+ const char *name;
+ const char * const *parent_names;
+ const char *parent;
+ unsigned long flags;
+ uint32_t mux_reg;
+ uint32_t divider_reg;
+ uint32_t gate_reg;
+ signed char mux_shift;
+ signed char mux_width;
+ signed char gate_shift;
+ signed char divider_shift;
+ signed char divider_width;
+ u8 mux_flags;
+ signed char num_parents;
+};
+#define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \
+ _width, _gate, _flags, _muxflags) { \
+ .id = _id, \
+ .name = _name, \
+ .mux_reg = _reg, \
+ .mux_shift = _shift, \
+ .mux_width = _width, \
+ .gate_reg = _reg, \
+ .gate_shift = _gate, \
+ .divider_shift = -1, \
+ .parent_names = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .flags = _flags, \
+ .mux_flags = _muxflags, \
+ }
+/*
+ * In case the rate change propagation to parent clocks is undesirable,
+ * this macro allows to specify the clock flags manually.
+ */
+#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
+ _gate, _flags) \
+ MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
+ _shift, _width, _gate, _flags, 0)
+/*
+ * Unless necessary, all MUX_GATE clocks propagate rate changes to their
+ * parent clock by default.
+ */
+#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \
+ MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
+ _gate, CLK_SET_RATE_PARENT)
+#define MUX(_id, _name, _parents, _reg, _shift, _width) \
+ MUX_FLAGS(_id, _name, _parents, _reg, \
+ _shift, _width, CLK_SET_RATE_PARENT)
+#define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .mux_reg = _reg, \
+ .mux_shift = _shift, \
+ .mux_width = _width, \
+ .gate_shift = -1, \
+ .divider_shift = -1, \
+ .parent_names = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .flags = _flags, \
+ }
+#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
+ _div_width, _div_shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .name = _name, \
+ .divider_reg = _div_reg, \
+ .divider_shift = _div_shift, \
+ .divider_width = _div_width, \
+ .gate_reg = _gate_reg, \
+ .gate_shift = _gate_shift, \
+ .mux_shift = -1, \
+ .flags = 0, \
+ }
+struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
+ void __iomem *base, spinlock_t *lock);
+void mtk_clk_register_composites(const struct mtk_composite *mcs,
+ int num, void __iomem *base, spinlock_t *lock,
+ struct clk_onecell_data *clk_data);
+struct mtk_gate_regs {
+ u32 sta_ofs;
+ u32 clr_ofs;
+ u32 set_ofs;
+};
+struct mtk_gate {
+ int id;
+ const char *name;
+ const char *parent_name;
+ const struct mtk_gate_regs *regs;
+ int shift;
+ const struct clk_ops *ops;
+ unsigned long flags;
+ struct pwr_status *pwr_stat;
+};
+int mtk_clk_register_gates(struct device_node *node,
+ const struct mtk_gate *clks, int num,
+ struct clk_onecell_data *clk_data);
+struct mtk_clk_divider {
+ int id;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+ u32 div_reg;
+ unsigned char div_shift;
+ unsigned char div_width;
+ unsigned char clk_divider_flags;
+ const struct clk_div_table *clk_div_table;
+};
+#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .div_reg = _reg, \
+ .div_shift = _shift, \
+ .div_width = _width, \
+}
+void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
+ int num, void __iomem *base, spinlock_t *lock,
+ struct clk_onecell_data *clk_data);
+struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
+#define HAVE_RST_BAR BIT(0)
+#define PLL_AO BIT(1)
+#define HAVE_RST_BAR_4_TIMES (BIT(2) | BIT(0))
+struct mtk_pll_div_table {
+ u32 div;
+ unsigned long freq;
+};
+struct mtk_pll_data {
+ int id;
+ const char *name;
+ uint32_t reg;
+ uint32_t pwr_reg;
+ uint32_t en_reg;
+ uint32_t en_mask;
+ uint32_t iso_mask;
+ uint32_t pwron_mask;
+ uint32_t pd_reg;
+ uint32_t tuner_reg;
+ uint32_t tuner_en_reg;
+ uint8_t tuner_en_bit;
+ int pd_shift;
+ unsigned int flags;
+ const struct clk_ops *ops;
+ uint32_t rst_bar_reg;
+ int rst_bar_mask;
+ unsigned long fmin;
+ unsigned long fmax;
+ int pcwbits;
+ int pcwibits;
+ uint32_t pcw_reg;
+ int pcw_shift;
+ uint32_t pcw_chg_reg;
+ const struct mtk_pll_div_table *div_table;
+ const char *parent_name;
+};
+void mtk_clk_register_plls(struct device_node *node,
+ const struct mtk_pll_data *plls, int num_plls,
+ struct clk_onecell_data *clk_data);
+struct clk *mtk_clk_register_ref2usb_tx(const char *name,
+ const char *parent_name, void __iomem *reg);
+extern bool (*mtk_fh_set_rate)(int pll_id, unsigned long dds, int postdiv);
+#ifdef CONFIG_RESET_CONTROLLER
+void mtk_register_reset_controller(struct device_node *np,
+ unsigned int num_regs, int regofs);
+#else
+static inline void mtk_register_reset_controller(struct device_node *np,
+ unsigned int num_regs, int regofs)
+{
+}
+#endif
+#endif /* __DRV_CLK_MTK_H */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mux.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mux.c
new file mode 100644
index 0000000..378c723
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mux.c
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Owen Chen <owen.chen@mediatek.com>
+ */
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/mfd/syscon.h>
+#include "clk-mtk.h"
+#include "clk-mux.h"
+static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
+{
+ return container_of(hw, struct mtk_clk_mux, hw);
+}
+static int mtk_mux_enable(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 mask = BIT(mux->gate_shift);
+ unsigned long flags = 0;
+ int ret = 0;
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+ else
+ __acquire(mux->lock);
+ ret = regmap_update_bits(mux->regmap, mux->mux_ofs, mask, 0);
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ else
+ __release(mux->lock);
+ return ret;
+}
+static void mtk_mux_disable(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 mask = BIT(mux->gate_shift);
+ unsigned long flags = 0;
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+ else
+ __acquire(mux->lock);
+ regmap_update_bits(mux->regmap, mux->mux_ofs, mask, mask);
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ else
+ __release(mux->lock);
+}
+static int mtk_mux_enable_setclr(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 val = 0;
+ unsigned long flags = 0;
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+ else
+ __acquire(mux->lock);
+ val = BIT(mux->gate_shift);
+ regmap_write(mux->regmap, mux->clr_ofs,
+ val);
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ else
+ __release(mux->lock);
+ return 0;
+}
+static void mtk_mux_disable_setclr(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ unsigned long flags = 0;
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+ else
+ __acquire(mux->lock);
+ regmap_write(mux->regmap, mux->set_ofs,
+ BIT(mux->gate_shift));
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ else
+ __release(mux->lock);
+}
+static int mtk_mux_is_enabled(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 val = 0;
+ if (mux->gate_shift < 0)
+ return true;
+ regmap_read(mux->regmap, mux->mux_ofs, &val);
+ return (val & BIT(mux->gate_shift)) == 0;
+}
+static u8 mtk_mux_get_parent(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ int num_parents = clk_hw_get_num_parents(hw);
+ u32 mask = GENMASK(mux->mux_width - 1, 0);
+ u32 val = 0;
+ regmap_read(mux->regmap, mux->mux_ofs, &val);
+ val = (val >> mux->mux_shift) & mask;
+ if (val >= num_parents)
+ return -EINVAL;
+ return val;
+}
+static int mtk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 mask = GENMASK(mux->mux_width - 1, 0)
+ << mux->mux_shift;
+ unsigned long flags = 0;
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+ else
+ __acquire(mux->lock);
+ regmap_update_bits(mux->regmap, mux->mux_ofs, mask,
+ index << mux->mux_shift);
+ if (mux->upd_shift >= 0)
+ regmap_write(mux->regmap, mux->upd_ofs,
+ BIT(mux->upd_shift));
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ else
+ __release(mux->lock);
+ return 0;
+}
+static int mtk_mux_set_parent_setclr(struct clk_hw *hw, u8 index)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 mask = GENMASK(mux->mux_width - 1, 0);
+ u32 val = 0, orig = 0;
+ unsigned long flags = 0;
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+ else
+ __acquire(mux->lock);
+ regmap_read(mux->regmap, mux->mux_ofs, &orig);
+ val = (orig & ~(mask << mux->mux_shift))
+ | (index << mux->mux_shift);
+ if (val != orig) {
+ regmap_write(mux->regmap, mux->clr_ofs,
+ mask << mux->mux_shift);
+ regmap_write(mux->regmap, mux->set_ofs,
+ index << mux->mux_shift);
+ if (mux->upd_shift >= 0)
+ regmap_write(mux->regmap, mux->upd_ofs,
+ BIT(mux->upd_shift));
+ }
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ else
+ __release(mux->lock);
+ return 0;
+}
+const struct clk_ops mtk_mux_ops = {
+ .get_parent = mtk_mux_get_parent,
+ .set_parent = mtk_mux_set_parent,
+};
+const struct clk_ops mtk_mux_clr_set_upd_ops = {
+ .get_parent = mtk_mux_get_parent,
+ .set_parent = mtk_mux_set_parent_setclr,
+};
+const struct clk_ops mtk_mux_gate_ops = {
+ .enable = mtk_mux_enable,
+ .disable = mtk_mux_disable,
+ .is_enabled = mtk_mux_is_enabled,
+ .get_parent = mtk_mux_get_parent,
+ .set_parent = mtk_mux_set_parent,
+};
+const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
+ .enable = mtk_mux_enable_setclr,
+ .disable = mtk_mux_disable_setclr,
+ .is_enabled = mtk_mux_is_enabled,
+ .get_parent = mtk_mux_get_parent,
+ .set_parent = mtk_mux_set_parent_setclr,
+};
+struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
+ struct regmap *regmap,
+ spinlock_t *lock)
+{
+ struct mtk_clk_mux *clk_mux;
+ struct clk_init_data init;
+ struct clk *clk;
+ clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);
+ if (!clk_mux)
+ return ERR_PTR(-ENOMEM);
+ init.name = mux->name;
+ init.flags = (mux->flags) | CLK_SET_RATE_PARENT;
+ init.parent_names = mux->parent_names;
+ init.num_parents = mux->num_parents;
+ init.ops = mux->ops;
+ clk_mux->regmap = regmap;
+ clk_mux->name = mux->name;
+ clk_mux->mux_ofs = mux->mux_ofs;
+ clk_mux->set_ofs = mux->set_ofs;
+ clk_mux->clr_ofs = mux->clr_ofs;
+ clk_mux->upd_ofs = mux->upd_ofs;
+ clk_mux->mux_shift = mux->mux_shift;
+ clk_mux->mux_width = mux->mux_width;
+ clk_mux->gate_shift = mux->gate_shift;
+ clk_mux->upd_shift = mux->upd_shift;
+ clk_mux->lock = lock;
+ clk_mux->hw.init = &init;
+ clk = clk_register(NULL, &clk_mux->hw);
+ if (IS_ERR(clk)) {
+ kfree(clk_mux);
+ return clk;
+ }
+ return clk;
+}
+int mtk_clk_register_muxes(const struct mtk_mux *muxes,
+ int num, struct device_node *node,
+ spinlock_t *lock,
+ struct clk_onecell_data *clk_data)
+{
+ struct regmap *regmap;
+ struct clk *clk;
+ int i;
+ regmap = syscon_node_to_regmap(node);
+ if (IS_ERR(regmap)) {
+ pr_notice("Cannot find regmap for %pOF: %ld\n", node,
+ PTR_ERR(regmap));
+ return PTR_ERR(regmap);
+ }
+ for (i = 0; i < num; i++) {
+ const struct mtk_mux *mux = &muxes[i];
+ if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
+ clk = mtk_clk_register_mux(mux, regmap, lock);
+ if (IS_ERR(clk)) {
+ pr_notice("Failed to register clk %s: %ld\n",
+ mux->name, PTR_ERR(clk));
+ continue;
+ }
+ clk_data->clks[mux->id] = clk;
+ }
+ }
+ return 0;
+}
\ No newline at end of file
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mux.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mux.h
new file mode 100644
index 0000000..229db5e
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-mux.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Owen Chen <owen.chen@mediatek.com>
+ */
+#ifndef __DRV_CLK_MTK_MUX_H
+#define __DRV_CLK_MTK_MUX_H
+#include <linux/clk-provider.h>
+struct mtk_clk_mux {
+ struct clk_hw hw;
+ struct regmap *regmap;
+ const char *name;
+ u32 mux_ofs;
+ u32 set_ofs;
+ u32 clr_ofs;
+ u32 upd_ofs;
+ s8 mux_shift;
+ s8 mux_width;
+ s8 gate_shift;
+ s8 upd_shift;
+ spinlock_t *lock;
+};
+struct mtk_mux {
+ int id;
+ const char *name;
+ const char * const *parent_names;
+ unsigned int flags;
+ u32 mux_ofs;
+ u32 set_ofs;
+ u32 clr_ofs;
+ u32 upd_ofs;
+ s8 mux_shift;
+ s8 mux_width;
+ s8 gate_shift;
+ s8 upd_shift;
+ const struct clk_ops *ops;
+ s8 num_parents;
+};
+extern const struct clk_ops mtk_mux_ops;
+extern const struct clk_ops mtk_mux_clr_set_upd_ops;
+extern const struct clk_ops mtk_mux_gate_ops;
+extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
+#define CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
+ _gate, _upd_ofs, _upd, _flags, _ops) { \
+ .id = _id, \
+ .name = _name, \
+ .mux_ofs = _mux_ofs, \
+ .set_ofs = _mux_set_ofs, \
+ .clr_ofs = _mux_clr_ofs, \
+ .upd_ofs = _upd_ofs, \
+ .mux_shift = _shift, \
+ .mux_width = _width, \
+ .gate_shift = _gate, \
+ .upd_shift = _upd, \
+ .parent_names = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .flags = _flags, \
+ .ops = &_ops, \
+ }
+#define MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
+ _gate, _upd_ofs, _upd, _flags) \
+ CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
+ _gate, _upd_ofs, _upd, _flags, \
+ mtk_mux_gate_clr_set_upd_ops)
+#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
+ _gate, _upd_ofs, _upd) \
+ MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
+ _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
+ _width, _gate, _upd_ofs, _upd, \
+ CLK_SET_RATE_PARENT)
+struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
+ struct regmap *regmap,
+ spinlock_t *lock);
+int mtk_clk_register_muxes(const struct mtk_mux *muxes,
+ int num, struct device_node *node,
+ spinlock_t *lock,
+ struct clk_onecell_data *clk_data);
+#endif /* __DRV_CLK_MTK_MUX_H */
\ No newline at end of file
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-pll.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-pll.c
new file mode 100644
index 0000000..2690b86
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clk-pll.c
@@ -0,0 +1,356 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/clkdev.h>
+#include <linux/delay.h>
+#include "clk-mtk.h"
+#define REG_CON0 0
+#define REG_CON1 4
+#define CON0_BASE_EN BIT(0)
+#define CON0_PWR_ON BIT(0)
+#define CON0_ISO_EN BIT(1)
+#define PCW_CHG_MASK BIT(31)
+#define AUDPLL_TUNER_EN BIT(31)
+#define POSTDIV_MASK 0x7
+#define INTEGER_BITS 7
+/*
+ * MediaTek PLLs are configured through their pcw value. The pcw value describes
+ * a divider in the PLL feedback loop which consists of 7 bits for the integer
+ * part and the remaining bits (if present) for the fractional part. Also they
+ * have a 3 bit power-of-two post divider.
+ */
+struct mtk_clk_pll {
+ struct clk_hw hw;
+ void __iomem *base_addr;
+ void __iomem *pd_addr;
+ void __iomem *pwr_addr;
+ void __iomem *tuner_addr;
+ void __iomem *tuner_en_addr;
+ void __iomem *pcw_addr;
+ void __iomem *pcw_chg_addr;
+ void __iomem *en_addr;
+ void __iomem *rst_bar_addr;
+ const struct mtk_pll_data *data;
+ uint32_t en_mask;
+ uint32_t iso_mask;
+ uint32_t pwron_mask;
+};
+
+bool (*mtk_fh_set_rate)(int pll_id, unsigned long dds, int postdiv) = NULL;
+EXPORT_SYMBOL(mtk_fh_set_rate);
+
+static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
+{
+ return container_of(hw, struct mtk_clk_pll, hw);
+}
+static int mtk_pll_is_prepared(struct clk_hw *hw)
+{
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
+ return (readl(pll->en_addr) & pll->data->en_mask) != 0;
+}
+static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
+ u32 pcw, int postdiv)
+{
+ int pcwbits = pll->data->pcwbits;
+ int pcwfbits;
+ int ibits;
+ u64 vco;
+ u8 c = 0;
+ /* The fractional part of the PLL divider. */
+ ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
+ pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0;
+ vco = (u64)fin * pcw;
+ if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
+ c = 1;
+ vco >>= pcwfbits;
+ if (c)
+ vco++;
+ return ((unsigned long)vco + postdiv - 1) / postdiv;
+}
+static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
+ int postdiv)
+{
+ u32 val, chg;
+ u32 tuner_en = 0;
+ u32 tuner_en_mask;
+ void __iomem *tuner_en_addr = NULL;
+ /* disable tuner */
+ if (pll->tuner_en_addr) {
+ tuner_en_addr = pll->tuner_en_addr;
+ tuner_en_mask = BIT(pll->data->tuner_en_bit);
+ } else if (pll->tuner_addr) {
+ tuner_en_addr = pll->tuner_addr;
+ tuner_en_mask = AUDPLL_TUNER_EN;
+ }
+ if (tuner_en_addr) {
+ val = readl(tuner_en_addr);
+ tuner_en = val & tuner_en_mask;
+ if (tuner_en) {
+ val &= ~tuner_en_mask;
+ writel(val, tuner_en_addr);
+ }
+ }
+ /* set postdiv */
+ val = readl(pll->pd_addr);
+ val &= ~(POSTDIV_MASK << pll->data->pd_shift);
+ val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
+ /* postdiv and pcw need to set at the same time if on same register */
+ if (pll->pd_addr != pll->pcw_addr) {
+ writel(val, pll->pd_addr);
+ val = readl(pll->pcw_addr);
+ }
+ /* set pcw */
+ val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
+ pll->data->pcw_shift);
+ val |= pcw << pll->data->pcw_shift;
+ writel(val, pll->pcw_addr);
+ if (pll->tuner_addr)
+ writel(val + 1, pll->tuner_addr);
+ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
+ writel(chg, pll->pcw_chg_addr);
+ /* restore tuner_en */
+ if (tuner_en_addr && tuner_en) {
+ val = readl(tuner_en_addr);
+ val |= tuner_en_mask;
+ writel(val, tuner_en_addr);
+ }
+ udelay(20);
+}
+/*
+ * mtk_pll_calc_values - calculate good values for a given input frequency.
+ * @pll: The pll
+ * @pcw: The pcw value (output)
+ * @postdiv: The post divider (output)
+ * @freq: The desired target frequency
+ * @fin: The input frequency
+ *
+ */
+static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
+ u32 freq, u32 fin)
+{
+ unsigned long fmin = pll->data->fmin ? pll->data->fmin : 1000 * MHZ;
+ const struct mtk_pll_div_table *div_table = pll->data->div_table;
+ u64 _pcw;
+ int ibits;
+ u32 val;
+ if (freq > pll->data->fmax)
+ freq = pll->data->fmax;
+ if (div_table) {
+ if (freq > div_table[0].freq)
+ freq = div_table[0].freq;
+ for (val = 0; div_table[val + 1].freq != 0; val++) {
+ if (freq > div_table[val + 1].freq)
+ break;
+ }
+ *postdiv = 1 << val;
+ } else {
+ for (val = 0; val < 5; val++) {
+ *postdiv = 1 << val;
+ if ((u64)freq * *postdiv >= fmin)
+ break;
+ }
+ }
+ /* _pcw = freq * postdiv / fin * 2^pcwfbits */
+ ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
+ _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
+ do_div(_pcw, fin);
+ *pcw = (u32)_pcw;
+}
+static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
+ u32 pcw = 0;
+ u32 postdiv;
+ mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
+ if (!mtk_fh_set_rate || !mtk_fh_set_rate(pll->data->id, pcw, postdiv))
+ mtk_pll_set_rate_regs(pll, pcw, postdiv);
+ return 0;
+}
+static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
+ u32 postdiv;
+ u32 pcw;
+ postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
+ postdiv = 1 << postdiv;
+ pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
+ pcw &= GENMASK(pll->data->pcwbits - 1, 0);
+ return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
+}
+static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
+ u32 pcw = 0;
+ int postdiv;
+ mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
+ return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
+}
+static int mtk_pll_prepare(struct clk_hw *hw)
+{
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
+ u32 r;
+ r = readl(pll->pwr_addr) | pll->pwron_mask;
+ writel(r, pll->pwr_addr);
+ udelay(1);
+ r = readl(pll->pwr_addr) & ~pll->iso_mask;
+ writel(r, pll->pwr_addr);
+ udelay(1);
+ r = readl(pll->en_addr) | pll->en_mask;
+ writel(r, pll->en_addr);
+ if (pll->tuner_en_addr) {
+ r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
+ writel(r, pll->tuner_en_addr);
+ } else if (pll->tuner_addr) {
+ r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
+ writel(r, pll->tuner_addr);
+ }
+ udelay(20);
+ if (pll->data->flags & HAVE_RST_BAR) {
+ r = readl(pll->rst_bar_addr);
+ r |= pll->data->rst_bar_mask;
+ writel(r, pll->rst_bar_addr);
+ }
+ return 0;
+}
+static void mtk_pll_unprepare(struct clk_hw *hw)
+{
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
+ u32 r;
+ u32 i;
+ if (pll->data->flags & HAVE_RST_BAR_4_TIMES) {
+ for (i = 0; i < 3; i++) {
+ r = readl(pll->rst_bar_addr);
+ r &= ~pll->data->rst_bar_mask;
+ writel(r, pll->rst_bar_addr);
+ udelay(1);
+ r = readl(pll->rst_bar_addr);
+ r |= pll->data->rst_bar_mask;
+ writel(r, pll->rst_bar_addr);
+ udelay(1);
+ }
+ }
+ if (pll->data->flags & HAVE_RST_BAR) {
+ r = readl(pll->rst_bar_addr);
+ r &= ~pll->data->rst_bar_mask;
+ writel(r, pll->rst_bar_addr);
+ }
+ if (pll->tuner_en_addr) {
+ r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
+ writel(r, pll->tuner_en_addr);
+ } else if (pll->tuner_addr) {
+ r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
+ writel(r, pll->tuner_addr);
+ }
+ r = readl(pll->en_addr) & ~pll->en_mask;
+ writel(r, pll->en_addr);
+ r = readl(pll->pwr_addr) | pll->iso_mask;
+ writel(r, pll->pwr_addr);
+ r = readl(pll->pwr_addr) & ~pll->pwron_mask;
+ writel(r, pll->pwr_addr);
+}
+static const struct clk_ops mtk_pll_ops = {
+ .is_prepared = mtk_pll_is_prepared,
+ .prepare = mtk_pll_prepare,
+ .unprepare = mtk_pll_unprepare,
+ .recalc_rate = mtk_pll_recalc_rate,
+ .round_rate = mtk_pll_round_rate,
+ .set_rate = mtk_pll_set_rate,
+};
+static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
+ void __iomem *base)
+{
+ struct mtk_clk_pll *pll;
+ struct clk_init_data init = {};
+ struct clk *clk;
+ const char *parent_name = "clk26m";
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+ pll->base_addr = base + data->reg;
+ pll->pwr_addr = base + data->pwr_reg;
+ if (data->en_reg)
+ pll->en_addr = base + data->en_reg;
+ else
+ pll->en_addr = pll->base_addr + REG_CON0;
+ pll->pd_addr = base + data->pd_reg;
+ pll->pcw_addr = base + data->pcw_reg;
+ if (data->pcw_chg_reg)
+ pll->pcw_chg_addr = base + data->pcw_chg_reg;
+ else
+ pll->pcw_chg_addr = pll->base_addr + REG_CON1;
+
+ if (data->rst_bar_reg)
+ pll->rst_bar_addr = base + data->rst_bar_reg;
+ else
+ pll->rst_bar_addr = pll->base_addr + REG_CON0;
+ if (data->tuner_reg)
+ pll->tuner_addr = base + data->tuner_reg;
+ if (data->tuner_en_reg)
+ pll->tuner_en_addr = base + data->tuner_en_reg;
+ if (data->en_mask)
+ pll->en_mask = data->en_mask;
+ else
+ pll->en_mask = CON0_BASE_EN;
+ if (data->iso_mask)
+ pll->iso_mask = data->iso_mask;
+ else
+ pll->iso_mask = CON0_ISO_EN;
+ if (data->pwron_mask)
+ pll->pwron_mask = data->pwron_mask;
+ else
+ pll->pwron_mask = CON0_PWR_ON;
+ pll->hw.init = &init;
+ pll->data = data;
+ init.name = data->name;
+ init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
+ init.ops = &mtk_pll_ops;
+ if (data->parent_name)
+ init.parent_names = &data->parent_name;
+ else
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk))
+ kfree(pll);
+ return clk;
+}
+void mtk_clk_register_plls(struct device_node *node,
+ const struct mtk_pll_data *plls, int num_plls,
+ struct clk_onecell_data *clk_data)
+{
+ void __iomem *base;
+ int i;
+ struct clk *clk;
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return;
+ }
+ for (i = 0; i < num_plls; i++) {
+ const struct mtk_pll_data *pll = &plls[i];
+ clk = mtk_clk_register_pll(pll, base);
+ if (IS_ERR(clk)) {
+ pr_err("Failed to register clk %s: %ld\n",
+ pll->name, PTR_ERR(clk));
+ continue;
+ }
+ clk_data->clks[pll->id] = clk;
+ }
+}
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk-mt2712.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk-mt2712.c
new file mode 100644
index 0000000..e4976d5
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk-mt2712.c
@@ -0,0 +1,407 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#include <linux/module.h>
+#include "clkchk.h"
+
+static const char * const off_pll_names[] = {
+ "vcodecpll",
+ "vencpll",
+ "apll1",
+ "apll2",
+ "lvdspll",
+ "lvdspll2",
+ "msdcpll",
+ "msdcpll2",
+ "tvdpll",
+ "mmpll",
+ "armca72pll",
+ "etherpll",
+ NULL
+};
+
+static const char * const all_clk_names[] = {
+ /* plls */
+ "vcodecpll",
+ "vencpll",
+ "apll1",
+ "apll2",
+ "lvdspll",
+ "lvdspll2",
+ "msdcpll",
+ "msdcpll2",
+ "tvdpll",
+ "mmpll",
+ "armca72pll",
+ "etherpll",
+ "cvbspll",
+ /* topckgen */
+ "armca35pll_600m",
+ "armca35pll_400m",
+ "armca72pll_ck",
+ "syspll1_d4",
+ "syspll1_d8",
+ "syspll1_d16",
+ "syspll_d3",
+ "syspll2_d2",
+ "syspll2_d4",
+ "syspll_d5",
+ "syspll3_d2",
+ "syspll3_d4",
+ "syspll_d7",
+ "syspll4_d2",
+ "syspll4_d4",
+ "univpll_d7",
+ "univpll_d26",
+ "univpll_d52",
+ "univpll_d104",
+ "univpll_d208",
+ "univpll1_d2",
+ "univpll1_d4",
+ "univpll1_d8",
+ "univpll_d3",
+ "univpll2_d2",
+ "univpll2_d4",
+ "univpll2_d8",
+ "univpll_d5",
+ "univpll3_d2",
+ "univpll3_d4",
+ "univpll3_d8",
+ "f_mp0_pll1_ck",
+ "f_mp0_pll2_ck",
+ "f_big_pll1_ck",
+ "f_big_pll2_ck",
+ "f_bus_pll1_ck",
+ "f_bus_pll2_ck",
+ "apll1_ck",
+ "apll1_d2",
+ "apll1_d3",
+ "apll1_d4",
+ "apll1_d8",
+ "apll1_d16",
+ "apll2_ck",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8",
+ "apll2_d16",
+ "lvdspll_ck",
+ "lvdspll_d2",
+ "lvdspll_d4",
+ "lvdspll_d8",
+ "lvdspll2_ck",
+ "lvdspll2_d2",
+ "lvdspll2_d4",
+ "lvdspll2_d8",
+ "etherpll_125m",
+ "etherpll_50m",
+ "cvbs",
+ "cvbs_d2",
+ "sys_26m",
+ "mmpll_ck",
+ "mmpll_d2",
+ "vencpll_ck",
+ "vencpll_d2",
+ "vcodecpll_ck",
+ "vcodecpll_d2",
+ "tvdpll_ck",
+ "tvdpll_d2",
+ "tvdpll_d4",
+ "tvdpll_d8",
+ "tvdpll_429m",
+ "tvdpll_429m_d2",
+ "tvdpll_429m_d4",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "msdcpll_d4",
+ "msdcpll2_ck",
+ "msdcpll2_d2",
+ "msdcpll2_d4",
+ "clk26m_d2",
+ "d2a_ulclk_6p5m",
+ "vpll3_dpix",
+ "vpll_dpix",
+ "ltepll_fs26m",
+ "dmpll_ck",
+ "dsi0_lntc",
+ "dsi1_lntc",
+ "lvdstx3",
+ "lvdstx",
+ "clkrtc_ext",
+ "clkrtc_int",
+ "csi0",
+ "apll_div0",
+ "apll_div1",
+ "apll_div2",
+ "apll_div3",
+ "apll_div4",
+ "apll_div5",
+ "apll_div6",
+ "apll_div7",
+ "apll_div_pdn0",
+ "apll_div_pdn1",
+ "apll_div_pdn2",
+ "apll_div_pdn3",
+ "apll_div_pdn4",
+ "apll_div_pdn5",
+ "apll_div_pdn6",
+ "apll_div_pdn7",
+ "nfi2x_en",
+ "nfiecc_en",
+ "nfi1x_ck_en",
+ "mm_sel",
+ "pwm_sel",
+ "vdec_sel",
+ "venc_sel",
+ "mfg_sel",
+ "camtg_sel",
+ "spi_sel",
+ "usb20_sel",
+ "usb30_sel",
+ "msdc50_0_h_sel",
+ "msdc50_0_sel",
+ "msdc30_1_sel",
+ "msdc30_2_sel",
+ "msdc30_3_sel",
+ "audio_sel",
+ "aud_intbus_sel",
+ "pmicspi_sel",
+ "dpilvds1_sel",
+ "atb_sel",
+ "nr_sel",
+ "nfi2x_sel",
+ "irda_sel",
+ "aud_1_sel",
+ "aud_2_sel",
+ "mem_mfg_sel",
+ "axi_mfg_sel",
+ "scam_sel",
+ "nfiecc_sel",
+ "pe2_mac_p0_sel",
+ "pe2_mac_p1_sel",
+ "dpilvds_sel",
+ "msdc50_3_h_sel",
+ "hdcp_sel",
+ "hdcp_24m_sel",
+ "spinor_sel",
+ "apll_sel",
+ "apll2_sel",
+ "a1sys_hp_sel",
+ "a2sys_hp_sel",
+ "asm_l_sel",
+ "asm_m_sel",
+ "asm_h_sel",
+ "i2so1_sel",
+ "i2so2_sel",
+ "i2so3_sel",
+ "tdmo0_sel",
+ "tdmo1_sel",
+ "i2si1_sel",
+ "i2si2_sel",
+ "i2si3_sel",
+ "ether_125m_sel",
+ "ether_50m_sel",
+ "jpgdec_sel",
+ "spislv_sel",
+ "ether_sel",
+ "cam2tg_sel",
+ "di_sel",
+ "tvd_sel",
+ "i2c_sel",
+ "pwm_infra_sel",
+ "msdc0p_aes_sel",
+ "cmsys_sel",
+ "gcpu_sel",
+ "aud_apll1_sel",
+ "aud_apll2_sel",
+ "apll1_ref_sel",
+ "apll2_ref_sel",
+ "audull_vtx_sel",
+ /* bdpsys */
+ "bdp_bridge_b",
+ "bdp_bridge_d",
+ "bdp_larb_d",
+ "bdp_vdi_pxl",
+ "bdp_vdi_d",
+ "bdp_vdi_b",
+ "bdp_fmt_b",
+ "bdp_27m",
+ "bdp_27m_vdout",
+ "bdp_27_74_74",
+ "bdp_2fs",
+ "bdp_2fs74_148",
+ "bdp_b",
+ "bdp_vdo_d",
+ "bdp_vdo_2fs",
+ "bdp_vdo_b",
+ "bdp_di_pxl",
+ "bdp_di_d",
+ "bdp_di_b",
+ "bdp_nr_agent",
+ "bdp_nr_d",
+ "bdp_nr_b",
+ "bdp_bridge_rt_b",
+ "bdp_bridge_rt_d",
+ "bdp_larb_rt_d",
+ "bdp_tvd_tdc",
+ "bdp_tvd_clk_54",
+ "bdp_tvd_cbus",
+ /* infracfg */
+ "infra_dbgclk",
+ "infra_gce",
+ "infra_m4u",
+ "infra_kp",
+ "infra_ao_spi0",
+ "infra_ao_spi1",
+ "infra_ao_uart5",
+ /* imgsys */
+ "img_smi_larb2",
+ "img_scam_en",
+ "img_cam_en",
+ "img_cam_sv_en",
+ "img_cam_sv1_en",
+ "img_cam_sv2_en",
+ /* jpgdecsys */
+ "jpgdec_jpgdec1",
+ "jpgdec_jpgdec",
+ /* mfgcfg */
+ "mfg_bg3d",
+ /* mmsys */
+ "mm_smi_common",
+ "mm_smi_larb0",
+ "mm_cam_mdp",
+ "mm_mdp_rdma0",
+ "mm_mdp_rdma1",
+ "mm_mdp_rsz0",
+ "mm_mdp_rsz1",
+ "mm_mdp_rsz2",
+ "mm_mdp_tdshp0",
+ "mm_mdp_tdshp1",
+ "mm_mdp_crop",
+ "mm_mdp_wdma",
+ "mm_mdp_wrot0",
+ "mm_mdp_wrot1",
+ "mm_fake_eng",
+ "mm_mutex_32k",
+ "mm_disp_ovl0",
+ "mm_disp_ovl1",
+ "mm_disp_rdma0",
+ "mm_disp_rdma1",
+ "mm_disp_rdma2",
+ "mm_disp_wdma0",
+ "mm_disp_wdma1",
+ "mm_disp_color0",
+ "mm_disp_color1",
+ "mm_disp_aal",
+ "mm_disp_gamma",
+ "mm_disp_ufoe",
+ "mm_disp_split0",
+ "mm_disp_od",
+ "mm_pwm0_mm",
+ "mm_pwm0_26m",
+ "mm_pwm1_mm",
+ "mm_pwm1_26m",
+ "mm_dsi0_engine",
+ "mm_dsi0_digital",
+ "mm_dsi1_engine",
+ "mm_dsi1_digital",
+ "mm_dpi_pixel",
+ "mm_dpi_engine",
+ "mm_dpi1_pixel",
+ "mm_dpi1_engine",
+ "mm_lvds_pixel",
+ "mm_lvds_cts",
+ "mm_smi_larb4",
+ "mm_smi_common1",
+ "mm_smi_larb5",
+ "mm_mdp_rdma2",
+ "mm_mdp_tdshp2",
+ "mm_disp_ovl2",
+ "mm_disp_wdma2",
+ "mm_disp_color2",
+ "mm_disp_aal1",
+ "mm_disp_od1",
+ "mm_lvds1_pixel",
+ "mm_lvds1_cts",
+ "mm_smi_larb7",
+ "mm_mdp_rdma3",
+ "mm_mdp_wrot2",
+ "mm_dsi2",
+ "mm_dsi2_digital",
+ "mm_dsi3",
+ "mm_dsi3_digital",
+ /* pericfg */
+ "per_nfi",
+ "per_therm",
+ "per_pwm0",
+ "per_pwm1",
+ "per_pwm2",
+ "per_pwm3",
+ "per_pwm4",
+ "per_pwm5",
+ "per_pwm6",
+ "per_pwm7",
+ "per_pwm",
+ "per_ap_dma",
+ "per_msdc30_0",
+ "per_msdc30_1",
+ "per_msdc30_2",
+ "per_msdc30_3",
+ "per_uart1",
+ "per_uart2",
+ "per_uart3",
+ "per_i2c0",
+ "per_i2c1",
+ "per_i2c2",
+ "per_i2c3",
+ "per_i2c4",
+ "per_auxadc",
+ "per_spi0",
+ "per_spi",
+ "per_i2c5",
+ "per_spi2",
+ "per_spi3",
+ "per_spi5",
+ "per_uart4",
+ "per_sflash",
+ "per_gmac",
+ "per_pcie0",
+ "per_pcie1",
+ "per_gmac_pclk",
+ "per_msdc50_0_en",
+ "per_msdc30_1_en",
+ "per_msdc30_2_en",
+ "per_msdc30_3_en",
+ "per_msdc50_0_h",
+ "per_msdc50_3_h",
+ "per_msdc30_0_q",
+ "per_msdc30_3_q",
+ /* vdecsys */
+ "vdec_cken",
+ "vdec_larb1_cken",
+ "vdec_imgrz_cken",
+ /* vencsys */
+ "venc_smi",
+ "venc_venc",
+ "venc_smi_larb6",
+ /* end */
+ NULL
+};
+
+static const char * const compatible[] = {"mediatek,mt2712", NULL};
+
+static struct clkchk_cfg_t cfg = {
+ .aee_excp_on_fail = false,
+ .warn_on_fail = true,
+ .compatible = compatible,
+ .off_pll_names = off_pll_names,
+ .all_clk_names = all_clk_names,
+};
+
+static int __init clkchk_platform_init(void)
+{
+ return clkchk_init(&cfg);
+}
+subsys_initcall(clkchk_platform_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk-mt6880.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk-mt6880.c
new file mode 100755
index 0000000..480ff9c
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk-mt6880.c
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/syscore_ops.h>
+#include <linux/version.h>
+#include <linux/module.h>
+
+#include "clkchk.h"
+//#include <mt-plat/aee.h>
+#include "clkdbg-mt6880.h"
+
+#define TAG "[clkchk] "
+#define BUG_ON_CHK_ENABLE 0
+
+static const char * const clks[] = {
+ /* topckgen */
+ "axi_sel",
+ "spm_sel",
+ "bus_aximem_sel",
+ "mm_sel",
+ "mfg_ref_sel",
+ "mfg_sel",
+ "uart_sel",
+ "msdc50_0_h_sel",
+ "msdc50_0_sel",
+ "msdc30_1_sel",
+ "audio_sel",
+ "aud_intbus_sel",
+ "aud_engen1_sel",
+ "aud_engen2_sel",
+ "aud_1_sel",
+ "aud_2_sel",
+ "pwrap_ulposc_sel",
+ "atb_sel",
+ "pwrmcu_sel",
+ "dbi_sel",
+ "disp_pwm_sel",
+ "usb_sel",
+ "ssusb_xhci_sel",
+ "i2c_sel",
+ "tl_sel",
+ "dpmaif_main_sel",
+ "pwm_sel",
+ "spmi_m_mst_sel",
+ "spmi_p_mst_sel",
+ "dvfsrc_sel",
+ "mcupm_sel",
+ "sflash_sel",
+ "gcpu_sel",
+ "spi_sel",
+ "spis_sel",
+ "ecc_sel",
+ "nfi1x_sel",
+ "spinfi_bclk_sel",
+ "netsys_sel",
+ "medsys_sel",
+ "hsm_crypto_sel",
+ "hsm_arc_sel",
+ "eip97_sel",
+ "snps_eth_312p5m_sel",
+ "snps_eth_250m_sel",
+ "snps_ptp_sel",
+ "snps_rmii_sel",
+ "netsys_500m_sel",
+ "netsys_med_mcu_sel",
+ "netsys_wed_mcu_sel",
+ "netsys_2x_sel",
+ "sgmii_sel",
+ "sgmii_sbus_sel",
+ "apll_i2s0_mck_sel",
+ "apll_i2s1_mck_sel",
+ "apll_i2s2_mck_sel",
+ "apll_i2s4_mck_sel",
+ "apll_tdmout_mck_sel",
+ "apll_i2s5_mck_sel",
+ "apll_i2s6_mck_sel",
+
+ /* topckgen */
+ "apll12_div0",
+ "apll12_div1",
+ "apll12_div2",
+ "apll12_div4",
+ "apll12_div_tdmout_m",
+ "apll12_div_tdmout_b",
+ "apll12_div5",
+ "apll12_div6",
+
+ /* dbgsys_dem */
+ "dbgsys_dem_atb_en",
+ "dbgsys_dem_busclk_en",
+ "dbgsys_dem_sysclk_en",
+
+ /* infracfg_ao */
+ "ifrao_pmic_tmr_set",
+ "ifrao_pmic_ap_set",
+ "ifrao_pmic_md_set",
+ "ifrao_pmic_conn_set",
+ "ifrao_sej",
+ "ifrao_apxgpt",
+ "ifrao_mcupm",
+ "ifrao_gce",
+ "ifrao_gce2",
+ "ifrao_therm",
+ "ifrao_i2c0",
+ "ifrao_i2c1",
+ "ifrao_i2c2",
+ "ifrao_i2c3",
+ "ifrao_pwm_hclk",
+ "ifrao_pwm1",
+ "ifrao_pwm2",
+ "ifrao_pwm3",
+ "ifrao_pwm4",
+ "ifrao_pwm5",
+ "ifrao_pwm",
+ "ifrao_uart0",
+ "ifrao_uart1",
+ "ifrao_uart2",
+ "ifrao_uart3",
+ "ifrao_gce_26m_set",
+ "ifrao_spi0",
+ "ifrao_msdc0",
+ "ifrao_msdc1",
+ "ifrao_msdc0_clk",
+ "ifrao_gcpu",
+ "ifrao_trng",
+ "ifrao_auxadc",
+ "ifrao_cpum",
+ "ifrao_ccif1_ap",
+ "ifrao_ccif1_md",
+ "ifrao_auxadc_md",
+ "ifrao_pcie_tl_26m",
+ "ifrao_msdc1_clk",
+ "ifrao_pcie_tl_96m",
+ "ifrao_dapc",
+ "ifrao_ccif_ap",
+ "ifrao_debugsys",
+ "ifrao_audio",
+ "ifrao_ccif_md",
+ "ifrao_devmpu_bclk",
+ "ifrao_dramc26",
+ "ifrao_ssusb",
+ "ifrao_disp_pwm",
+ "ifrao_cldmabclk",
+ "ifrao_audio26m",
+ "ifrao_mdtemp",
+ "ifrao_spi1",
+ "ifrao_i2c4",
+ "ifrao_spi2",
+ "ifrao_spi3",
+ "ifrao_unipro_tick",
+ "ifrao_ufs_bclk",
+ "ifrao_md32_bclk",
+ "ifrao_unipro_mbist",
+ "ifrao_pwm6",
+ "ifrao_pwm7",
+ "ifrao_i2c_slave",
+ "ifrao_i2c1a",
+ "ifrao_i2c1_imm",
+ "ifrao_i2c2a",
+ "ifrao_i2c2_imm",
+ "ifrao_ssusb_xhci",
+ "ifrao_msdc0sf",
+ "ifrao_msdc1sf",
+ "ifrao_msdc2sf",
+ "ifrao_sspm_26m",
+ "ifrao_sspm_32k",
+ "ifrao_i2c6",
+ "ifrao_ap_msdc0",
+ "ifrao_md_msdc0",
+ "ifrao_ccif5_ap",
+ "ifrao_ccif5_md",
+ "ifrao_pcie_h_133m",
+ "ifrao_spis_h_66m",
+ "ifrao_pcie_peri_26m",
+ "ifrao_ccif2_ap",
+ "ifrao_ccif2_md",
+ "ifrao_sej_f13m",
+ "ifrao_aes",
+ "ifrao_i2c7",
+ "ifrao_i2c8",
+ "ifrao_fbist2fpc",
+ "ifrao_dpmaif_main",
+ "ifrao_pcie_tl_32k",
+ "ifrao_ccif4_ap",
+ "ifrao_ccif4_md",
+ "ifrao_133m_mclk_ck",
+ "ifrao_66m_mclk_ck",
+ "ifrao_infra_133m",
+ "ifrao_infra_66m",
+ "ifrao_peru_bus_133m",
+ "ifrao_peru_bus_66m",
+ "ifrao_133m_cldma_top",
+ "ifrao_ecc_top",
+ "ifrao_66m_gcpu",
+ "ifrao_133m_dwc_ether",
+ "ifrao_133m_flashif",
+ "ifrao_133m_pcie_p0",
+ "ifrao_133m_pcie_p1",
+ "ifrao_133m_pcie_p2",
+ "ifrao_133m_pcie_p3",
+ "ifrao_mmw_dpmaif_ck",
+ "ifrao_nfi",
+ "ifrao_fpinfi_bclk_ck",
+ "ifrao_66m_nfi_h_ck",
+ "ifrao_fspis_ck",
+ "ifrao_26m_p1",
+ "ifrao_26m_p2",
+ "ifrao_26m_p3",
+ "ifrao_flash_26m",
+ "ifrao_sflash_ck",
+
+ /* apmixedsys */
+ "armpll_ll",
+ "ccipll",
+ "mpll",
+ "mainpll",
+ "univpll",
+ "msdcpll",
+ "mmpll",
+ "mfgpll",
+ "apll1",
+ "apll2",
+ "net1pll",
+ "net2pll",
+ "wedmcupll",
+ "medmcupll",
+ "sgmiipll",
+
+ /* gce */
+ "gce_0",
+
+ /* audiosys */
+ "aud_afe",
+ "aud_22m",
+ "aud_24m",
+ "aud_apll2_tuner",
+ "aud_apll_tuner",
+ "aud_tdm_ck",
+ "aud_adc",
+ "aud_dac",
+ "aud_dac_predis",
+ "aud_tml",
+ "aud_i2s0_bclk",
+ "aud_i2s1_bclk",
+ "aud_i2s2_bclk",
+ "aud_i2s4_bclk",
+ "aud_i2s5_bclk",
+ "aud_i2s6_bclk",
+ "aud_general1_asrc",
+ "aud_general2_asrc",
+ "aud_adda6_adc",
+ "aud_connsys_i2s_asrc",
+ "aud_afe_src_pcm_tx",
+ "aud_afe_src_pcm_tx2",
+ "aud_afe_src_pcm_tx3",
+ "aud_afe_src_pcm_rx",
+ "aud_afe_src_i2sin",
+ "aud_afe_src_i2sout",
+
+ /* imp_iic_wrap_e */
+ "impe_i2c0_ro",
+ "impe_i2c1_ro",
+ "impe_i2c2_ro",
+ "impe_i2c3_ro",
+ "impe_i2c4_ro",
+ "impe_i2c5_ro",
+
+ /* mfgsys */
+ "mfgcfg_bg3d",
+
+ /* mmsys */
+ "mmsys_mutex0",
+ "mmsys_apb_bus",
+ "mm_mdp_rsz0",
+ "mm_disp_gamma0",
+ "mm_mdp_wrot0",
+ "mm_disp_color0",
+ "mm_disp_ccorr0",
+ "mm_disp_aal0",
+ "mm_disp_rdma0",
+ "mm_mdp_rdma0",
+ "mmsys_fake_eng0",
+ "mm_disp_dither0",
+ "mm_disp_wdma0",
+ "mm_mdp_tdshp0",
+ "mm_disp_ovl0",
+ "mm_dbpi0",
+ "mm_disp_dsi0",
+ "mmsys_smi_common",
+ "disp_axi",
+ "dsi",
+ "dbi",
+ NULL
+};
+
+const char * const *get_mt6880_all_clk_names(void)
+{
+ return clks;
+}
+
+static const char * const off_pll_names[] = {
+ "armpll_ll",
+ "ccipll",
+ "mpll",
+ "mainpll",
+ "univpll",
+ "msdcpll",
+ "mmpll",
+ "mfgpll",
+ "apll1",
+ "apll2",
+ "net1pll",
+ "net2pll",
+ "wedmcupll",
+ "medmcupll",
+ "sgmiipll",
+ NULL
+};
+
+static const char * const notice_pll_names[] = {
+ NULL
+};
+
+/*6890 dtsi defined as 6880 too*/
+static const char * const compatible[] = {"mediatek,mt6880", NULL};
+
+static struct clkchk_cfg_t cfg = {
+ .aee_excp_on_fail = false,
+ .warn_on_fail = false,
+ .compatible = compatible,
+ .off_pll_names = off_pll_names,
+ .all_clk_names = clks,
+};
+
+static int __init clkchk_mt6880_init(void)
+{
+ return clkchk_init(&cfg);
+}
+subsys_initcall(clkchk_mt6880_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk-mt6890.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk-mt6890.c
new file mode 100755
index 0000000..504bcde
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk-mt6890.c
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/syscore_ops.h>
+#include <linux/version.h>
+#include <linux/module.h>
+
+#include "clkchk.h"
+//#include <mt-plat/aee.h>
+#include "clkdbg-mt6890.h"
+
+#define TAG "[clkchk] "
+#define BUG_ON_CHK_ENABLE 0
+
+static const char * const clks[] = {
+ /* topckgen */
+ "axi_sel",
+ "spm_sel",
+ "bus_aximem_sel",
+ "mm_sel",
+ "mfg_ref_sel",
+ "mfg_sel",
+ "uart_sel",
+ "msdc50_0_h_sel",
+ "msdc50_0_sel",
+ "msdc30_1_sel",
+ "audio_sel",
+ "aud_intbus_sel",
+ "aud_engen1_sel",
+ "aud_engen2_sel",
+ "aud_1_sel",
+ "aud_2_sel",
+ "pwrap_ulposc_sel",
+ "atb_sel",
+ "pwrmcu_sel",
+ "dbi_sel",
+ "disp_pwm_sel",
+ "usb_sel",
+ "ssusb_xhci_sel",
+ "i2c_sel",
+ "tl_sel",
+ "dpmaif_main_sel",
+ "pwm_sel",
+ "spmi_m_mst_sel",
+ "spmi_p_mst_sel",
+ "dvfsrc_sel",
+ "mcupm_sel",
+ "sflash_sel",
+ "gcpu_sel",
+ "spi_sel",
+ "spis_sel",
+ "ecc_sel",
+ "nfi1x_sel",
+ "spinfi_bclk_sel",
+ "netsys_sel",
+ "medsys_sel",
+ "hsm_crypto_sel",
+ "hsm_arc_sel",
+ "eip97_sel",
+ "snps_eth_312p5m_sel",
+ "snps_eth_250m_sel",
+ "snps_ptp_sel",
+ "snps_rmii_sel",
+ "netsys_500m_sel",
+ "netsys_med_mcu_sel",
+ "netsys_wed_mcu_sel",
+ "netsys_2x_sel",
+ "sgmii_sel",
+ "sgmii_sbus_sel",
+ "apll_i2s0_mck_sel",
+ "apll_i2s1_mck_sel",
+ "apll_i2s2_mck_sel",
+ "apll_i2s4_mck_sel",
+ "apll_tdmout_mck_sel",
+ "apll_i2s5_mck_sel",
+ "apll_i2s6_mck_sel",
+
+ /* topckgen */
+ "apll12_div0",
+ "apll12_div1",
+ "apll12_div2",
+ "apll12_div4",
+ "apll12_div_tdmout_m",
+ "apll12_div_tdmout_b",
+ "apll12_div5",
+ "apll12_div6",
+
+ /* dbgsys_dem */
+ "dbgsys_dem_atb_en",
+ "dbgsys_dem_busclk_en",
+ "dbgsys_dem_sysclk_en",
+
+ /* infracfg_ao */
+ "ifrao_pmic_tmr_set",
+ "ifrao_pmic_ap_set",
+ "ifrao_pmic_md_set",
+ "ifrao_pmic_conn_set",
+ "ifrao_sej",
+ "ifrao_apxgpt",
+ "ifrao_mcupm",
+ "ifrao_gce",
+ "ifrao_gce2",
+ "ifrao_therm",
+ "ifrao_i2c0",
+ "ifrao_i2c1",
+ "ifrao_i2c2",
+ "ifrao_i2c3",
+ "ifrao_pwm_hclk",
+ "ifrao_pwm1",
+ "ifrao_pwm2",
+ "ifrao_pwm3",
+ "ifrao_pwm4",
+ "ifrao_pwm5",
+ "ifrao_pwm",
+ "ifrao_uart0",
+ "ifrao_uart1",
+ "ifrao_uart2",
+ "ifrao_uart3",
+ "ifrao_gce_26m_set",
+ "ifrao_spi0",
+ "ifrao_msdc0",
+ "ifrao_msdc1",
+ "ifrao_msdc0_clk",
+ "ifrao_gcpu",
+ "ifrao_trng",
+ "ifrao_auxadc",
+ "ifrao_cpum",
+ "ifrao_ccif1_ap",
+ "ifrao_ccif1_md",
+ "ifrao_auxadc_md",
+ "ifrao_pcie_tl_26m",
+ "ifrao_msdc1_clk",
+ "ifrao_pcie_tl_96m",
+ "ifrao_dapc",
+ "ifrao_ccif_ap",
+ "ifrao_debugsys",
+ "ifrao_audio",
+ "ifrao_ccif_md",
+ "ifrao_devmpu_bclk",
+ "ifrao_dramc26",
+ "ifrao_ssusb",
+ "ifrao_disp_pwm",
+ "ifrao_cldmabclk",
+ "ifrao_audio26m",
+ "ifrao_mdtemp",
+ "ifrao_spi1",
+ "ifrao_i2c4",
+ "ifrao_spi2",
+ "ifrao_spi3",
+ "ifrao_unipro_tick",
+ "ifrao_ufs_bclk",
+ "ifrao_md32_bclk",
+ "ifrao_unipro_mbist",
+ "ifrao_pwm6",
+ "ifrao_pwm7",
+ "ifrao_i2c_slave",
+ "ifrao_i2c1a",
+ "ifrao_i2c1_imm",
+ "ifrao_i2c2a",
+ "ifrao_i2c2_imm",
+ "ifrao_ssusb_xhci",
+ "ifrao_msdc0sf",
+ "ifrao_msdc1sf",
+ "ifrao_msdc2sf",
+ "ifrao_sspm_26m",
+ "ifrao_sspm_32k",
+ "ifrao_i2c6",
+ "ifrao_ap_msdc0",
+ "ifrao_md_msdc0",
+ "ifrao_ccif5_ap",
+ "ifrao_ccif5_md",
+ "ifrao_pcie_h_133m",
+ "ifrao_spis_h_66m",
+ "ifrao_pcie_peri_26m",
+ "ifrao_ccif2_ap",
+ "ifrao_ccif2_md",
+ "ifrao_sej_f13m",
+ "ifrao_aes",
+ "ifrao_i2c7",
+ "ifrao_i2c8",
+ "ifrao_fbist2fpc",
+ "ifrao_dpmaif_main",
+ "ifrao_pcie_tl_32k",
+ "ifrao_ccif4_ap",
+ "ifrao_ccif4_md",
+ "ifrao_133m_mclk_ck",
+ "ifrao_66m_mclk_ck",
+ "ifrao_infra_133m",
+ "ifrao_infra_66m",
+ "ifrao_peru_bus_133m",
+ "ifrao_peru_bus_66m",
+ "ifrao_133m_cldma_top",
+ "ifrao_ecc_top",
+ "ifrao_66m_gcpu",
+ "ifrao_133m_dwc_ether",
+ "ifrao_133m_flashif",
+ "ifrao_133m_pcie_p0",
+ "ifrao_133m_pcie_p1",
+ "ifrao_133m_pcie_p2",
+ "ifrao_133m_pcie_p3",
+ "ifrao_mmw_dpmaif_ck",
+ "ifrao_nfi",
+ "ifrao_fpinfi_bclk_ck",
+ "ifrao_66m_nfi_h_ck",
+ "ifrao_fspis_ck",
+ "ifrao_26m_p1",
+ "ifrao_26m_p2",
+ "ifrao_26m_p3",
+ "ifrao_flash_26m",
+ "ifrao_sflash_ck",
+
+ /* apmixedsys */
+ "armpll_ll",
+ "ccipll",
+ "mpll",
+ "mainpll",
+ "univpll",
+ "msdcpll",
+ "mmpll",
+ "mfgpll",
+ "apll1",
+ "apll2",
+ "net1pll",
+ "net2pll",
+ "wedmcupll",
+ "medmcupll",
+ "sgmiipll",
+
+ /* gce */
+ "gce_0",
+
+ /* audiosys */
+ "aud_afe",
+ "aud_22m",
+ "aud_24m",
+ "aud_apll2_tuner",
+ "aud_apll_tuner",
+ "aud_tdm_ck",
+ "aud_adc",
+ "aud_dac",
+ "aud_dac_predis",
+ "aud_tml",
+ "aud_i2s0_bclk",
+ "aud_i2s1_bclk",
+ "aud_i2s2_bclk",
+ "aud_i2s4_bclk",
+ "aud_i2s5_bclk",
+ "aud_i2s6_bclk",
+ "aud_general1_asrc",
+ "aud_general2_asrc",
+ "aud_adda6_adc",
+ "aud_connsys_i2s_asrc",
+ "aud_afe_src_pcm_tx",
+ "aud_afe_src_pcm_tx2",
+ "aud_afe_src_pcm_tx3",
+ "aud_afe_src_pcm_rx",
+ "aud_afe_src_i2sin",
+ "aud_afe_src_i2sout",
+
+ /* imp_iic_wrap_e */
+ "impe_i2c0_ro",
+ "impe_i2c1_ro",
+ "impe_i2c2_ro",
+ "impe_i2c3_ro",
+ "impe_i2c4_ro",
+ "impe_i2c5_ro",
+
+ /* mfgsys */
+ "mfgcfg_bg3d",
+
+ /* mmsys */
+ "mmsys_mutex0",
+ "mmsys_apb_bus",
+ "mm_mdp_rsz0",
+ "mm_disp_gamma0",
+ "mm_mdp_wrot0",
+ "mm_disp_color0",
+ "mm_disp_ccorr0",
+ "mm_disp_aal0",
+ "mm_disp_rdma0",
+ "mm_mdp_rdma0",
+ "mmsys_fake_eng0",
+ "mm_disp_dither0",
+ "mm_disp_wdma0",
+ "mm_mdp_tdshp0",
+ "mm_disp_ovl0",
+ "mm_dbpi0",
+ "mm_disp_dsi0",
+ "mmsys_smi_common",
+ "disp_axi",
+ "dsi",
+ "dbi",
+ NULL
+};
+
+const char * const *get_mt6890_all_clk_names(void)
+{
+ return clks;
+}
+
+static const char * const off_pll_names[] = {
+ "armpll_ll",
+ "ccipll",
+ "mpll",
+ "mainpll",
+ "univpll",
+ "msdcpll",
+ "mmpll",
+ "mfgpll",
+ "apll1",
+ "apll2",
+ "net1pll",
+ "net2pll",
+ "wedmcupll",
+ "medmcupll",
+ "sgmiipll",
+ NULL
+};
+
+static const char * const notice_pll_names[] = {
+ NULL
+};
+
+/*6890 dtsi defined as 6880 too*/
+static const char * const compatible[] = {"mediatek,mt6890", NULL};
+
+static struct clkchk_cfg_t cfg = {
+ .aee_excp_on_fail = false,
+ .warn_on_fail = false,
+ .compatible = compatible,
+ .off_pll_names = off_pll_names,
+ .all_clk_names = clks,
+};
+
+static int __init clkchk_mt6890_init(void)
+{
+ return clkchk_init(&cfg);
+}
+subsys_initcall(clkchk_mt6890_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk-mt8168.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk-mt8168.c
new file mode 100644
index 0000000..8973547
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk-mt8168.c
@@ -0,0 +1,435 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/syscore_ops.h>
+#include <linux/version.h>
+#define WARN_ON_CHECK_FAIL 0
+#define CLKDBG_CCF_API_4_4 1
+#define TAG "[clkchk] "
+#define clk_warn(fmt, args...) pr_notice(TAG fmt, ##args)
+#if !CLKDBG_CCF_API_4_4
+/* backward compatible */
+static const char *clk_hw_get_name(const struct clk_hw *hw)
+{
+ return __clk_get_name(hw->clk);
+}
+static bool clk_hw_is_prepared(const struct clk_hw *hw)
+{
+ return __clk_is_prepared(hw->clk);
+}
+static bool clk_hw_is_enabled(const struct clk_hw *hw)
+{
+ return __clk_is_enabled(hw->clk);
+}
+#endif /* !CLKDBG_CCF_API_4_4 */
+
+void print_enabled_clks(void);
+
+static const char * const *get_all_clk_names(void)
+{
+ static const char * const clks[] = {
+ /* PLLs */
+ "univpll",
+ "mfgpll",
+ "msdcpll",
+ "mmpll",
+ "apll1",
+ "apll2",
+ "mpll",
+ "lvdspll",
+ "dsppll",
+ "apupll",
+ /* TOP */
+ "i2s0_bck",
+ "dsi0_lntc_dsick",
+ "vpll_dpix",
+ "lvdstx_dig_cts",
+ "mfgpll_ck",
+ "syspll_d2",
+ "syspll1_d4",
+ "syspll1_d16",
+ "syspll_d3",
+ "syspll2_d2",
+ "syspll2_d4",
+ "syspll2_d8",
+ "syspll_d5",
+ "syspll3_d2",
+ "syspll3_d4",
+ "syspll4_d2",
+ "syspll4_d4",
+ "univpll_d2",
+ "univpll1_d2",
+ "univpll1_d4",
+ "univpll_d3",
+ "univpll2_d2",
+ "univpll2_d4",
+ "univpll2_d8",
+ "univpll2_d32",
+ "univpll_d5",
+ "univpll3_d2",
+ "univpll3_d4",
+ "mmpll_ck",
+ "mmpll_d2",
+ "lvdspll_d2",
+ "lvdspll_d4",
+ "lvdspll_d8",
+ "lvdspll_d16",
+ "usb20_192m_ck",
+ "usb20_192m_d4",
+ "usb20_192m_d8",
+ "usb20_192m_d16",
+ "usb20_192m_d32",
+ "apll1_ck",
+ "apll1_d2",
+ "apll1_d4",
+ "apll1_d8",
+ "apll2_ck",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "dsppll_ck",
+ "dsppll_d2",
+ "dsppll_d4",
+ "dsppll_d8",
+ "apupll_ck",
+ "mpll_d2",
+ "mpll_d4",
+ "clk26m_d52",
+ "mem_sel",
+ "mm_sel",
+ "scp_sel",
+ "mfg_sel",
+ "atb_sel",
+ "camtg_sel",
+ "camtg1_sel",
+ "spi_sel",
+ "msdc50_0_hc_sel",
+ "msdc2_2_hc_sel",
+ "msdc50_0_sel",
+ "msdc50_2_sel",
+ "msdc30_1_sel",
+ "audio_sel",
+ "aud_intbus_sel",
+ "aud_1_sel",
+ "aud_2_sel",
+ "aud_engen1_sel",
+ "aud_engen2_sel",
+ "aud_spdif_sel",
+ "disp_pwm_sel",
+ "ssusb_sys_sel",
+ "ssusb_xhci_sel",
+ "i2c_sel",
+ "pwm_sel",
+ "senif_sel",
+ "aes_fde_sel",
+ "camtm_sel",
+ "dpi0_sel",
+ "dpi1_sel",
+ "dsp_sel",
+ "nfi2x_sel",
+ "nfiecc_sel",
+ "ecc_sel",
+ "eth_sel",
+ "gcpu_sel",
+ "gcpu_cpm_sel",
+ "apu_sel",
+ "apu_if_sel",
+ "mbist_diag_sel",
+ "apll_i2s0_sel",
+ "apll_i2s1_sel",
+ "apll_i2s2_sel",
+ "apll_i2s3_sel",
+ "apll_tdmout_sel",
+ "apll_tdmin_sel",
+ "apll_spdif_sel",
+ "apll12_ck_div0",
+ "apll12_ck_div1",
+ "apll12_ck_div2",
+ "apll12_ck_div3",
+ "apll12_ck_div4",
+ "apll12_ck_div4b",
+ "apll12_ck_div5",
+ "apll12_ck_div5b",
+ "apll12_ck_div6",
+ "aud_i2s0_m_ck",
+ "aud_i2s1_m_ck",
+ "aud_i2s2_m_ck",
+ "aud_i2s3_m_ck",
+ "aud_tdmout_m_ck",
+ "aud_tdmout_b_ck",
+ "aud_tdmin_m_ck",
+ "aud_tdmin_b_ck",
+ "aud_spdif_m_ck",
+ "usb20_48m_en",
+ "univpll_48m_en",
+ "lvdstx_dig_en",
+ "vpll_dpix_en",
+ "ssusb_top_ck_en",
+ "ssusb_phy_ck_en",
+ "conn_32k",
+ "conn_26m",
+ "dsp_32k",
+ "dsp_26m",
+ /* INFRACFG */
+ "ifr_sej",
+ "ifr_apxgpt",
+ "ifr_icusb",
+ "ifr_gce",
+ "ifr_therm",
+ "ifr_pwm_hclk",
+ "ifr_pwm1",
+ "ifr_pwm2",
+ "ifr_pwm3",
+ "ifr_pwm4",
+ "ifr_pwm5",
+ "ifr_pwm",
+ "ifr_uart1",
+ "ifr_gce_26m",
+ "ifr_cq_dma_fpc",
+ "ifr_btif",
+ "ifr_spi0",
+ "ifr_msdc",
+ "ifr_msdc1",
+ "ifr_gcpu",
+ "ifr_trng",
+ "ifr_auxadc",
+ "ifr_auxadc_md",
+ "ifr_ap_dma",
+ "ifr_device_apc",
+ "ifr_audio",
+ "ifr_dramc_f26m",
+ "ifr_pwm_fbclk6",
+ "ifr_disp_pwm",
+ "ifr_aud_26m_bk",
+ "ifr_cq_dma",
+ "ifr_msdc0_sf",
+ "ifr_msdc1_sf",
+ "ifr_msdc2_sf",
+ "ifr_ap_msdc0",
+ "ifr_md_msdc0",
+ "ifr_msdc0_src",
+ "ifr_msdc1_src",
+ "ifr_msdc2_src",
+ "ifr_sej_f13m",
+ "ifr_mcu_pm_bk",
+ "ifr_irrx_26m",
+ "ifr_i2c0_axi",
+ "ifr_i2c1_axi",
+ "ifr_i2c2_axi",
+ "ifr_i2c3_axi",
+ "ifr_nic_axi",
+ "ifr_nic_slv_axi",
+ "ifr_apu_axi",
+ "ifr_nfiecc",
+ "ifr_nfiecc_bk",
+ "ifr_nfi1x_bk",
+ "ifr_nfi_bk",
+ "ifr_msdc2_ap_bk",
+ "ifr_msdc2_md_bk",
+ "ifr_msdc2_bk",
+ "ifr_susb_133_bk",
+ "ifr_susb_66_bk",
+ "ifr_ssusb_sys",
+ "ifr_ssusb_ref",
+ "ifr_ssusb_xhci",
+ /* AUDIO */
+ "aud_afe",
+ "aud_22m",
+ "aud_24m",
+ "aud_apll_tuner",
+ "aud_adc",
+ "aud_dac",
+ "aud_dac_predis",
+ "aud_tml",
+ "aud_i2s1_bclk",
+ "aud_i2s2_bclk",
+ "aud_i2s3_bclk",
+ "aud_i2s4_bclk",
+ /* CAM */
+ "cam_larb2",
+ "cam",
+ "camtg",
+ "cam_senif",
+ "camsv0",
+ "camsv1",
+ "cam_fdvt",
+ "cam_wpe",
+ /* IMG */
+ "img_larb2",
+ "img_dip",
+ "img_fdvt",
+ "img_dpe",
+ "img_rsc",
+ /* MFG */
+ "mfg_bg3d",
+ "mfg_mbist_diag",
+ /* MM */
+ "mm_mdp_rdma0",
+ "mm_mdp_ccorr0",
+ "mm_mdp_rsz0",
+ "mm_mdp_rsz1",
+ "mm_mdp_tdshp0",
+ "mm_mdp_wrot0",
+ "mm_mdp_wdma0",
+ "mm_disp_ovl0",
+ "mm_disp_ovl0_21",
+ "mm_disp_rsz0",
+ "mm_disp_rdma0",
+ "mm_disp_wdma0",
+ "mm_disp_color0",
+ "mm_disp_ccorr0",
+ "mm_disp_aal0",
+ "mm_disp_gamma0",
+ "mm_disp_dither0",
+ "mm_dsi0",
+ "mm_disp_rdma1",
+ "mm_mdp_rdma1",
+ "mm_dpi0_dpi0",
+ "mm_fake",
+ "mm_smi_common",
+ "mm_smi_larb0",
+ "mm_smi_comm0",
+ "mm_smi_comm1",
+ "mm_cam_mdp",
+ "mm_smi_img",
+ "mm_smi_cam",
+ "mm_dl_relay",
+ "mm_dl_async_top",
+ "mm_dsi0_dig_dsi",
+ "mm_f26m_hrtwt",
+ "mm_dpi0",
+ "mm_flvdstx_pxl",
+ "mm_flvdstx_cts",
+ /* VENC */
+ "venc_fvenc_ck",
+ "venc_jpgenc_ck",
+ /* VDEC */
+ "vdec_fvdec_ck",
+ "vdec_flarb1_ck",
+ /* end */
+ NULL
+ };
+ return clks;
+}
+
+static const char *ccf_state(struct clk_hw *hw)
+{
+ if (__clk_get_enable_count(hw->clk))
+ return "enabled";
+ if (clk_hw_is_prepared(hw))
+ return "prepared";
+ return "disabled";
+}
+
+void print_enabled_clks(void)
+{
+ const char * const *cn = get_all_clk_names();
+
+ clk_warn("enabled clks:\n");
+ for (; *cn; cn++) {
+ struct clk *c = __clk_lookup(*cn);
+ struct clk_hw *c_hw = __clk_get_hw(c);
+ struct clk_hw *p_hw;
+
+ if (IS_ERR_OR_NULL(c) || !c_hw)
+ continue;
+ p_hw = clk_hw_get_parent(c_hw);
+ if (!p_hw)
+ continue;
+ if (!clk_hw_is_prepared(c_hw) && !__clk_get_enable_count(c))
+ continue;
+ clk_warn("[%-17s: %8s, %3d, %3d, %10ld, %17s]\n",
+ clk_hw_get_name(c_hw),
+ ccf_state(c_hw),
+ clk_hw_is_prepared(c_hw),
+ __clk_get_enable_count(c),
+ clk_hw_get_rate(c_hw),
+ p_hw ? clk_hw_get_name(p_hw) : "- ");
+ }
+}
+
+static void check_pll_off(void)
+{
+ static const char * const off_pll_names[] = {
+ "univpll",
+ "mfgpll",
+ "apll1",
+ "apll2",
+ "mmpll",
+ "msdcpll",
+ "lvdspll",
+ "dsppll",
+ "apupll",
+ NULL
+ };
+ static struct clk *off_plls[ARRAY_SIZE(off_pll_names)];
+ struct clk **c;
+ int invalid = 0;
+ char buf[128] = {0};
+ int n = 0;
+
+ if (!off_plls[0]) {
+ const char * const *pn;
+
+ for (pn = off_pll_names, c = off_plls; *pn; pn++, c++)
+ *c = __clk_lookup(*pn);
+ }
+ for (c = off_plls; *c; c++) {
+ struct clk_hw *c_hw = __clk_get_hw(*c);
+
+ if (!c_hw)
+ continue;
+ if (!clk_hw_is_enabled(c_hw))
+ continue;
+ n += snprintf(buf + n, sizeof(buf) - n, "%s ",
+ clk_hw_get_name(c_hw));
+ invalid++;
+ }
+ if (invalid) {
+ clk_warn("suspend warning: unexpected unclosed PLL: %s\n", buf);
+ print_enabled_clks();
+#if WARN_ON_CHECK_FAIL
+ WARN_ON(1);
+#endif
+ }
+
+}
+
+void print_enabled_clks_once(void)
+{
+ static bool first_flag = true;
+
+ if (first_flag) {
+ first_flag = false;
+ print_enabled_clks();
+ }
+}
+
+static int clkchk_syscore_suspend(void)
+{
+ check_pll_off();
+ return 0;
+}
+
+static void clkchk_syscore_resume(void)
+{
+}
+
+static struct syscore_ops clkchk_syscore_ops = {
+ .suspend = clkchk_syscore_suspend,
+ .resume = clkchk_syscore_resume,
+};
+
+static int __init clkchk_init(void)
+{
+ if (!of_machine_is_compatible("mediatek,mt8168"))
+ return -ENODEV;
+ register_syscore_ops(&clkchk_syscore_ops);
+ return 0;
+}
+subsys_initcall(clkchk_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk.c
new file mode 100644
index 0000000..cdc1ca4
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#define pr_fmt(fmt) "[clkchk] " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/syscore_ops.h>
+#include "clkchk.h"
+
+#define AEE_EXCP_CHECK_PLL_FAIL 0
+#define CLKDBG_CCF_API_4_4 1
+#define MAX_PLLS 32
+
+#if AEE_EXCP_CHECK_PLL_FAIL
+#include <mt-plat/aee.h>
+#endif
+
+#if !CLKDBG_CCF_API_4_4
+
+/* backward compatible */
+
+static const char *clk_hw_get_name(const struct clk_hw *hw)
+{
+ return __clk_get_name(hw->clk);
+}
+
+static bool clk_hw_is_prepared(const struct clk_hw *hw)
+{
+ return __clk_is_prepared(hw->clk);
+}
+
+static bool clk_hw_is_enabled(const struct clk_hw *hw)
+{
+ return __clk_is_enabled(hw->clk);
+}
+
+static unsigned long clk_hw_get_rate(const struct clk_hw *hw)
+{
+ return __clk_get_rate(hw->clk);
+}
+
+static struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw)
+{
+ return __clk_get_hw(clk_get_parent(hw->clk));
+}
+
+#endif /* !CLKDBG_CCF_API_4_4 */
+
+static struct clkchk_cfg_t *clkchk_cfg;
+
+static const char *ccf_state(struct clk_hw *hw)
+{
+ if (__clk_get_enable_count(hw->clk))
+ return "enabled";
+
+ if (clk_hw_is_prepared(hw))
+ return "prepared";
+
+ return "disabled";
+}
+
+static void print_enabled_clks(void)
+{
+ const char * const *cn = clkchk_cfg->all_clk_names;
+
+ pr_warn("enabled clks:\n");
+
+ for (; *cn != NULL; cn++) {
+ struct clk *c = __clk_lookup(*cn);
+ struct clk_hw *c_hw = __clk_get_hw(c);
+ struct clk_hw *p_hw;
+
+ if (IS_ERR_OR_NULL(c) || c_hw == NULL)
+ continue;
+
+ p_hw = clk_hw_get_parent(c_hw);
+
+ if (p_hw == NULL)
+ continue;
+
+ if (!clk_hw_is_prepared(c_hw) &&
+ __clk_get_enable_count(c) <= 0U)
+ continue;
+
+ pr_warn("[%-17s: %8s, %3d, %3d, %10ld, %17s]\n",
+ clk_hw_get_name(c_hw),
+ ccf_state(c_hw),
+ clk_hw_is_prepared(c_hw),
+ __clk_get_enable_count(c),
+ clk_hw_get_rate(c_hw),
+ p_hw != NULL ? clk_hw_get_name(p_hw) : "- ");
+ }
+}
+
+static void check_pll_off(void)
+{
+ static struct clk *off_plls[MAX_PLLS];
+
+ struct clk **c;
+ int invalid = 0;
+ char buf[128] = {0};
+ int n = 0;
+
+ if (off_plls[0] == NULL) {
+ const char * const *pn = clkchk_cfg->off_pll_names;
+ struct clk **end = off_plls + MAX_PLLS - 1;
+
+ for (c = off_plls; *pn != NULL && c < end; pn++, c++)
+ *c = __clk_lookup(*pn);
+ }
+
+ for (c = off_plls; *c != NULL; c++) {
+ struct clk_hw *c_hw = __clk_get_hw(*c);
+
+ if (c_hw == NULL)
+ continue;
+
+ if (!clk_hw_is_prepared(c_hw) && !clk_hw_is_enabled(c_hw))
+ continue;
+
+ n += snprintf(buf + n, sizeof(buf) - (size_t)n, "%s ",
+ clk_hw_get_name(c_hw));
+
+ invalid++;
+ }
+
+ if (invalid == 0)
+ return;
+
+ /* invalid. output debug info */
+
+ pr_warn("unexpected unclosed PLL: %s\n", buf);
+ print_enabled_clks();
+
+#if AEE_EXCP_CHECK_PLL_FAIL
+ if (clkchk_cfg->aee_excp_on_fail)
+ aee_kernel_exception("clkchk", "unclosed PLL: %s\n", buf);
+#endif
+
+ if (clkchk_cfg->warn_on_fail)
+ WARN_ON(true);
+}
+
+static int clkchk_syscore_suspend(void)
+{
+
+ pr_notice("Enter CLOCK suspend Call Back !!\n");
+ check_pll_off();
+
+ return 0;
+}
+
+static void clkchk_syscore_resume(void)
+{
+ pr_notice("Enter CLOCK resume Call Back !!\n");
+}
+
+static struct syscore_ops clkchk_syscore_ops = {
+ .suspend = clkchk_syscore_suspend,
+ .resume = clkchk_syscore_resume,
+};
+
+int clkchk_init(struct clkchk_cfg_t *cfg)
+{
+ const char * const *c;
+ bool match = false;
+
+ if (cfg == NULL || cfg->compatible == NULL
+ || cfg->all_clk_names == NULL || cfg->off_pll_names == NULL) {
+ pr_warn("Invalid clkchk_cfg.\n");
+ return -EINVAL;
+ }
+
+ clkchk_cfg = cfg;
+
+ for (c = cfg->compatible; *c != NULL; c++) {
+ if (of_machine_is_compatible(*c) != 0) {
+ match = true;
+ break;
+ }
+ }
+
+ if (!match)
+ return -ENODEV;
+
+ register_syscore_ops(&clkchk_syscore_ops);
+
+ return 0;
+}
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk.h
new file mode 100644
index 0000000..c9f1e10
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkchk.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#include <stdbool.h>
+#include <stddef.h>
+
+struct clkchk_cfg_t {
+ bool aee_excp_on_fail;
+ bool warn_on_fail;
+ const char * const *compatible;
+ const char * const *off_pll_names;
+ const char * const *all_clk_names;
+};
+
+int clkchk_init(struct clkchk_cfg_t *cfg);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt2712.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt2712.c
new file mode 100644
index 0000000..685c146
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt2712.c
@@ -0,0 +1,1065 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+
+#include "clkdbg.h"
+
+#define DUMP_INIT_STATE 0
+
+/*
+ * clkdbg dump_regs
+ */
+
+enum {
+ topckgen,
+ infracfg,
+ pericfg,
+ scpsys,
+ apmixed,
+ fhctl,
+ mfgsys,
+ mmsys,
+ imgsys,
+ bdpsys,
+ vdecsys,
+ vencsys,
+ jpgdecsys,
+};
+
+#define REGBASE_V(_phys, _id_name) { .phys = _phys, .name = #_id_name }
+
+/*
+ * checkpatch.pl ERROR:COMPLEX_MACRO
+ *
+ * #define REGBASE(_phys, _id_name) [_id_name] = REGBASE_V(_phys, _id_name)
+ */
+
+static struct regbase rb[] = {
+ [topckgen] = REGBASE_V(0x10000000, topckgen),
+ [infracfg] = REGBASE_V(0x10001000, infracfg),
+ [pericfg] = REGBASE_V(0x10003000, pericfg),
+ [scpsys] = REGBASE_V(0x10006000, scpsys),
+ [apmixed] = REGBASE_V(0x10209000, apmixed),
+ [fhctl] = REGBASE_V(0x10209e00, fhctl),
+ [mfgsys] = REGBASE_V(0x13000000, mfgsys),
+ [mmsys] = REGBASE_V(0x14000000, mmsys),
+ [imgsys] = REGBASE_V(0x15000000, imgsys),
+ [bdpsys] = REGBASE_V(0x15010000, bdpsys),
+ [vdecsys] = REGBASE_V(0x16000000, vdecsys),
+ [vencsys] = REGBASE_V(0x18000000, vencsys),
+ [jpgdecsys] = REGBASE_V(0x19000000, jpgdecsys),
+};
+
+#define REGNAME(_base, _ofs, _name) \
+ { .base = &rb[_base], .ofs = _ofs, .name = #_name }
+
+static struct regname rn[] = {
+ REGNAME(topckgen, 0x040, CLK_CFG_0),
+ REGNAME(topckgen, 0x050, CLK_CFG_1),
+ REGNAME(topckgen, 0x060, CLK_CFG_2),
+ REGNAME(topckgen, 0x070, CLK_CFG_3),
+ REGNAME(topckgen, 0x080, CLK_CFG_4),
+ REGNAME(topckgen, 0x090, CLK_CFG_5),
+ REGNAME(topckgen, 0x0a0, CLK_CFG_6),
+ REGNAME(topckgen, 0x0b0, CLK_CFG_7),
+ REGNAME(topckgen, 0x0c0, CLK_CFG_8),
+ REGNAME(topckgen, 0x0d0, CLK_CFG_9),
+ REGNAME(topckgen, 0x134, CLK_AUDDIV_4),
+ REGNAME(topckgen, 0x500, CLK_CFG_10),
+ REGNAME(topckgen, 0x510, CLK_CFG_11),
+ REGNAME(topckgen, 0x520, CLK_CFG_12),
+ REGNAME(topckgen, 0x530, CLK_CFG_13),
+ REGNAME(topckgen, 0x540, CLK_CFG_14),
+ REGNAME(topckgen, 0x550, CLK_CFG_15),
+ REGNAME(topckgen, 0x560, CLK_CFG_16),
+ REGNAME(topckgen, 0x570, CLK_CFG_17),
+ REGNAME(scpsys, 0x210, SPM_VDE_PWR_CON),
+ REGNAME(scpsys, 0x214, SPM_MFG_PWR_CON),
+ REGNAME(scpsys, 0x230, SPM_VEN_PWR_CON),
+ REGNAME(scpsys, 0x238, SPM_ISP_PWR_CON),
+ REGNAME(scpsys, 0x23c, SPM_DIS_PWR_CON),
+ REGNAME(scpsys, 0x29c, SPM_AUDIO_PWR_CON),
+ REGNAME(scpsys, 0x2cc, SPM_USB_PWR_CON),
+ REGNAME(scpsys, 0x2d4, SPM_USB2_PWR_CON),
+ REGNAME(scpsys, 0x60c, SPM_PWR_STATUS),
+ REGNAME(scpsys, 0x610, SPM_PWR_STATUS_2ND),
+ REGNAME(apmixed, 0x004, AP_PLL_CON1),
+ REGNAME(apmixed, 0x008, AP_PLL_CON2),
+ REGNAME(apmixed, 0x100, ARMCA35PLL_CON0),
+ REGNAME(apmixed, 0x104, ARMCA35PLL_CON1),
+ REGNAME(apmixed, 0x110, ARMCA35PLL_PWR_CON0),
+ REGNAME(apmixed, 0x210, ARMCA72PLL_CON0),
+ REGNAME(apmixed, 0x214, ARMCA72PLL_CON1),
+ REGNAME(apmixed, 0x210, ARMCA72PLL_PWR_CON0),
+ REGNAME(apmixed, 0x230, MAINPLL_CON0),
+ REGNAME(apmixed, 0x234, MAINPLL_CON1),
+ REGNAME(apmixed, 0x23c, MAINPLL_PWR_CON0),
+ REGNAME(apmixed, 0x240, UNIVPLL_CON0),
+ REGNAME(apmixed, 0x244, UNIVPLL_CON1),
+ REGNAME(apmixed, 0x24c, UNIVPLL_PWR_CON0),
+ REGNAME(apmixed, 0x250, MMPLL_CON0),
+ REGNAME(apmixed, 0x254, MMPLL_CON1),
+ REGNAME(apmixed, 0x260, MMPLL_PWR_CON0),
+ REGNAME(apmixed, 0x270, MSDCPLL_CON0),
+ REGNAME(apmixed, 0x274, MSDCPLL_CON1),
+ REGNAME(apmixed, 0x27c, MSDCPLL_PWR_CON0),
+ REGNAME(apmixed, 0x280, VENCPLL_CON0),
+ REGNAME(apmixed, 0x284, VENCPLL_CON1),
+ REGNAME(apmixed, 0x28c, VENCPLL_PWR_CON0),
+ REGNAME(apmixed, 0x290, TVDPLL_CON0),
+ REGNAME(apmixed, 0x294, TVDPLL_CON1),
+ REGNAME(apmixed, 0x29c, TVDPLL_PWR_CON0),
+ REGNAME(apmixed, 0x300, ETHERPLL_CON0),
+ REGNAME(apmixed, 0x304, ETHERPLL_CON1),
+ REGNAME(apmixed, 0x30c, ETHERPLL_PWR_CON0),
+ REGNAME(apmixed, 0x320, VCODECPLL_CON0),
+ REGNAME(apmixed, 0x324, VCODECPLL_CON1),
+ REGNAME(apmixed, 0x32c, VCODECPLL_PWR_CON0),
+ REGNAME(apmixed, 0x330, APLL1_CON0),
+ REGNAME(apmixed, 0x334, APLL1_CON1),
+ REGNAME(apmixed, 0x340, APLL1_PWR_CON0),
+ REGNAME(apmixed, 0x350, APLL2_CON0),
+ REGNAME(apmixed, 0x354, APLL2_CON1),
+ REGNAME(apmixed, 0x360, APLL2_PWR_CON0),
+ REGNAME(apmixed, 0x370, LVDSPLL_CON0),
+ REGNAME(apmixed, 0x374, LVDSPLL_CON1),
+ REGNAME(apmixed, 0x37c, LVDSPLL_PWR_CON0),
+ REGNAME(apmixed, 0x390, LVDSPLL2_CON0),
+ REGNAME(apmixed, 0x394, LVDSPLL2_CON1),
+ REGNAME(apmixed, 0x39c, LVDSPLL2_PWR_CON0),
+ REGNAME(apmixed, 0x410, MSDCPLL2_CON0),
+ REGNAME(apmixed, 0x414, MSDCPLL2_CON1),
+ REGNAME(apmixed, 0x41c, MSDCPLL2_PWR_CON0),
+ REGNAME(topckgen, 0x120, CLK_AUDDIV_0),
+ REGNAME(infracfg, 0x040, INFRA_PDN_STA),
+ REGNAME(pericfg, 0x018, PERI_PDN0_STA),
+ REGNAME(pericfg, 0x01c, PERI_PDN1_STA),
+ REGNAME(pericfg, 0x42c, PERI_MSDC_CLK_EN),
+ REGNAME(mfgsys, 0x000, MFG_CG_STA),
+ REGNAME(mmsys, 0x100, MMSYS_CG0_STA),
+ REGNAME(mmsys, 0x110, MMSYS_CG1_STA),
+ REGNAME(mmsys, 0x220, MMSYS_CG2_STA),
+ REGNAME(imgsys, 0x000, IMG_CG),
+ REGNAME(bdpsys, 0x100, BDP_DISPSYS_CG_CON0),
+ REGNAME(vdecsys, 0x000, VDEC_CKEN_SET),
+ REGNAME(vdecsys, 0x008, VDEC_LARB1_CKEN_STA),
+ REGNAME(vencsys, 0x000, VENC_CG_STA),
+ REGNAME(jpgdecsys, 0x000, JPGDEC_CG_STA),
+ {}
+};
+
+static const struct regname *get_all_regnames(void)
+{
+ return rn;
+}
+
+static void __init init_regbase(void)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(rb); i++)
+ rb[i].virt = ioremap(rb[i].phys, PAGE_SIZE);
+}
+
+/*
+ * clkdbg fmeter
+ */
+
+#include <linux/delay.h>
+
+#ifndef GENMASK
+#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l))
+#endif
+
+#define ALT_BITS(o, h, l, v) \
+ (((o) & ~GENMASK(h, l)) | (((v) << (l)) & GENMASK(h, l)))
+
+#define clk_readl(addr) readl(addr)
+#define clk_writel(addr, val) \
+ do { writel(val, addr); wmb(); } while (0) /* sync write */
+#define clk_writel_mask(addr, mask, val) \
+ clk_writel(addr, (clk_readl(addr) & ~(mask)) | (val))
+
+#define ABS_DIFF(a, b) ((a) > (b) ? (a) - (b) : (b) - (a))
+
+#define FMCLK(_t, _i, _n) { .type = _t, .id = _i, .name = _n }
+
+static const struct fmeter_clk fclks[] = {
+ FMCLK(ABIST, 2, "AD_ARMCA35PLL_600M_CORE_CK"),
+ FMCLK(ABIST, 3, "AD_ARMCA35PLL_400M_CORE_CK"),
+ FMCLK(ABIST, 4, "AD_MAIN_H546M_CK"),
+ FMCLK(ABIST, 5, "AD_MAIN_H364M_CK"),
+ FMCLK(ABIST, 6, "AD_MAIN_H218P4M_CK"),
+ FMCLK(ABIST, 7, "AD_MAIN_H156M_CK"),
+ FMCLK(ABIST, 8, "AD_UNIV_178P3M_CK"),
+ FMCLK(ABIST, 9, "AD_UNIVPLL_UNIV_48M_CK"),
+ FMCLK(ABIST, 10, "AD_UNIV_624M_CK"),
+ FMCLK(ABIST, 11, "AD_UNIV_416M_CK"),
+ FMCLK(ABIST, 12, "AD_UNIV_249P6M_CK"),
+ FMCLK(ABIST, 13, "AD_APLL1_CK"),
+ FMCLK(ABIST, 14, "AD_APLL2_CK"),
+ FMCLK(ABIST, 15, "AD_LTEPLL_FS26M_CK"),
+ FMCLK(ABIST, 16, "rtc32k_ck_i"),
+ FMCLK(ABIST, 17, "AD_MMPLL_500M_CK"),
+ FMCLK(ABIST, 18, "AD_VENCPLL_380M_CK"),
+ FMCLK(ABIST, 19, "AD_VCODEPLL_442M_CK"),
+ FMCLK(ABIST, 20, "AD_TVDPLL_572M_CK"),
+ FMCLK(ABIST, 21, "AD_LVDSPLL_150M_CK"),
+ FMCLK(ABIST, 22, "AD_MSDCPLL_400M_CK"),
+ FMCLK(ABIST, 23, "AD_ETHERPLL_50M_CK"),
+ FMCLK(ABIST, 24, "clkph_MCK_o"),
+ FMCLK(ABIST, 25, "AD_USB_48M_CK"),
+ FMCLK(ABIST, 26, "AD_MSDCPLL2_400M_CK"),
+ FMCLK(ABIST, 27, "AD_CVBSADC_CKOUTA"),
+ FMCLK(ABIST, 30, "AD_TVDPLL_429M_CK"),
+ FMCLK(ABIST, 33, "AD_LVDSPLL2_150M_CK"),
+ FMCLK(ABIST, 34, "AD_ETHERPLL_125M_CK"),
+ FMCLK(ABIST, 35, "AD_MIPI_26M_CK_CKSYS"),
+ FMCLK(ABIST, 36, "AD_LTEPLL_ARMPLL26M_CK_CKSYS"),
+ FMCLK(ABIST, 37, "AD_LETPLL_SSUSB26M_CK_CKSYS"),
+ FMCLK(ABIST, 38, "AD_DSI2_LNTC_DSICLK_CKSYS"),
+ FMCLK(ABIST, 39, "AD_DSI3_LNTC_DSICLK_CKSYS"),
+ FMCLK(ABIST, 40, "AD_DSI2_MPPLL_TST_CK_CKSYS"),
+ FMCLK(ABIST, 41, "AD_DSI3_MPPLL_TST_CK_CKSYS"),
+ FMCLK(ABIST, 42, "AD_LVDSTX3_MONCLK"),
+ FMCLK(ABIST, 43, "AD_PLLGP_TST_CK_CKSYS"),
+ FMCLK(ABIST, 44, "AD_SSUSB_48M_CK_CKSYS"),
+ FMCLK(ABIST, 45, "AD_MONREF3_CK"),
+ FMCLK(ABIST, 46, "AD_MONFBK3_CK"),
+ FMCLK(ABIST, 47, "big_clkmon_o"),
+ FMCLK(ABIST, 48, "DA_ARMCPU_MON_CK"),
+ FMCLK(ABIST, 49, "AD_CSI0_LNRC_BYTE_CLK"),
+ FMCLK(ABIST, 50, "AD_CSI1_LNRC_BYTE_CLK"),
+ FMCLK(ABIST, 51, "AD_CSI0_LNRC_4X_CLK"),
+ FMCLK(ABIST, 52, "AD_CSI1_LNRC_4X_CLK"),
+ FMCLK(ABIST, 53, "AD_CSI0_CAL_CLK"),
+ FMCLK(ABIST, 54, "AD_CSI1_CAL_CLK"),
+ FMCLK(ABIST, 55, "AD_UNIVPL_1248M_CK"),
+ FMCLK(ABIST, 56, "AD_MAINPLL_1092_CORE_CK"),
+ FMCLK(ABIST, 57, "AD_ARMCA15PLL_2002M_CORE_CK"),
+ FMCLK(ABIST, 58, "mcusys_arm_clk_out_all"),
+ FMCLK(ABIST, 59, "AD_ARMCA7PLL_1508M_CORE_CK"),
+ FMCLK(ABIST, 61, "AD_UNIVPLL_USB20_48M_CK"),
+ FMCLK(ABIST, 62, "AD_UNIVPLL_USB20_48M_CK1"),
+ FMCLK(ABIST, 63, "AD_UNIVPLL_USB20_48M_CK2"),
+ FMCLK(ABIST, 65, "AD_UNIVPLL_USB20_48M_CK3"),
+ FMCLK(ABIST, 77, "AD_LVDSTX1_MONCLK"),
+ FMCLK(ABIST, 78, "AD_MONREF1_CK"),
+ FMCLK(ABIST, 79, "AD_MONFBK1_CK"),
+ FMCLK(ABIST, 85, "trng_freq_debug_out0"),
+ FMCLK(ABIST, 86, "trng_freq_debug_out1"),
+ FMCLK(ABIST, 87, "AD_DSI0_LNTC_DSICLK_CKSYS"),
+ FMCLK(ABIST, 88, "AD_DSI0_MPLL_TST_CK_CKSYS"),
+ FMCLK(ABIST, 89, "AD_DSI1_LNTC_DSICLK_CKSYS"),
+ FMCLK(ABIST, 90, "AD_DSI1_MPLL_TST_CK_CKSYS"),
+ FMCLK(ABIST, 91, "ddr_clk_freq_meter[0]"),
+ FMCLK(ABIST, 92, "ddr_clk_freq_meter[1]"),
+ FMCLK(ABIST, 93, "ddr_clk_freq_meter[2]"),
+ FMCLK(ABIST, 94, "ddr_clk_freq_meter[3]"),
+ FMCLK(ABIST, 95, "ddr_clk_freq_meter[4]"),
+ FMCLK(ABIST, 96, "ddr_clk_freq_meter[5]"),
+ FMCLK(ABIST, 97, "ddr_clk_freq_meter[6]"),
+ FMCLK(ABIST, 98, "ddr_clk_freq_meter[7]"),
+ FMCLK(ABIST, 99, "ddr_clk_freq_meter[8]"),
+ FMCLK(ABIST, 100, "ddr_clk_freq_meter[9]"),
+ FMCLK(ABIST, 101, "ddr_clk_freq_meter[10]"),
+ FMCLK(ABIST, 102, "ddr_clk_freq_meter[11]"),
+ FMCLK(ABIST, 103, "ddr_clk_freq_meter[12]"),
+ FMCLK(ABIST, 104, "ddr_clk_freq_meter[13]"),
+ FMCLK(ABIST, 105, "ddr_clk_freq_meter[14]"),
+ FMCLK(ABIST, 106, "ddr_clk_freq_meter[15]"),
+ FMCLK(ABIST, 107, "ddr_clk_freq_meter[16]"),
+ FMCLK(ABIST, 108, "ddr_clk_freq_meter[17]"),
+ FMCLK(ABIST, 109, "ddr_clk_freq_meter[18]"),
+ FMCLK(ABIST, 110, "ddr_clk_freq_meter[19]"),
+ FMCLK(ABIST, 111, "ddr_clk_freq_meter[20]"),
+ FMCLK(ABIST, 112, "ddr_clk_freq_meter[21]"),
+ FMCLK(ABIST, 113, "ddr_clk_freq_meter[22]"),
+ FMCLK(ABIST, 114, "ddr_clk_freq_meter[23]"),
+ FMCLK(ABIST, 115, "ddr_clk_freq_meter[24]"),
+ FMCLK(ABIST, 116, "ddr_clk_freq_meter[25]"),
+ FMCLK(ABIST, 117, "ddr_clk_freq_meter[26]"),
+ FMCLK(ABIST, 118, "ddr_clk_freq_meter[27]"),
+ FMCLK(ABIST, 119, "ddr_clk_freq_meter[28]"),
+ FMCLK(ABIST, 120, "ddr_clk_freq_meter[29]"),
+ FMCLK(ABIST, 121, "ddr_clk_freq_meter[30]"),
+ FMCLK(ABIST, 122, "ddr_clk_freq_meter[31]"),
+ FMCLK(ABIST, 123, "ddr_clk_freq_meter[32]"),
+ FMCLK(ABIST, 124, "ddr_clk_freq_meter[33]"),
+ FMCLK(ABIST, 125, "ddr_clk_freq_meter[34]"),
+ FMCLK(CKGEN, 1, "hf_faxi_ck"),
+ FMCLK(CKGEN, 2, "hd_faxi_ck"),
+ FMCLK(CKGEN, 3, "hf_fscam_ck"),
+ FMCLK(CKGEN, 5, "hf_fmm_ck"),
+ FMCLK(CKGEN, 6, "f_fpwm_ck"),
+ FMCLK(CKGEN, 7, "hf_fvdec_ck"),
+ FMCLK(CKGEN, 8, "hf_fvenc_ck"),
+ FMCLK(CKGEN, 9, "hf_fmfg_ck"),
+ FMCLK(CKGEN, 10, "hf_fcamtg_ck"),
+ FMCLK(CKGEN, 11, "f_fuart_ck"),
+ FMCLK(CKGEN, 12, "hf_fspi_ck"),
+ FMCLK(CKGEN, 13, "f_fusb20_ck"),
+ FMCLK(CKGEN, 14, "f_fusb30_ck"),
+ FMCLK(CKGEN, 15, "hf_fmsdc50_0_hclk_ck"),
+ FMCLK(CKGEN, 16, "hf_fmsdc50_0_ck"),
+ FMCLK(CKGEN, 17, "hf_fmsdc30_1_ck"),
+ FMCLK(CKGEN, 18, "hf_fmsdc30_2_ck"),
+ FMCLK(CKGEN, 19, "hf_fmsdc30_3_ck"),
+ FMCLK(CKGEN, 20, "hf_faudio_ck"),
+ FMCLK(CKGEN, 21, "hf_faud_intbus_ck"),
+ FMCLK(CKGEN, 22, "hf_fpmicspi_ck"),
+ FMCLK(CKGEN, 23, "hf_fdpilvds1_ck"),
+ FMCLK(CKGEN, 24, "hf_fatb_ck"),
+ FMCLK(CKGEN, 25, "hf_fnr_ck"),
+ FMCLK(CKGEN, 26, "hf_firda_ck"),
+ FMCLK(CKGEN, 27, "hf_fcci400_ck"),
+ FMCLK(CKGEN, 28, "hf_faud_1_ck"),
+ FMCLK(CKGEN, 29, "hf_faud_2_ck"),
+ FMCLK(CKGEN, 30, "hf_fmem_mfg_in_as_ck"),
+ FMCLK(CKGEN, 31, "hf_faxi_mfg_in_as_ck"),
+ FMCLK(CKGEN, 32, "f_frtc_ck"),
+ FMCLK(CKGEN, 33, "f_f26m_ck"),
+ FMCLK(CKGEN, 34, "f_f32k_md1_ck"),
+ FMCLK(CKGEN, 35, "f_frtc_conn_ck"),
+ FMCLK(CKGEN, 36, "hg_fmipicfg_ck"),
+ FMCLK(CKGEN, 37, "hd_haxi_nli_ck"),
+ FMCLK(CKGEN, 38, "hd_qaxidcm_ck"),
+ FMCLK(CKGEN, 39, "f_ffpc_ck"),
+ FMCLK(CKGEN, 40, "f_fckbus_ck_scan"),
+ FMCLK(CKGEN, 41, "f_fckrtc_ck_scan"),
+ FMCLK(CKGEN, 42, "hf_flvds_pxl_ck"),
+ FMCLK(CKGEN, 43, "hf_flvds_cts_ck"),
+ FMCLK(CKGEN, 44, "hf_fdpilvds_ck"),
+ FMCLK(CKGEN, 45, "hf_flvds1_pxl_ck"),
+ FMCLK(CKGEN, 46, "hf_flvds1_cts_ck"),
+ FMCLK(CKGEN, 47, "hf_fhdcp_ck"),
+ FMCLK(CKGEN, 48, "hf_fmsdc50_3_hclk_ck"),
+ FMCLK(CKGEN, 49, "hf_fhdcp_24m_ck"),
+ FMCLK(CKGEN, 50, "hf_fmsdc0p_aes_ck"),
+ FMCLK(CKGEN, 51, "hf_fgcpu_ck"),
+ FMCLK(CKGEN, 52, "hf_fmem_ck"),
+ FMCLK(CKGEN, 53, "hf_fi2so1_mck"),
+ FMCLK(CKGEN, 54, "hf_fcam2tg_ck"),
+ FMCLK(CKGEN, 55, "hf_fether_125m_ck"),
+ FMCLK(CKGEN, 56, "hf_fapll2_ck"),
+ FMCLK(CKGEN, 57, "hf_fa2sys_hp_ck"),
+ FMCLK(CKGEN, 58, "hf_fasm_l_ck"),
+ FMCLK(CKGEN, 59, "hf_fspislv_ck"),
+ FMCLK(CKGEN, 60, "hf_ftdmo1_mck"),
+ FMCLK(CKGEN, 61, "hf_fasm_h_ck"),
+ FMCLK(CKGEN, 62, "hf_ftdmo0_mck"),
+ FMCLK(CKGEN, 63, "hf_fa1sys_hp_ck"),
+ FMCLK(CKGEN, 65, "hf_fasm_m_ck"),
+ FMCLK(CKGEN, 66, "hf_fapll_ck"),
+ FMCLK(CKGEN, 67, "hf_fspinor_ck"),
+ FMCLK(CKGEN, 68, "hf_fpe2_mac_p0_ck"),
+ FMCLK(CKGEN, 69, "hf_fjpgdec_ck"),
+ FMCLK(CKGEN, 70, "hf_fpwm_infra_ck"),
+ FMCLK(CKGEN, 71, "hf_fnfiecc_ck"),
+ FMCLK(CKGEN, 72, "hf_fether_50m_rmii_ck"),
+ FMCLK(CKGEN, 73, "hf_fi2c_ck"),
+ FMCLK(CKGEN, 74, "hf_fcmsys_ck"),
+ FMCLK(CKGEN, 75, "hf_fpe2_mac_p1_ck"),
+ FMCLK(CKGEN, 76, "hf_fdi_ck"),
+ FMCLK(CKGEN, 77, "hf_fi2si3_mck"),
+ FMCLK(CKGEN, 78, "hf_fether_50m_ck"),
+ FMCLK(CKGEN, 79, "hf_fi2si2_mck"),
+ FMCLK(CKGEN, 80, "hf_fi2so3_mck"),
+ FMCLK(CKGEN, 81, "hf_ftvd_ck"),
+ FMCLK(CKGEN, 82, "hf_fnfi2x_ck"),
+ FMCLK(CKGEN, 83, "hf_fi2si1_mck"),
+ FMCLK(CKGEN, 84, "hf_fi2so2_mck"),
+ {}
+};
+
+#define FHCTL_HP_EN (rb[fhctl].virt + 0x000)
+#define CLK_CFG_M0 (rb[topckgen].virt + 0x100)
+#define CLK_CFG_M1 (rb[topckgen].virt + 0x104)
+#define CLK_MISC_CFG_1 (rb[topckgen].virt + 0x214)
+#define CLK_MISC_CFG_2 (rb[topckgen].virt + 0x218)
+#define CLK26CALI_0 (rb[topckgen].virt + 0x220)
+#define CLK26CALI_1 (rb[topckgen].virt + 0x224)
+#define CLK26CALI_2 (rb[topckgen].virt + 0x228)
+#define PLL_TEST_CON0 (rb[apmixed].virt + 0x040)
+#define CVBSPLL_CON1 (rb[apmixed].virt + 0x314)
+#define CVBSREFPLL_CON1 (rb[apmixed].virt + 0x31c)
+
+#define RG_FRMTR_WINDOW 1023U
+
+static void set_fmeter_divider_ca35(u32 k1)
+{
+ u32 val = clk_readl(CLK_MISC_CFG_1);
+
+ val = ALT_BITS(val, 15, 8, k1);
+ clk_writel(CLK_MISC_CFG_1, val);
+}
+
+static void set_fmeter_divider_ca72(u32 k1)
+{
+ u32 val = clk_readl(CLK_MISC_CFG_2);
+
+ val = ALT_BITS(val, 7, 0, k1);
+ clk_writel(CLK_MISC_CFG_2, val);
+}
+
+static void set_fmeter_divider(u32 k1)
+{
+ u32 val = clk_readl(CLK_MISC_CFG_1);
+
+ val = ALT_BITS(val, 7, 0, k1);
+ val = ALT_BITS(val, 31, 24, k1);
+ clk_writel(CLK_MISC_CFG_1, val);
+}
+
+static u8 wait_fmeter_done(u32 tri_bit)
+{
+ static int max_wait_count;
+ int wait_count = (max_wait_count > 0) ? (max_wait_count * 2 + 2) : 100;
+ int i;
+
+ /* wait fmeter */
+ for (i = 0; i < wait_count &&
+ (clk_readl(CLK26CALI_0) & tri_bit) != 0U; i++)
+ udelay(20);
+
+ if ((clk_readl(CLK26CALI_0) & tri_bit) == 0U) {
+ max_wait_count = max(max_wait_count, i);
+ return 1;
+ }
+
+ return 0;
+}
+
+static u32 fmeter_freq(enum FMETER_TYPE type, u32 k1, u32 clk)
+{
+ void __iomem *clk_cfg_reg = (type == CKGEN) ? CLK_CFG_M1 : CLK_CFG_M0;
+ void __iomem *cnt_reg = (type == CKGEN) ? CLK26CALI_2 : CLK26CALI_1;
+ u32 cksw_mask = (type == CKGEN) ? GENMASK(22, 16) : GENMASK(14, 8);
+ u32 cksw_val = (type == CKGEN) ? (clk << 16) : (clk << 8);
+ u32 tri_bit = (type == CKGEN) ? BIT(4) : BIT(0);
+ u32 clk_exc = (type == CKGEN) ? BIT(5) : BIT(2);
+ u32 clk_misc_cfg_1, clk_misc_cfg_2, clk_cfg_val, cnt, freq = 0;
+
+ /* setup fmeter */
+ clk_setl(CLK26CALI_0, BIT(7)); /* enable fmeter_en */
+ clk_clrl(CLK26CALI_0, clk_exc); /* set clk_exc */
+ /* load_cnt */
+ clk_writel_mask(cnt_reg, GENMASK(25, 16), RG_FRMTR_WINDOW << 16);
+
+ /* backup CLK_MISC_CFG_1 value */
+ clk_misc_cfg_1 = clk_readl(CLK_MISC_CFG_1);
+ /* backup CLK_MISC_CFG_2 value */
+ clk_misc_cfg_2 = clk_readl(CLK_MISC_CFG_2);
+ /* backup clk_cfg_reg value */
+ clk_cfg_val = clk_readl(clk_cfg_reg);
+
+ set_fmeter_divider(k1); /* set divider (0 = /1) */
+ set_fmeter_divider_ca35(k1);
+ set_fmeter_divider_ca72(k1);
+ /* select cksw */
+ clk_writel_mask(clk_cfg_reg, cksw_mask, cksw_val);
+
+ clk_setl(CLK26CALI_0, tri_bit); /* start fmeter */
+
+ if (wait_fmeter_done(tri_bit) == 1U) {
+ cnt = clk_readl(cnt_reg) & 0xFFFF;
+ /* (KHz) ; freq = counter * 26M / 1024 */
+ freq = (cnt * 26000U) * (k1 + 1U) / (RG_FRMTR_WINDOW + 1U);
+ }
+
+ /* restore register settings */
+ clk_writel(clk_cfg_reg, clk_cfg_val);
+ clk_writel(CLK_MISC_CFG_2, clk_misc_cfg_2);
+ clk_writel(CLK_MISC_CFG_1, clk_misc_cfg_1);
+
+ clk_clrl(CLK26CALI_0, BIT(7)); /* disable fmeter_en */
+
+ return freq;
+}
+
+static u32 measure_stable_fmeter_freq(enum FMETER_TYPE type, u32 k1, u32 clk)
+{
+ u32 last_freq = 0;
+ u32 freq = fmeter_freq(type, k1, clk);
+ u32 maxfreq = max(freq, last_freq);
+
+ while (maxfreq != 0U &&
+ ABS_DIFF(freq, last_freq) * 100U / maxfreq > 10U) {
+ last_freq = freq;
+ freq = fmeter_freq(type, k1, clk);
+ maxfreq = max(freq, last_freq);
+ }
+
+ return freq;
+}
+
+static const struct fmeter_clk *get_all_fmeter_clks(void)
+{
+ return fclks;
+}
+
+struct bak {
+ u32 fhctl_hp_en;
+};
+
+static void *prepare_fmeter(void)
+{
+ static struct bak regs;
+
+ regs.fhctl_hp_en = clk_readl(FHCTL_HP_EN);
+
+ clk_writel(FHCTL_HP_EN, 0x0); /* disable PLL hopping */
+ udelay(10);
+
+ /* use AD_PLLGP_TST_CK_CKSYS to measure CVBSPLL */
+ /* [9:8]:TST_SEL, [3:0]:TSTOD_EN, A2DCK_EN, TSTCK_EN, TST_EN */
+ clk_setl(PLL_TEST_CON0, 0x30F);
+ /* [4]:CVBS_MONCK_EN, [3:0]:CVBSREFPLL_TESTMUX */
+ clk_setl(CVBSREFPLL_CON1, 0x11);
+ clk_setl(CVBSPLL_CON1, 0x20); /* [5]: CVBSPLL_MONCK_EN */
+
+ return ®s;
+}
+
+static void unprepare_fmeter(void *data)
+{
+ struct bak *regs = data;
+
+ /* [9:8]:TST_SEL, [3:0]:TSTOD_EN, A2DCK_EN, TSTCK_EN, TST_EN */
+ clk_clrl(PLL_TEST_CON0, 0x30F);
+ /* [4]:CVBS_MONCK_EN, [3:0]:CVBSREFPLL_TESTMUX */
+ clk_clrl(CVBSREFPLL_CON1, 0x11);
+ clk_clrl(CVBSPLL_CON1, 0x20); /* [5]: CVBSPLL_MONCK_EN */
+
+ /* restore old setting */
+ clk_writel(FHCTL_HP_EN, regs->fhctl_hp_en);
+}
+
+static u32 fmeter_freq_op(const struct fmeter_clk *fclk)
+{
+ if (fclk->type != FT_NULL)
+ return measure_stable_fmeter_freq(fclk->type, 0, fclk->id);
+
+ return 0;
+}
+
+/*
+ * clkdbg dump_state
+ */
+
+static const char * const *get_all_clk_names(void)
+{
+ static const char * const clks[] = {
+ /* plls */
+ "mainpll",
+ "univpll",
+ "vcodecpll",
+ "vencpll",
+ "apll1",
+ "apll2",
+ "lvdspll",
+ "lvdspll2",
+ "msdcpll",
+ "msdcpll2",
+ "tvdpll",
+ "mmpll",
+ "armca35pll",
+ "armca72pll",
+ "etherpll",
+ "cvbspll",
+ /* topckgen */
+ "armca35pll_ck",
+ "armca35pll_600m",
+ "armca35pll_400m",
+ "armca72pll_ck",
+ "syspll_ck",
+ "syspll_d2",
+ "syspll1_d2",
+ "syspll1_d4",
+ "syspll1_d8",
+ "syspll1_d16",
+ "syspll_d3",
+ "syspll2_d2",
+ "syspll2_d4",
+ "syspll_d5",
+ "syspll3_d2",
+ "syspll3_d4",
+ "syspll_d7",
+ "syspll4_d2",
+ "syspll4_d4",
+ "univpll_ck",
+ "univpll_d7",
+ "univpll_d26",
+ "univpll_d52",
+ "univpll_d104",
+ "univpll_d208",
+ "univpll_d2",
+ "univpll1_d2",
+ "univpll1_d4",
+ "univpll1_d8",
+ "univpll_d3",
+ "univpll2_d2",
+ "univpll2_d4",
+ "univpll2_d8",
+ "univpll_d5",
+ "univpll3_d2",
+ "univpll3_d4",
+ "univpll3_d8",
+ "f_mp0_pll1_ck",
+ "f_mp0_pll2_ck",
+ "f_big_pll1_ck",
+ "f_big_pll2_ck",
+ "f_bus_pll1_ck",
+ "f_bus_pll2_ck",
+ "apll1_ck",
+ "apll1_d2",
+ "apll1_d3",
+ "apll1_d4",
+ "apll1_d8",
+ "apll1_d16",
+ "apll2_ck",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8",
+ "apll2_d16",
+ "lvdspll_ck",
+ "lvdspll_d2",
+ "lvdspll_d4",
+ "lvdspll_d8",
+ "lvdspll2_ck",
+ "lvdspll2_d2",
+ "lvdspll2_d4",
+ "lvdspll2_d8",
+ "etherpll_125m",
+ "etherpll_50m",
+ "cvbs",
+ "cvbs_d2",
+ "sys_26m",
+ "mmpll_ck",
+ "mmpll_d2",
+ "vencpll_ck",
+ "vencpll_d2",
+ "vcodecpll_ck",
+ "vcodecpll_d2",
+ "tvdpll_ck",
+ "tvdpll_d2",
+ "tvdpll_d4",
+ "tvdpll_d8",
+ "tvdpll_429m",
+ "tvdpll_429m_d2",
+ "tvdpll_429m_d4",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "msdcpll_d4",
+ "msdcpll2_ck",
+ "msdcpll2_d2",
+ "msdcpll2_d4",
+ "clk26m_d2",
+ "d2a_ulclk_6p5m",
+ "vpll3_dpix",
+ "vpll_dpix",
+ "ltepll_fs26m",
+ "dmpll_ck",
+ "dsi0_lntc",
+ "dsi1_lntc",
+ "lvdstx3",
+ "lvdstx",
+ "clkrtc_ext",
+ "clkrtc_int",
+ "csi0",
+ "apll_div0",
+ "apll_div1",
+ "apll_div2",
+ "apll_div3",
+ "apll_div4",
+ "apll_div5",
+ "apll_div6",
+ "apll_div7",
+ "apll_div_pdn0",
+ "apll_div_pdn1",
+ "apll_div_pdn2",
+ "apll_div_pdn3",
+ "apll_div_pdn4",
+ "apll_div_pdn5",
+ "apll_div_pdn6",
+ "apll_div_pdn7",
+ "nfi2x_en",
+ "nfiecc_en",
+ "nfi1x_ck_en",
+ "axi_sel",
+ "mem_sel",
+ "mm_sel",
+ "pwm_sel",
+ "vdec_sel",
+ "venc_sel",
+ "mfg_sel",
+ "camtg_sel",
+ "uart_sel",
+ "spi_sel",
+ "usb20_sel",
+ "usb30_sel",
+ "msdc50_0_h_sel",
+ "msdc50_0_sel",
+ "msdc30_1_sel",
+ "msdc30_2_sel",
+ "msdc30_3_sel",
+ "audio_sel",
+ "aud_intbus_sel",
+ "pmicspi_sel",
+ "dpilvds1_sel",
+ "atb_sel",
+ "nr_sel",
+ "nfi2x_sel",
+ "irda_sel",
+ "cci400_sel",
+ "aud_1_sel",
+ "aud_2_sel",
+ "mem_mfg_sel",
+ "axi_mfg_sel",
+ "scam_sel",
+ "nfiecc_sel",
+ "pe2_mac_p0_sel",
+ "pe2_mac_p1_sel",
+ "dpilvds_sel",
+ "msdc50_3_h_sel",
+ "hdcp_sel",
+ "hdcp_24m_sel",
+ "rtc_sel",
+ "spinor_sel",
+ "apll_sel",
+ "apll2_sel",
+ "a1sys_hp_sel",
+ "a2sys_hp_sel",
+ "asm_l_sel",
+ "asm_m_sel",
+ "asm_h_sel",
+ "i2so1_sel",
+ "i2so2_sel",
+ "i2so3_sel",
+ "tdmo0_sel",
+ "tdmo1_sel",
+ "i2si1_sel",
+ "i2si2_sel",
+ "i2si3_sel",
+ "ether_125m_sel",
+ "ether_50m_sel",
+ "jpgdec_sel",
+ "spislv_sel",
+ "ether_sel",
+ "cam2tg_sel",
+ "di_sel",
+ "tvd_sel",
+ "i2c_sel",
+ "pwm_infra_sel",
+ "msdc0p_aes_sel",
+ "cmsys_sel",
+ "gcpu_sel",
+ "aud_apll1_sel",
+ "aud_apll2_sel",
+ "apll1_ref_sel",
+ "apll2_ref_sel",
+ "audull_vtx_sel",
+ /* mcucfg */
+ "mcu_mp0_sel",
+ "mcu_mp2_sel",
+ "mcu_bus_sel",
+ /* bdpsys */
+ "bdp_bridge_b",
+ "bdp_bridge_d",
+ "bdp_larb_d",
+ "bdp_vdi_pxl",
+ "bdp_vdi_d",
+ "bdp_vdi_b",
+ "bdp_fmt_b",
+ "bdp_27m",
+ "bdp_27m_vdout",
+ "bdp_27_74_74",
+ "bdp_2fs",
+ "bdp_2fs74_148",
+ "bdp_b",
+ "bdp_vdo_d",
+ "bdp_vdo_2fs",
+ "bdp_vdo_b",
+ "bdp_di_pxl",
+ "bdp_di_d",
+ "bdp_di_b",
+ "bdp_nr_agent",
+ "bdp_nr_d",
+ "bdp_nr_b",
+ "bdp_bridge_rt_b",
+ "bdp_bridge_rt_d",
+ "bdp_larb_rt_d",
+ "bdp_tvd_tdc",
+ "bdp_tvd_clk_54",
+ "bdp_tvd_cbus",
+ /* infracfg */
+ "infra_dbgclk",
+ "infra_gce",
+ "infra_m4u",
+ "infra_kp",
+ "infra_ao_spi0",
+ "infra_ao_spi1",
+ "infra_ao_uart5",
+ /* imgsys */
+ "img_smi_larb2",
+ "img_scam_en",
+ "img_cam_en",
+ "img_cam_sv_en",
+ "img_cam_sv1_en",
+ "img_cam_sv2_en",
+ /* jpgdecsys */
+ "jpgdec_jpgdec1",
+ "jpgdec_jpgdec",
+ /* mfgcfg */
+ "mfg_bg3d",
+ /* mmsys */
+ "mm_smi_common",
+ "mm_smi_larb0",
+ "mm_cam_mdp",
+ "mm_mdp_rdma0",
+ "mm_mdp_rdma1",
+ "mm_mdp_rsz0",
+ "mm_mdp_rsz1",
+ "mm_mdp_rsz2",
+ "mm_mdp_tdshp0",
+ "mm_mdp_tdshp1",
+ "mm_mdp_crop",
+ "mm_mdp_wdma",
+ "mm_mdp_wrot0",
+ "mm_mdp_wrot1",
+ "mm_fake_eng",
+ "mm_mutex_32k",
+ "mm_disp_ovl0",
+ "mm_disp_ovl1",
+ "mm_disp_rdma0",
+ "mm_disp_rdma1",
+ "mm_disp_rdma2",
+ "mm_disp_wdma0",
+ "mm_disp_wdma1",
+ "mm_disp_color0",
+ "mm_disp_color1",
+ "mm_disp_aal",
+ "mm_disp_gamma",
+ "mm_disp_ufoe",
+ "mm_disp_split0",
+ "mm_disp_od",
+ "mm_pwm0_mm",
+ "mm_pwm0_26m",
+ "mm_pwm1_mm",
+ "mm_pwm1_26m",
+ "mm_dsi0_engine",
+ "mm_dsi0_digital",
+ "mm_dsi1_engine",
+ "mm_dsi1_digital",
+ "mm_dpi_pixel",
+ "mm_dpi_engine",
+ "mm_dpi1_pixel",
+ "mm_dpi1_engine",
+ "mm_lvds_pixel",
+ "mm_lvds_cts",
+ "mm_smi_larb4",
+ "mm_smi_common1",
+ "mm_smi_larb5",
+ "mm_mdp_rdma2",
+ "mm_mdp_tdshp2",
+ "mm_disp_ovl2",
+ "mm_disp_wdma2",
+ "mm_disp_color2",
+ "mm_disp_aal1",
+ "mm_disp_od1",
+ "mm_lvds1_pixel",
+ "mm_lvds1_cts",
+ "mm_smi_larb7",
+ "mm_mdp_rdma3",
+ "mm_mdp_wrot2",
+ "mm_dsi2",
+ "mm_dsi2_digital",
+ "mm_dsi3",
+ "mm_dsi3_digital",
+ /* pericfg */
+ "per_nfi",
+ "per_therm",
+ "per_pwm0",
+ "per_pwm1",
+ "per_pwm2",
+ "per_pwm3",
+ "per_pwm4",
+ "per_pwm5",
+ "per_pwm6",
+ "per_pwm7",
+ "per_pwm",
+ "per_ap_dma",
+ "per_msdc30_0",
+ "per_msdc30_1",
+ "per_msdc30_2",
+ "per_msdc30_3",
+ "per_uart0",
+ "per_uart1",
+ "per_uart2",
+ "per_uart3",
+ "per_i2c0",
+ "per_i2c1",
+ "per_i2c2",
+ "per_i2c3",
+ "per_i2c4",
+ "per_auxadc",
+ "per_spi0",
+ "per_spi",
+ "per_i2c5",
+ "per_spi2",
+ "per_spi3",
+ "per_spi5",
+ "per_uart4",
+ "per_sflash",
+ "per_gmac",
+ "per_pcie0",
+ "per_pcie1",
+ "per_gmac_pclk",
+ "per_msdc50_0_en",
+ "per_msdc30_1_en",
+ "per_msdc30_2_en",
+ "per_msdc30_3_en",
+ "per_msdc50_0_h",
+ "per_msdc50_3_h",
+ "per_msdc30_0_q",
+ "per_msdc30_3_q",
+ /* vdecsys */
+ "vdec_cken",
+ "vdec_larb1_cken",
+ "vdec_imgrz_cken",
+ /* vencsys */
+ "venc_smi",
+ "venc_venc",
+ "venc_smi_larb6",
+ /* end */
+ NULL
+ };
+
+ return clks;
+}
+
+/*
+ * clkdbg pwr_status
+ */
+
+static const char * const *get_pwr_names(void)
+{
+ static const char * const pwr_names[] = {
+ [0] = "MD",
+ [1] = "CONN",
+ [2] = "DDRPHY0",
+ [3] = "DISP",
+ [4] = "MFG",
+ [5] = "ISP",
+ [6] = "INFRA",
+ [7] = "VDEC",
+ [8] = "MP0_CPUTOP",
+ [9] = "MP0_CPU0",
+ [10] = "MP0_CPU1",
+ [11] = "MP0_CPU2",
+ [12] = "MP0_CPU3",
+ [13] = "",
+ [14] = "MCUSYS",
+ [15] = "MP1_CPUTOP",
+ [16] = "MP1_CPU0",
+ [17] = "MP1_CPU1",
+ [18] = "",
+ [19] = "USB2",
+ [20] = "",
+ [21] = "VENC",
+ [22] = "MFG_SC1",
+ [23] = "MFG_SC2",
+ [24] = "AUDIO",
+ [25] = "USB",
+ [26] = "",
+ [27] = "DDRPHY1",
+ [28] = "DDRPHY2",
+ [29] = "DDRPHY3",
+ [30] = "MFG_SC3",
+ [31] = "",
+ };
+
+ return pwr_names;
+}
+
+/*
+ * clkdbg dump_clks
+ */
+
+static void setup_provider_clk(struct provider_clk *pvdck)
+{
+ static const struct {
+ const char *pvdname;
+ u32 pwr_mask;
+ } pvd_pwr_mask[] = {
+ {"mfgcfg", BIT(4)},
+ {"mmsys", BIT(3)},
+ {"imgsys", BIT(3) | BIT(5)},
+ {"bdpsys", BIT(3) | BIT(5)},
+ {"vdecsys", BIT(3) | BIT(7)},
+ {"vencsys", BIT(3) | BIT(21)},
+ {"jpgdecsys", BIT(3) | BIT(21)},
+ {"audsys", BIT(24)},
+ };
+
+ size_t i;
+ const char *pvdname = pvdck->provider_name;
+
+ if (pvdname == NULL)
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(pvd_pwr_mask); i++) {
+ if (strcmp(pvdname, pvd_pwr_mask[i].pvdname) == 0) {
+ pvdck->pwr_mask = pvd_pwr_mask[i].pwr_mask;
+ return;
+ }
+ }
+}
+
+/*
+ * init functions
+ */
+
+static struct clkdbg_ops clkdbg_mt2712_ops = {
+ .get_all_fmeter_clks = get_all_fmeter_clks,
+ .prepare_fmeter = prepare_fmeter,
+ .unprepare_fmeter = unprepare_fmeter,
+ .fmeter_freq = fmeter_freq_op,
+ .get_all_regnames = get_all_regnames,
+ .get_all_clk_names = get_all_clk_names,
+ .get_pwr_names = get_pwr_names,
+ .setup_provider_clk = setup_provider_clk,
+};
+
+static void __init init_custom_cmds(void)
+{
+ static const struct cmd_fn cmds[] = {
+ {}
+ };
+
+ set_custom_cmds(cmds);
+}
+
+static int __init clkdbg_mt2712_init(void)
+{
+ if (of_machine_is_compatible("mediatek,mt2712") == 0)
+ return -ENODEV;
+
+ init_regbase();
+
+ init_custom_cmds();
+ set_clkdbg_ops(&clkdbg_mt2712_ops);
+
+#if DUMP_INIT_STATE
+ print_regs();
+ print_fmeter_all();
+#endif /* DUMP_INIT_STATE */
+
+ return 0;
+}
+device_initcall(clkdbg_mt2712_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt6880.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt6880.c
new file mode 100755
index 0000000..366966c
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt6880.c
@@ -0,0 +1,874 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/seq_file.h>
+#include <linux/delay.h>
+
+#ifdef CONFIG_MTK_DEVAPC
+#include <linux/soc/mediatek/devapc_public.h>
+#endif
+#include "clk-mux.h"
+#include "clkdbg.h"
+#include "clkdbg-mt6880.h"
+#include "clk-mt6880-fmeter.h"
+
+#define DUMP_INIT_STATE 0
+
+/*
+ * clkdbg dump_regs
+ */
+
+#define REGBASE_V(_phys, _id_name, _pg) { .phys = _phys, \
+ .name = #_id_name, .pg = _pg}
+
+static DEFINE_SPINLOCK(meter_lock);
+#define fmeter_lock(flags) spin_lock_irqsave(&meter_lock, flags)
+#define fmeter_unlock(flags) spin_unlock_irqrestore(&meter_lock, flags)
+/*
+ * checkpatch.pl ERROR:COMPLEX_MACRO
+ *
+ * #define REGBASE(_phys, _id_name) [_id_name] = REGBASE_V(_phys, _id_name)
+ */
+
+static struct regbase rb[] = {
+ [top] = REGBASE_V(0x10000000, top, NULL),
+ [dbgsys_dem] = REGBASE_V(0x0d0a0000, dbgsys_dem, NULL),
+ [ifrao] = REGBASE_V(0x10001000, ifrao, NULL),
+ [infracfg_ao_bus] = REGBASE_V(0x10001000, infracfg_ao_bus, NULL),
+ [peri] = REGBASE_V(0x10003000, peri, NULL),
+ [spm] = REGBASE_V(0x10006000, spm, NULL),
+ [apmixed] = REGBASE_V(0x1000C000, apmixed, NULL),
+ [gce] = REGBASE_V(0x10228000, gce, NULL),
+ [audsys] = REGBASE_V(0x11210000, audsys, "MT6880_POWER_DOMAIN_AUDIO"),
+ [impe] = REGBASE_V(0x11c46000, impe, NULL),
+ [mfgcfg] = REGBASE_V(0x13fbf000, mfgcfg, "MT6880_POWER_DOMAIN_MFG0"),
+ [mm] = REGBASE_V(0x14000000, mm, "MT6880_POWER_DOMAIN_DIS"),
+ {},
+};
+
+#define REGNAME(_base, _ofs, _name) \
+ { .base = &rb[_base], .ofs = _ofs, .name = #_name }
+
+static struct regname rn[] = {
+ /* TOPCKGEN register */
+ REGNAME(top, 0x0010, CLK_CFG_0),
+ REGNAME(top, 0x0020, CLK_CFG_1),
+ REGNAME(top, 0x0030, CLK_CFG_2),
+ REGNAME(top, 0x0040, CLK_CFG_3),
+ REGNAME(top, 0x0050, CLK_CFG_4),
+ REGNAME(top, 0x0060, CLK_CFG_5),
+ REGNAME(top, 0x0070, CLK_CFG_6),
+ REGNAME(top, 0x0080, CLK_CFG_7),
+ REGNAME(top, 0x0090, CLK_CFG_8),
+ REGNAME(top, 0x00A0, CLK_CFG_9),
+ REGNAME(top, 0x00B0, CLK_CFG_10),
+ REGNAME(top, 0x00C0, CLK_CFG_11),
+ REGNAME(top, 0x00D0, CLK_CFG_12),
+ REGNAME(top, 0x0320, CLK_AUDDIV_0),
+ REGNAME(top, 0x0328, CLK_AUDDIV_2),
+ REGNAME(top, 0x0334, CLK_AUDDIV_3),
+ /* DBGSYS_DEM register */
+ REGNAME(dbgsys_dem, 0x70, ATB),
+ REGNAME(dbgsys_dem, 0x2c, DBGBUSCLK_EN),
+ REGNAME(dbgsys_dem, 0x30, DBGSYSCLK_EN),
+ /* INFRACFG_AO register */
+ REGNAME(ifrao, 0x70, INFRA_BUS_DCM_CTRL),
+ REGNAME(ifrao, 0x90, MODULE_SW_CG_0),
+ REGNAME(ifrao, 0x94, MODULE_SW_CG_1),
+ REGNAME(ifrao, 0xac, MODULE_SW_CG_2),
+ REGNAME(ifrao, 0xc8, MODULE_SW_CG_3),
+ REGNAME(ifrao, 0xe8, MODULE_SW_CG_4),
+ REGNAME(ifrao, 0x74, PERI_BUS_DCM_CTRL),
+ /* INFRACFG_AO_BUS register */
+ REGNAME(infracfg_ao_bus, 0x0710, INFRA_TOPAXI_PROTECTEN_2),
+ REGNAME(infracfg_ao_bus, 0x0720, INFRA_TOPAXI_PROTECTEN_STA0_2),
+ REGNAME(infracfg_ao_bus, 0x0724, INFRA_TOPAXI_PROTECTEN_STA1_2),
+ REGNAME(infracfg_ao_bus, 0x0220, INFRA_TOPAXI_PROTECTEN),
+ REGNAME(infracfg_ao_bus, 0x0224, INFRA_TOPAXI_PROTECTEN_STA0),
+ REGNAME(infracfg_ao_bus, 0x0228, INFRA_TOPAXI_PROTECTEN_STA1),
+ REGNAME(infracfg_ao_bus, 0x0250, INFRA_TOPAXI_PROTECTEN_1),
+ REGNAME(infracfg_ao_bus, 0x0254, INFRA_TOPAXI_PROTECTEN_STA0_1),
+ REGNAME(infracfg_ao_bus, 0x0258, INFRA_TOPAXI_PROTECTEN_STA1_1),
+ REGNAME(infracfg_ao_bus, 0x0B80, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR),
+ REGNAME(infracfg_ao_bus, 0x0B8c, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA0),
+ REGNAME(infracfg_ao_bus, 0x0B90, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA1),
+ REGNAME(infracfg_ao_bus, 0x0BA0, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1),
+ REGNAME(infracfg_ao_bus, 0x0BAc, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_STA0),
+ REGNAME(infracfg_ao_bus, 0x0BB0, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_STA1),
+ REGNAME(infracfg_ao_bus, 0x0BB4, INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR),
+ REGNAME(infracfg_ao_bus, 0x0BC0, INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_STA0),
+ REGNAME(infracfg_ao_bus, 0x0BC4, INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_STA1),
+ REGNAME(infracfg_ao_bus, 0x02D0, INFRA_TOPAXI_PROTECTEN_MM),
+ REGNAME(infracfg_ao_bus, 0x02E8, INFRA_TOPAXI_PROTECTEN_MM_STA0),
+ REGNAME(infracfg_ao_bus, 0x02EC, INFRA_TOPAXI_PROTECTEN_MM_STA1),
+ /* PERICFG register */
+ REGNAME(peri, 0x20c, PERIAXI_SI0_CTL),
+ /* SPM register */
+ REGNAME(spm, 0x308, MFG0_PWR_CON),
+ REGNAME(spm, 0x324, IFR_PWR_CON),
+ REGNAME(spm, 0x32C, DPY_PWR_CON),
+ REGNAME(spm, 0x330, PEXTP_D_2LX1_PWR_CON),
+ REGNAME(spm, 0x334, PEXTP_R_2LX1_PWR_CON),
+ REGNAME(spm, 0x338, PEXTP_R_1LX2_PWR_CON),
+ REGNAME(spm, 0x33C, ETH_PWR_CON),
+ REGNAME(spm, 0x34C, NETSYS_PWR_CON),
+ REGNAME(spm, 0x350, DIS_PWR_CON),
+ REGNAME(spm, 0x354, AUDIO_PWR_CON),
+ REGNAME(spm, 0x300, MD1_PWR_CON),
+ REGNAME(spm, 0x328, EIP97_PWR_CON),
+ REGNAME(spm, 0x304, CONN_PWR_CON),
+ REGNAME(spm, 0x3C4, DPY2_PWR_CON),
+ REGNAME(spm, 0x3C0, MCUPM_PWR_CON),
+ REGNAME(spm, 0x3A4, MSDC_PWR_CON),
+ REGNAME(spm, 0x3D0, PERI_PWR_CON),
+ REGNAME(spm, 0x344, HSMTOP_PWR_CON),
+ REGNAME(spm, 0x340, SSUSB_PWR_CON),
+ REGNAME(spm, 0x31C, SSUSB_PHY_PWR_CON),
+ REGNAME(spm, 0x358, SGMII_0_PHY_PWR_CON),
+ REGNAME(spm, 0x360, SGMII_0_TOP_PWR_CON),
+ REGNAME(spm, 0x35C, SGMII_1_PHY_PWR_CON),
+ REGNAME(spm, 0x364, SGMII_1_TOP_PWR_CON),
+ REGNAME(spm, 0x30C, PEXTP_D_2LX1_PHY_PWR_CON),
+ REGNAME(spm, 0x310, PEXTP_R_2LX1_PHY_PWR_CON),
+ REGNAME(spm, 0x314, PEXTP_R_1LX2_0P_PHY_PWR_CON),
+ REGNAME(spm, 0x318, PEXTP_R_1LX2_1P_PHY_PWR_CON),
+ REGNAME(spm, 0x368, DRAMC_MD32_PWR_CON),
+ /* APMIXEDSYS register */
+ REGNAME(apmixed, 0x204, ARMPLL_LL_CON0),
+ REGNAME(apmixed, 0x208, ARMPLL_LL_CON1),
+ REGNAME(apmixed, 0x20c, ARMPLL_LL_CON2),
+ REGNAME(apmixed, 0x210, ARMPLL_LL_CON3),
+ REGNAME(apmixed, 0x214, ARMPLL_LL_CON4),
+ REGNAME(apmixed, 0x218, CCIPLL_CON0),
+ REGNAME(apmixed, 0x21c, CCIPLL_CON1),
+ REGNAME(apmixed, 0x220, CCIPLL_CON2),
+ REGNAME(apmixed, 0x224, CCIPLL_CON3),
+ REGNAME(apmixed, 0x228, CCIPLL_CON4),
+ REGNAME(apmixed, 0x604, MPLL_CON0),
+ REGNAME(apmixed, 0x608, MPLL_CON1),
+ REGNAME(apmixed, 0x60c, MPLL_CON2),
+ REGNAME(apmixed, 0x610, MPLL_CON3),
+ REGNAME(apmixed, 0x614, MPLL_CON4),
+ REGNAME(apmixed, 0x404, MAINPLL_CON0),
+ REGNAME(apmixed, 0x408, MAINPLL_CON1),
+ REGNAME(apmixed, 0x40c, MAINPLL_CON2),
+ REGNAME(apmixed, 0x410, MAINPLL_CON3),
+ REGNAME(apmixed, 0x414, MAINPLL_CON4),
+ REGNAME(apmixed, 0x418, UNIVPLL_CON0),
+ REGNAME(apmixed, 0x41c, UNIVPLL_CON1),
+ REGNAME(apmixed, 0x420, UNIVPLL_CON2),
+ REGNAME(apmixed, 0x424, UNIVPLL_CON3),
+ REGNAME(apmixed, 0x428, UNIVPLL_CON4),
+ REGNAME(apmixed, 0x22c, MSDCPLL_CON0),
+ REGNAME(apmixed, 0x230, MSDCPLL_CON1),
+ REGNAME(apmixed, 0x234, MSDCPLL_CON2),
+ REGNAME(apmixed, 0x238, MSDCPLL_CON3),
+ REGNAME(apmixed, 0x23c, MSDCPLL_CON4),
+ REGNAME(apmixed, 0x42c, MMPLL_CON0),
+ REGNAME(apmixed, 0x430, MMPLL_CON1),
+ REGNAME(apmixed, 0x434, MMPLL_CON2),
+ REGNAME(apmixed, 0x438, MMPLL_CON3),
+ REGNAME(apmixed, 0x43c, MMPLL_CON4),
+ REGNAME(apmixed, 0x618, MFGPLL_CON0),
+ REGNAME(apmixed, 0x61c, MFGPLL_CON1),
+ REGNAME(apmixed, 0x620, MFGPLL_CON2),
+ REGNAME(apmixed, 0x624, MFGPLL_CON3),
+ REGNAME(apmixed, 0x628, MFGPLL_CON4),
+ REGNAME(apmixed, 0x454, APLL1_CON0),
+ REGNAME(apmixed, 0x458, APLL1_CON1),
+ REGNAME(apmixed, 0x45c, APLL1_CON2),
+ REGNAME(apmixed, 0x460, APLL1_CON3),
+ REGNAME(apmixed, 0x464, APLL1_CON4),
+ REGNAME(apmixed, 0x468, APLL1_CON5),
+ REGNAME(apmixed, 0x46c, APLL2_CON0),
+ REGNAME(apmixed, 0x470, APLL2_CON1),
+ REGNAME(apmixed, 0x474, APLL2_CON2),
+ REGNAME(apmixed, 0x478, APLL2_CON3),
+ REGNAME(apmixed, 0x47c, APLL2_CON4),
+ REGNAME(apmixed, 0x480, APLL2_CON5),
+ REGNAME(apmixed, 0x804, NET1PLL_CON0),
+ REGNAME(apmixed, 0x808, NET1PLL_CON1),
+ REGNAME(apmixed, 0x80c, NET1PLL_CON2),
+ REGNAME(apmixed, 0x810, NET1PLL_CON3),
+ REGNAME(apmixed, 0x814, NET1PLL_CON4),
+ REGNAME(apmixed, 0x818, NET2PLL_CON0),
+ REGNAME(apmixed, 0x81c, NET2PLL_CON1),
+ REGNAME(apmixed, 0x820, NET2PLL_CON2),
+ REGNAME(apmixed, 0x824, NET2PLL_CON3),
+ REGNAME(apmixed, 0x828, NET2PLL_CON4),
+ REGNAME(apmixed, 0x82c, WEDMCUPLL_CON0),
+ REGNAME(apmixed, 0x830, WEDMCUPLL_CON1),
+ REGNAME(apmixed, 0x834, WEDMCUPLL_CON2),
+ REGNAME(apmixed, 0x838, WEDMCUPLL_CON3),
+ REGNAME(apmixed, 0x83c, WEDMCUPLL_CON4),
+ REGNAME(apmixed, 0x840, MEDMCUPLL_CON0),
+ REGNAME(apmixed, 0x844, MEDMCUPLL_CON1),
+ REGNAME(apmixed, 0x848, MEDMCUPLL_CON2),
+ REGNAME(apmixed, 0x84c, MEDMCUPLL_CON3),
+ REGNAME(apmixed, 0x850, MEDMCUPLL_CON4),
+ REGNAME(apmixed, 0x240, SGMIIPLL_CON0),
+ REGNAME(apmixed, 0x244, SGMIIPLL_CON1),
+ REGNAME(apmixed, 0x248, SGMIIPLL_CON2),
+ REGNAME(apmixed, 0x24c, SGMIIPLL_CON3),
+ REGNAME(apmixed, 0x250, SGMIIPLL_CON4),
+ /* GCE register */
+ REGNAME(gce, 0xf0, GCE_CTL_INT0),
+ /* AUDIO register */
+ REGNAME(audsys, 0x0, AUDIO_TOP_0),
+ REGNAME(audsys, 0x4, AUDIO_TOP_1),
+ REGNAME(audsys, 0x8, AUDIO_TOP_2),
+ /* IMP_IIC_WRAP_E register */
+ REGNAME(impe, 0xe00, AP_CLOCK_CG_RO_EST),
+ /* MFGCFG register */
+ REGNAME(mfgcfg, 0x0, MFG_CG),
+ /* MMSYS CONFIG register */
+ REGNAME(mm, 0x100, MMSYS_CG_CON0),
+ REGNAME(mm, 0x110, MMSYS_CG_CON1),
+ REGNAME(mm, 0x120, MMSYS_CG_CON2),
+ {},
+};
+
+/*
+ * clkdbg vf table
+ */
+
+struct mtk_vf {
+ const char *name;
+ int freq_table[4];
+};
+
+#define MTK_VF_TABLE(_n, _freq0, _freq1, _freq2, _freq3) { \
+ .name = _n, \
+ .freq_table = {_freq0, _freq1, _freq2, _freq3}, \
+ }
+
+/*
+ * Opp0 : 0p75v
+ * Opp1 : 0p65v
+ * Opp2 : 0p60v
+ * Opp3 : 0p55v
+ *//*
+static struct mtk_vf vf_table[] = {
+ // Opp0, Opp1, Opp2, Opp3
+ MTK_VF_TABLE("axi_sel", 156000, 156000, 156000, 136500),
+ MTK_VF_TABLE("spm_sel", 78000, 78000, 78000, 78000),
+ MTK_VF_TABLE("bus_aximem_sel", 218400, 156000,156000, 156000),
+ MTK_VF_TABLE("mm_sel", 208000, 178285, 178285, 178285),
+ MTK_VF_TABLE("mfg_ref_sel", 416000, 416000, 218400, 218400),
+ MTK_VF_TABLE("uart_sel", 52000, 52000, 52000, 52000),
+ MTK_VF_TABLE("msdc50_0_hclk_sel", 273000, 273000, 273000, 273000),
+ MTK_VF_TABLE("msdc50_0_sel", 416000, 416000, 416000, 416000),
+ MTK_VF_TABLE("msdc30_1_sel", 208000, 208000, 208000, 208000),
+ MTK_VF_TABLE("audio_sel", 54600, 54600, 54600, 54600),
+ MTK_VF_TABLE("aud_intbus_sel", 136500, 136500, 136500, 136500),
+ MTK_VF_TABLE("aud_engen1_sel", 22579, 22579, 22579, 22579),
+ MTK_VF_TABLE("aud_engen2_sel", 24576, 24576,24576, 24576),
+ MTK_VF_TABLE("aud_1_sel", 180633, 180633, 180633, 180633),
+ MTK_VF_TABLE("aud_2_sel", 196608, 196608, 196608, 196608),
+ MTK_VF_TABLE("pwrap_ulposc_sel", 65000, 65000, 65000, 65000),
+ MTK_VF_TABLE("atb_sel", 273000, 273000, 273000, 273000),
+ MTK_VF_TABLE("pwrmcu_sel", 364000, 312000, 312000, 273000),
+ MTK_VF_TABLE("dbi_sel", 124800, 124800, 124800, 124800),
+ MTK_VF_TABLE("disp_pwm_sel", 130000, 130000, 130000, 130000),
+ MTK_VF_TABLE("usb_top_sel", 124800, 124800, 124800, 124800),
+ MTK_VF_TABLE("ssusb_xhci_sel", 124800, 124800, 124800, 124800),
+ MTK_VF_TABLE("i2c_sel", 124800, 124800, 124800, 124800),
+ MTK_VF_TABLE("tl_sel", 136500, 136500, 136500, 136500),
+ MTK_VF_TABLE("dpmaif_main_sel", 364000, 364000, 364000, 273000),
+ MTK_VF_TABLE("pwm_sel", 78000, 78000, 78000, 78000),
+ MTK_VF_TABLE("spmi_m_mst_sel", 32500, 32500, 32500, 32500),
+ MTK_VF_TABLE("spmi_p_mst_sel", 32500, 32500, 32500, 32500),
+ MTK_VF_TABLE("dvfsrc_sel", 26000, 26000, 26000, 26000),
+ MTK_VF_TABLE("mcupm_sel", 182000, 182000, 182000, 182000),
+ MTK_VF_TABLE("sflash_sel", 62400, 62400, 62400, 62400),
+ MTK_VF_TABLE("gcpu_sel", 416000, 364000, 364000, 273000),
+ MTK_VF_TABLE("spi_sel", 208000, 208000, 208000, 178285),
+ MTK_VF_TABLE("spis_sel", 416000, 416000, 312000, 104000),
+ MTK_VF_TABLE("ecc_sel", 312000, 242666, 242666, 136500),
+ MTK_VF_TABLE("nfi1x_sel", 182000, 182000, 182000, 182000),
+ MTK_VF_TABLE("spinfi_bclk_sel", 124800, 124800, 124800, 124800),
+ MTK_VF_TABLE("netsys_sel", 78000, 356571, 242666, 156000),
+ MTK_VF_TABLE("medsys_sel", 78000, 356571, 242666, 156000),
+ MTK_VF_TABLE("hsm_crypto_sel", 312000, 312000, 26000, 26000),
+ MTK_VF_TABLE("hsm_arc_sel", 26000, 26000, 182000, 182000),
+ MTK_VF_TABLE("eip97_sel", 800000, 546000, 364000, 218400),
+ MTK_VF_TABLE("snps_eth_312p5m_sel", 312500, 312500, 312500, 312500),
+ MTK_VF_TABLE("snps_eth_250m_sel", 250000, 250000, 250000, 250000),
+ MTK_VF_TABLE("snps_eth_62p4m_ptp_sel", 62400, 62400, 62400, 62400),
+ MTK_VF_TABLE("snps_eth_50m_rmii_sel", 50000, 50000, 50000, 50000),
+ MTK_VF_TABLE("netsys_500m_sel", 500000, 500000, 500000, 500000),
+ MTK_VF_TABLE("netsys_med_mcu_sel", 580000, 356571, 273000, 104000),
+ MTK_VF_TABLE("netsys_wed_mcu_sel", 760000, 436800, 364000, 182000),
+ MTK_VF_TABLE("netsys_2x_sel", 800000, 546000, 273000, 124800),
+ MTK_VF_TABLE("sgmii_sel", 325000, 325000, 325000, 325000),
+ MTK_VF_TABLE("sgmii_sbus_sel", 78000, 78000,78000, 78000),
+};*/
+
+/*
+ * clkdbg fmeter
+ */
+
+#define clk_readl(addr) readl(addr)
+#define clk_writel(addr, val) \
+ do { writel(val, addr); wmb(); } while (0) /* sync write */
+
+#define FMCLK2(_t, _i, _n, _o, _p) { .type = _t, \
+ .id = _i, .name = _n, .ofs = _o, .pdn = _p}
+#define FMCLK(_t, _i, _n) { .type = _t, .id = _i, .name = _n }
+
+static const struct fmeter_clk fclks[] = {
+ /* CKGEN Part */
+ FMCLK2(CKGEN, FM_AXI_CK, "fm_axi_ck", 0x0010, 7),
+ FMCLK2(CKGEN, FM_SPM_CK, "fm_spm_ck", 0x0010, 15),
+ FMCLK2(CKGEN, FM_BUS_CK, "fm_bus_ck", 0x0010, 23),
+ FMCLK2(CKGEN, FM_MM_CK, "fm_mm_ck", 0x0010, 31),
+ FMCLK2(CKGEN, FM_MFG_REF_CK, "fm_mfg_ref_ck", 0x0020, 7),
+ FMCLK2(CKGEN, FM_FUART_CK, "fm_fuart_ck", 0x0020, 15),
+ FMCLK2(CKGEN, FM_MSDC50_0_H_CK, "fm_msdc50_0_h_ck", 0x0020, 23),
+ FMCLK2(CKGEN, FM_MSDC50_0_CK, "fm_msdc50_0_ck", 0x0020, 31),
+ FMCLK2(CKGEN, FM_MSDC30_1_CK, "fm_msdc30_1_ck", 0x0030, 7),
+ FMCLK2(CKGEN, FM_AUDIO_CK, "fm_audio_ck", 0x0030, 15),
+ FMCLK2(CKGEN, FM_AUD_INTBUS_CK, "fm_aud_intbus_ck", 0x0030, 23),
+ FMCLK2(CKGEN, FM_AUD_ENGEN1_CK, "fm_aud_engen1_ck", 0x0030, 31),
+ FMCLK2(CKGEN, FM_AUD_ENGEN2_CK, "fm_aud_engen2_ck", 0x0040, 7),
+ FMCLK2(CKGEN, FM_AUD1_CK, "fm_aud1_ck", 0x0040, 15),
+ FMCLK2(CKGEN, FM_AUD2_CK, "fm_aud2_ck", 0x0040, 23),
+ FMCLK2(CKGEN, FM_FPWRAP_ULPOSC_CK, "fm_fpwrap_ulposc_ck", 0x0040, 31),
+ FMCLK2(CKGEN, FM_ATB_CK, "fm_atb_ck", 0x0050, 7),
+ FMCLK2(CKGEN, FM_PWRMCU_CK, "fm_pwrmcu_ck", 0x0050, 15),
+ FMCLK2(CKGEN, FM_DBI_CK, "fm_dbi_ck", 0x0050, 23),
+ FMCLK2(CKGEN, FM_FDISP_PWM_CK, "fm_fdisp_pwm_ck", 0x0050, 31),
+ FMCLK2(CKGEN, FM_FUSB_CK, "fm_fusb_ck", 0x0060, 7),
+ FMCLK2(CKGEN, FM_FSSUSB_XHCI_CK, "fm_fssusb_xhci_ck", 0x0060, 15),
+ FMCLK2(CKGEN, FM_I2C_CK, "fm_i2c_ck", 0x0060, 23),
+ FMCLK2(CKGEN, FM_TL_CK, "fm_tl_ck", 0x0060, 31),
+ FMCLK2(CKGEN, FM_DPMAIF_MAIN_CK, "fm_dpmaif_main_ck", 0x0070, 7),
+ FMCLK2(CKGEN, FM_PWM_CK, "fm_pwm_ck", 0x0070, 15),
+ FMCLK2(CKGEN, FM_SPMI_M_MST_CK, "fm_spmi_m_mst_ck", 0x0070, 23),
+ FMCLK2(CKGEN, FM_SPMI_P_MST_CK, "fm_spmi_p_mst_ck", 0x0070, 31),
+ FMCLK2(CKGEN, FM_DVFSRC_CK, "fm_dvfsrc_ck", 0x0080, 7),
+ FMCLK2(CKGEN, FM_MCUPM_CK, "fm_mcupm_ck", 0x0080, 15),
+ FMCLK2(CKGEN, FM_SFLASH_CK, "fm_sflash_ck", 0x0080, 23),
+ FMCLK2(CKGEN, FM_GCPU_CK, "fm_gcpu_ck", 0x0080, 31),
+ FMCLK2(CKGEN, FM_SPI_CK, "fm_spi_ck", 0x0090, 7),
+ FMCLK2(CKGEN, FM_SPIS_CK, "fm_spis_ck", 0x0090, 15),
+ FMCLK2(CKGEN, FM_ECC_CK, "fm_ecc_ck", 0x0090, 23),
+ FMCLK2(CKGEN, FM_NFI1X_CK, "fm_nfi1x_ck", 0x0090, 31),
+ FMCLK2(CKGEN, FM_SPINFI_BCLK_CK, "fm_spinfi_bclk_ck", 0x00A0, 7),
+ FMCLK2(CKGEN, FM_NETSYS_CK, "fm_netsys_ck", 0x00A0, 15),
+ FMCLK2(CKGEN, FM_MEDSYS_CK, "fm_medsys_ck", 0x00A0, 23),
+ FMCLK2(CKGEN, FM_HSM_CRYPTO_CK, "fm_hsm_crypto_ck", 0x00A0, 31),
+ FMCLK2(CKGEN, FM_HSM_ARC_CK, "fm_hsm_arc_ck", 0x00B0, 7),
+ FMCLK2(CKGEN, FM_EIP97_CK, "fm_eip97_ck", 0x00B0, 15),
+ FMCLK2(CKGEN, FM_SNPS_ETH_312P5M_CK, "fm_snps_eth_312p5m_ck", 0x00B0, 23),
+ FMCLK2(CKGEN, FM_SNPS_ETH_250M_CK, "fm_snps_eth_250m_ck", 0x00B0, 31),
+ FMCLK2(CKGEN, FM_SNPS_PTP_CK, "fm_snps_ptp_ck", 0x00C0, 7),
+ FMCLK2(CKGEN, FM_SNPS_ETH_50M_RMII_CK, "fm_snps_eth_50m_rmii_ck", 0x00C0, 15),
+ FMCLK2(CKGEN, FM_NETSYS_500M_CK, "fm_netsys_500m_ck", 0x00C0, 23),
+ FMCLK2(CKGEN, FM_NETSYS_MED_MCU_CK, "fm_netsys_med_mcu_ck", 0x00C0, 31),
+ FMCLK2(CKGEN, FM_NETSYS_WED_MCU_CK, "fm_netsys_wed_mcu_ck", 0x00D0, 7),
+ FMCLK2(CKGEN, FM_NETSYS_2X_CK, "fm_netsys_2x_ck", 0x00D0, 15),
+ FMCLK2(CKGEN, FM_SGMII_CK, "fm_sgmii_ck", 0x00D0, 23),
+ FMCLK2(CKGEN, FM_SGMII_SBUS_CK, "fm_sgmii_sbus_ck", 0x00D0, 31),
+ /* ABIST Part */
+ FMCLK(ABIST, FM_APLL1_CK, "fm_apll1_ck"),
+ FMCLK(ABIST, FM_APLL2_CK, "fm_apll2_ck"),
+ FMCLK(ABIST, FM_APPLLGP_MON_FM_CK, "fm_appllgp_mon_fm_ck"),
+ FMCLK(ABIST, FM_ARMPLL_LL_CK, "fm_armpll_ll_ck"),
+ FMCLK(ABIST, FM_CCIPLL_CK, "fm_ccipll_ck"),
+ FMCLK(ABIST, FM_NET1PLL_CK, "fm_net1pll_ck"),
+ FMCLK(ABIST, FM_NET2PLL_CK, "fm_net2pll_ck"),
+ FMCLK(ABIST, FM_WEDMCUPLL_CK, "fm_wedmcupll_ck"),
+ FMCLK(ABIST, FM_MEDMCUPLL_CK, "fm_medmcupll_ck"),
+ FMCLK(ABIST, FM_SGMIIPLL_CK, "fm_sgmiipll_ck"),
+ FMCLK(ABIST, FM_SNPSETHPLL_CK, "fm_snpsethpll_ck"),
+ FMCLK(ABIST, FM_DSI0_LNTC_DSICLK, "fm_dsi0_lntc_dsiclk"),
+ FMCLK(ABIST, FM_DSI0_MPPLL_TST_CK, "fm_dsi0_mppll_tst_ck"),
+ FMCLK(ABIST, FM_MDPLL1_FS26M_DRF_GUIDE, "fm_mdpll1_fs26m_drf_guide"),
+ FMCLK(ABIST, FM_MFG_CK, "fm_mfg_ck"),
+ FMCLK(ABIST, FM_MAINPLL_CK, "fm_mainpll_ck"),
+ FMCLK(ABIST, FM_MDPLL1_FS26M_GUIDE, "fm_mdpll1_fs26m_guide"),
+ FMCLK(ABIST, FM_MFGPLL_CK, "fm_mfgpll_ck"),
+ FMCLK(ABIST, FM_MMPLL_CK, "fm_mmpll_ck"),
+ FMCLK(ABIST, FM_MMPLL_D3_CK, "fm_mmpll_d3_ck"),
+ FMCLK(ABIST, FM_MPLL_CK, "fm_mpll_ck"),
+ FMCLK(ABIST, FM_MSDCPLL_CK, "fm_msdcpll_ck"),
+ FMCLK(ABIST, FM_RCLRPLL_DIV4_CK, "fm_rclrpll_div4_ck"),
+ FMCLK(ABIST, FM_RPHYPLL_DIV4_CK, "fm_rphypll_div4_ck"),
+ FMCLK(ABIST, FM_ULPOSC_CK, "fm_ulposc_ck"),
+ FMCLK(ABIST, FM_UNIVPLL_CK, "fm_univpll_ck"),
+ FMCLK(ABIST, FMEM_AFT_CH0, "fmem_aft_ch0"),
+ FMCLK(ABIST, FMEM_AFT_CH1, "fmem_aft_ch1"),
+ FMCLK(ABIST, FM_TRNG_FREQ_DEBUG_OUT0, "fm_trng_freq_debug_out0"),
+ FMCLK(ABIST, FM_TRNG_FREQ_DEBUG_OUT1, "fm_trng_freq_debug_out1"),
+ FMCLK(ABIST, FMEM_BFE_CH0, "fmem_bfe_ch0"),
+ FMCLK(ABIST, FMEM_BFE_CH1, "fmem_bfe_ch1"),
+ FMCLK(ABIST, FM_466M_FMEM_INFRASYS, "fm_466m_fmem_infrasys"),
+ FMCLK(ABIST, FM_MCUSYS_ARM_OUT_ALL, "fm_mcusys_arm_out_all"),
+ FMCLK(ABIST, FM_RTC32K_I_VAO, "fm_rtc32k_i_vao"),
+ /* ABIST_2 Part */
+ FMCLK(ABIST_2, FM_MCUPM_CK, "fm_mcupm_ck"),
+ FMCLK(ABIST_2, FM_SFLASH_CK, "fm_sflash_ck"),
+ FMCLK(ABIST_2, FM_UNIPLL_SES_CK, "fm_unipll_ses_ck"),
+ FMCLK(ABIST_2, FM_ULPOSC_CK, "fm_ulposc_ck"),
+ FMCLK(ABIST_2, FM_ULPOSC_CORE_CK, "fm_ulposc_core_ck"),
+ FMCLK(ABIST_2, FM_SRCK_CK, "fm_srck_ck"),
+ FMCLK(ABIST_2, FM_MAINPLL_H728M_CK, "fm_mainpll_h728m_ck"),
+ FMCLK(ABIST_2, FM_MAINPLL_H546M_CK, "fm_mainpll_h546m_ck"),
+ FMCLK(ABIST_2, FM_MAINPLL_H436P8M_CK, "fm_mainpll_h436p8m_ck"),
+ FMCLK(ABIST_2, FM_MAINPLL_H364M_CK, "fm_mainpll_h364m_ck"),
+ FMCLK(ABIST_2, FM_MAINPLL_H312M_CK, "fm_mainpll_h312m_ck"),
+ FMCLK(ABIST_2, FM_UNIVPLL_1248M_CK, "fm_univpll_1248m_ck"),
+ FMCLK(ABIST_2, FM_UNIVPLL_832M_CK, "fm_univpll_832m_ck"),
+ FMCLK(ABIST_2, FM_UNIVPLL_624M_CK, "fm_univpll_624m_ck"),
+ FMCLK(ABIST_2, FM_UNIVPLL_499M_CK, "fm_univpll_499m_ck"),
+ FMCLK(ABIST_2, FM_UNIVPLL_416M_CK, "fm_univpll_416m_ck"),
+ FMCLK(ABIST_2, FM_UNIVPLL_356P6M_CK, "fm_univpll_356p6m_ck"),
+ FMCLK(ABIST_2, FM_MMPLL_D3_CK, "fm_mmpll_d3_ck"),
+ FMCLK(ABIST_2, FM_MMPLL_D4_CK, "fm_mmpll_d4_ck"),
+ FMCLK(ABIST_2, FM_MMPLL_D5_CK, "fm_mmpll_d5_ck"),
+ FMCLK(ABIST_2, FM_MMPLL_D6_CK, "fm_mmpll_d6_ck"),
+ FMCLK(ABIST_2, FM_MMPLL_D7_CK, "fm_mmpll_d7_ck"),
+ FMCLK(ABIST_2, FM_MMPLL_D9_CK, "fm_mmpll_d9_ck"),
+ FMCLK(ABIST_2, FM_NET1PLL_CK, "fm_net1pll_ck"),
+ FMCLK(ABIST_2, FM_NET2PLL_CK, "fm_net2pll_ck"),
+ FMCLK(ABIST_2, FM_WEDMCUPLL_CK, "fm_wedmcupll_ck"),
+ FMCLK(ABIST_2, FM_MEDMCUPLL_CK, "fm_medmcupll_ck"),
+ FMCLK(ABIST_2, FM_SGMIIPLL_CK, "fm_sgmiipll_ck"),
+ {},
+};
+
+#define _CKGEN(x) (rb[top].virt + (x))
+#define CLK_CFG_0 _CKGEN(0x10)
+#define CLK_CFG_1 _CKGEN(0x20)
+#define CLK_CFG_2 _CKGEN(0x30)
+#define CLK_CFG_3 _CKGEN(0x40)
+#define CLK_CFG_4 _CKGEN(0x50)
+#define CLK_CFG_5 _CKGEN(0x60)
+#define CLK_CFG_6 _CKGEN(0x70)
+#define CLK_CFG_7 _CKGEN(0x80)
+#define CLK_CFG_8 _CKGEN(0x90)
+#define CLK_CFG_9 _CKGEN(0xA0)
+#define CLK_CFG_10 _CKGEN(0xB0)
+#define CLK_CFG_11 _CKGEN(0xC0)
+#define CLK_CFG_12 _CKGEN(0xD0)
+//#define CLK_CFG_13 _CKGEN(0xE0)
+#define CLK_MISC_CFG_0 _CKGEN(0x140)
+#define CLK_DBG_CFG _CKGEN(0x17C)
+#define CLK26CALI_0 _CKGEN(0x220)
+#define CLK26CALI_1 _CKGEN(0x224)
+
+/*
+ * clkdbg dump_clks
+ */
+
+ static const char * const *get_pwr_names(void)
+{
+ static const char * const pwr_names[] = {
+ [0] = "md1",
+ [1] = "conn",
+ [2] = "mfg0",
+ [3] = "pextp_d_2lx1_phy",
+ [4] = "pextp_r_2lx1_phy",
+ [5] = "pextp_r_1lx2_0p_phy",
+ [6] = "pextp_r_1lx2_1p_phy",
+ [7] = "ssusb_phy",
+ [8] = "sgmii_0_phy",
+ [9] = "infra",
+ [10] = "sgmii_1_phy",
+ [11] = "dpy",
+ [12] = "pextp_d_2lx1",
+ [13] = "pextp_r_2lx1",
+ [14] = "pextp_r_1lx2",
+ [15] = "eth",
+ [16] = "ssusb",
+ [17] = "sgmii_0_top",
+ [18] = "sgmii_1_top",
+ [19] = "netsys",
+ [20] = "dis",
+ [21] = "audio",
+ [22] = "eip97",
+ [23] = "hsmtop",
+ [24] = "dramc_md32",
+ [25] = "(Reserved)",
+ [26] = "(Reserved)",
+ [27] = "(Reserved)",
+ [28] = "dpy2",
+ [29] = "mcupm",
+ [30] = "msdc",
+ [31] = "peri",
+ };
+ return pwr_names;
+}
+
+ static const char * const *get_all_clk_names(void)
+{
+ return get_mt6880_all_clk_names();
+}
+
+ static const struct regname *get_all_regnames(void)
+{
+ return rn;
+}
+
+static void __init init_regbase(void)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(rb); i++) {
+ if (!rb[i].phys)
+ continue;
+ rb[i].virt = ioremap_nocache(rb[i].phys, 0x1000);
+ }
+}
+
+unsigned int mt_get_abist_freq(unsigned int ID)
+{
+ int output = 0, i = 0;
+ unsigned long flags;
+ unsigned int temp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1 = 0;
+ fmeter_lock(flags);
+ while (clk_readl(CLK26CALI_0) & 0x1000) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ ;
+ clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
+ clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFC0FFFC)|(ID << 16));
+ clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
+ clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (3 << 24));
+ clk26cali_1 = clk_readl(CLK26CALI_1);
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+ /* wait frequency meter finish */
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ /* illegal pass */
+ if (i == 0) {
+ clk_writel(CLK26CALI_0, 0x0000);
+ //re-trigger
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ }
+ temp = clk_readl(CLK26CALI_1) & 0xFFFF;
+ output = (temp * 26000) / 1024;
+ clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
+ clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
+ /*clk_writel(CLK26CALI_0, clk26cali_0);*/
+ /*clk_writel(CLK26CALI_1, clk26cali_1);*/
+ clk_writel(CLK26CALI_0, 0x0000);
+ fmeter_unlock(flags);
+ if (i > 30)
+ return 0;
+ else {
+ if ((output * 4) < 25000) {
+ pr_notice("%s: CLK_DBG_CFG = 0x%x, CLK_MISC_CFG_0 = 0x%x, CLK26CALI_0 = 0x%x, CLK26CALI_1 = 0x%x\n",
+ __func__,
+ clk_readl(CLK_DBG_CFG),
+ clk_readl(CLK_MISC_CFG_0),
+ clk_readl(CLK26CALI_0),
+ clk_readl(CLK26CALI_1));
+ }
+ return (output * 4);
+ }
+}
+
+static unsigned int mt_get_abist2_freq(unsigned int ID)
+{
+ int output = 0, i = 0;
+ unsigned long flags;
+ unsigned int temp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1 = 0;
+ fmeter_lock(flags);
+ while (clk_readl(CLK26CALI_0) & 0x1000) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ ;
+ clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
+ clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xC0FFFFFC)
+ | (ID << 24) | (0x2));
+ clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
+ clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (1 << 24));
+ clk26cali_1 = clk_readl(CLK26CALI_1);
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+ // wait frequency meter finish
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ // illegal pass
+ if (i == 0) {
+ clk_writel(CLK26CALI_0, 0x0000);
+ //re-trigger
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ }
+ temp = clk_readl(CLK26CALI_1) & 0xFFFF;
+ output = (temp * 26000) / 1024;
+ clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
+ clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
+ //clk_writel(CLK26CALI_0, clk26cali_0);
+ //clk_writel(CLK26CALI_1, clk26cali_1);
+ clk_writel(CLK26CALI_0, 0x0000);
+ //pr_debug("%s = %d Khz\n", abist_array[ID-1], output);
+ fmeter_unlock(flags);
+ if (i > 30)
+ return 0;
+ else
+ return (output * 2);
+}
+
+static unsigned int check_mux_pdn(unsigned int ID)
+{
+ int i;
+ if ((ID > 0) && (ID < 64)) {
+ for (i = 0; i < ARRAY_SIZE(fclks); i++)
+ if (fclks[i].id == ID)
+ break;
+ if (i >= ARRAY_SIZE(fclks))
+ return 1;
+ if ((clk_readl(rb[top].virt + fclks[i].ofs)
+ & BIT(fclks[i].pdn)))
+ return 1;
+ else
+ return 0;
+ } else
+ return 1;
+}
+
+unsigned int mt_get_ckgen_freq(unsigned int ID)
+{
+ int output = 0, i = 0;
+ unsigned int temp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1 = 0;
+ unsigned long flags;
+ if (check_mux_pdn(ID)) {
+ pr_notice("ID-%d: MUX PDN, return 0.\n", ID);
+ return 0;
+ }
+ fmeter_lock(flags);
+ while (clk_readl(CLK26CALI_0) & 0x1000) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
+ clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFFFC0FC)|(ID << 8)|(0x1));
+ clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
+ clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (3 << 24));
+ clk26cali_1 = clk_readl(CLK26CALI_1);
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+ /* wait frequency meter finish */
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ /* illegal pass */
+ if (i == 0) {
+ clk_writel(CLK26CALI_0, 0x0000);
+ //re-trigger
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ }
+ temp = clk_readl(CLK26CALI_1) & 0xFFFF;
+ output = (temp * 26000) / 1024;
+ clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
+ clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
+ /*clk_writel(CLK26CALI_0, clk26cali_0);*/
+ /*clk_writel(CLK26CALI_1, clk26cali_1);*/
+ clk_writel(CLK26CALI_0, 0x0000);
+ fmeter_unlock(flags);
+ /*print("ckgen meter[%d] = %d Khz\n", ID, output);*/
+ if (i > 30)
+ return 0;
+ else {
+ if ((output * 4) < 25000) {
+ pr_notice("%s: CLK_DBG_CFG = 0x%x, CLK_MISC_CFG_0 = 0x%x, CLK26CALI_0 = 0x%x, CLK26CALI_1 = 0x%x\n",
+ __func__,
+ clk_readl(CLK_DBG_CFG),
+ clk_readl(CLK_MISC_CFG_0),
+ clk_readl(CLK26CALI_0),
+ clk_readl(CLK26CALI_1));
+ }
+ return (output * 4);
+ }
+}
+
+ static u32 fmeter_freq_op(const struct fmeter_clk *fclk)
+{
+ if (fclk->type == ABIST)
+ return mt_get_abist_freq(fclk->id);
+ else if (fclk->type == ABIST_2)
+ return mt_get_abist2_freq(fclk->id);
+ else if (fclk->type == CKGEN)
+ return mt_get_ckgen_freq(fclk->id);
+ return 0;
+}
+
+static const struct fmeter_clk *get_all_fmeter_clks(void)
+{
+ return fclks;
+}
+
+void setup_provider_clk(struct provider_clk *pvdck)
+{
+ static const struct {
+ const char *pvdname;
+ u32 pwr_mask;
+ } pvd_pwr_mask[] = {
+ };
+
+ int i;
+ const char *pvdname = pvdck->provider_name;
+
+ if (!pvdname)
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(pvd_pwr_mask); i++) {
+ if (strcmp(pvdname, pvd_pwr_mask[i].pvdname) == 0) {
+ pvdck->pwr_mask = pvd_pwr_mask[i].pwr_mask;
+ return;
+ }
+ }
+}
+
+/*
+ * chip_ver functions
+ */
+/*
+static int clkdbg_chip_ver(struct seq_file *s, void *v)
+{
+ static const char * const sw_ver_name[] = {
+ "CHIP_SW_VER_01",
+ "CHIP_SW_VER_02",
+ "CHIP_SW_VER_03",
+ "CHIP_SW_VER_04",
+ };
+
+ seq_printf(s, "mt_get_chip_sw_ver(): %d (%s)\n", 0, sw_ver_name[0]);
+
+ return 0;
+}*/
+
+/*
+ * init functions
+ */
+
+static struct clkdbg_ops clkdbg_mt6880_ops = {
+ .get_all_fmeter_clks = get_all_fmeter_clks,
+ .prepare_fmeter = NULL,
+ .unprepare_fmeter = NULL,
+ .fmeter_freq = fmeter_freq_op,
+ .get_all_regnames = get_all_regnames,
+ .get_all_clk_names = get_all_clk_names,
+ .get_pwr_names = get_pwr_names,
+ .setup_provider_clk = setup_provider_clk,
+};
+
+static void __init init_custom_cmds(void)
+{
+ /*static const struct cmd_fn cmds[] = {
+ CMDFN("chip_ver", clkdbg_chip_ver),
+ {}
+ };
+
+ set_custom_cmds(cmds);*/
+}
+
+static int __init clkdbg_mt6880_init(void)
+{
+/* if (!of_machine_is_compatible("mediatek,MT6880"))
+ return -ENODEV;
+*/
+ init_regbase();
+
+ init_custom_cmds();
+ set_clkdbg_ops(&clkdbg_mt6880_ops);
+
+#ifdef CONFIG_MTK_DEVAPC
+// register_devapc_vio_callback(&devapc_vio_handle);
+#endif
+
+#if DUMP_INIT_STATE
+ print_regs();
+ print_fmeter_all();
+#endif /* DUMP_INIT_STATE */
+
+ return 0;
+}
+subsys_initcall(clkdbg_mt6880_init);
+
+/*
+ * MT6880: for mtcmos debug
+ */
+static bool is_valid_reg(void __iomem *addr)
+{
+#ifdef CONFIG_64BIT
+ return ((u64)addr & 0xf0000000) != 0UL ||
+ (((u64)addr >> 32U) & 0xf0000000) != 0UL;
+#else
+ return ((u32)addr & 0xf0000000) != 0U;
+#endif
+}
+
+void print_subsys_reg(enum dbg_sys_id id)
+{
+ struct regbase *rb_dump;
+ const struct regname *rns = &rn[0];
+ int i;
+ /*if (rns == NULL)
+ return;*/
+ if (id >= dbg_sys_num || id < 0) {
+ pr_info("wrong id:%d\n", id);
+ return;
+ }
+ rb_dump = &rb[id];
+ for (i = 0; i < ARRAY_SIZE(rn) - 1; i++, rns++) {
+ if (!is_valid_reg(ADDR(rns)))
+ return;
+ /* filter out the subsys that we don't want */
+ if (rns->base != rb_dump)
+ continue;
+ pr_info("%-18s: [0x%08x] = 0x%08x\n",
+ rns->name, PHYSADDR(rns), clk_readl(ADDR(rns)));
+ }
+}
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt6880.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt6880.h
new file mode 100755
index 0000000..0fa1e3b
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt6880.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+
+#ifndef __DRV_CLKDBG_MT6880_H
+#define __DRV_CLKDBG_MT6880_H
+
+enum dbg_sys_id {
+ top,
+ dbgsys_dem,
+ ifrao,
+ infracfg_ao_bus,
+ peri,
+ spm,
+ apmixed,
+ gce,
+ audsys,
+ impe,
+ mfgcfg,
+ mm,
+ dbg_sys_num,
+};
+
+extern void subsys_if_on(void);
+
+extern unsigned int mt_get_ckgen_freq(unsigned int ID);
+
+/*ram console api*/
+#ifdef CONFIG_MTK_RAM_CONSOLE
+extern void aee_rr_rec_clk(int id, u32 val);
+#endif
+
+extern const char * const *get_mt6880_all_clk_names(void);
+extern void print_enabled_clks_once(void);
+extern void print_subsys_reg(enum dbg_sys_id id);
+
+#endif /* __DRV_CLKDBG_MT6758_H */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt6890.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt6890.c
new file mode 100755
index 0000000..cb718fb
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt6890.c
@@ -0,0 +1,874 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2019 MediaTek Inc.
+
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/seq_file.h>
+#include <linux/delay.h>
+
+#ifdef CONFIG_MTK_DEVAPC
+#include <linux/soc/mediatek/devapc_public.h>
+#endif
+#include "clk-mux.h"
+#include "clkdbg.h"
+#include "clkdbg-mt6890.h"
+#include "clk-mt6890-fmeter.h"
+
+#define DUMP_INIT_STATE 0
+
+/*
+ * clkdbg dump_regs
+ */
+
+#define REGBASE_V(_phys, _id_name, _pg) { .phys = _phys, \
+ .name = #_id_name, .pg = _pg}
+
+static DEFINE_SPINLOCK(meter_lock);
+#define fmeter_lock(flags) spin_lock_irqsave(&meter_lock, flags)
+#define fmeter_unlock(flags) spin_unlock_irqrestore(&meter_lock, flags)
+/*
+ * checkpatch.pl ERROR:COMPLEX_MACRO
+ *
+ * #define REGBASE(_phys, _id_name) [_id_name] = REGBASE_V(_phys, _id_name)
+ */
+
+static struct regbase rb[] = {
+ [top] = REGBASE_V(0x10000000, top, NULL),
+ [dbgsys_dem] = REGBASE_V(0x0d0a0000, dbgsys_dem, NULL),
+ [ifrao] = REGBASE_V(0x10001000, ifrao, NULL),
+ [infracfg_ao_bus] = REGBASE_V(0x10001000, infracfg_ao_bus, NULL),
+ [peri] = REGBASE_V(0x10003000, peri, NULL),
+ [spm] = REGBASE_V(0x10006000, spm, NULL),
+ [apmixed] = REGBASE_V(0x1000C000, apmixed, NULL),
+ [gce] = REGBASE_V(0x10228000, gce, NULL),
+ [audsys] = REGBASE_V(0x11210000, audsys, "MT6890_POWER_DOMAIN_AUDIO"),
+ [impe] = REGBASE_V(0x11c46000, impe, NULL),
+ [mfgcfg] = REGBASE_V(0x13fbf000, mfgcfg, "MT6890_POWER_DOMAIN_MFG0"),
+ [mm] = REGBASE_V(0x14000000, mm, "MT6890_POWER_DOMAIN_DIS"),
+ {},
+};
+
+#define REGNAME(_base, _ofs, _name) \
+ { .base = &rb[_base], .ofs = _ofs, .name = #_name }
+
+static struct regname rn[] = {
+ /* TOPCKGEN register */
+ REGNAME(top, 0x0010, CLK_CFG_0),
+ REGNAME(top, 0x0020, CLK_CFG_1),
+ REGNAME(top, 0x0030, CLK_CFG_2),
+ REGNAME(top, 0x0040, CLK_CFG_3),
+ REGNAME(top, 0x0050, CLK_CFG_4),
+ REGNAME(top, 0x0060, CLK_CFG_5),
+ REGNAME(top, 0x0070, CLK_CFG_6),
+ REGNAME(top, 0x0080, CLK_CFG_7),
+ REGNAME(top, 0x0090, CLK_CFG_8),
+ REGNAME(top, 0x00A0, CLK_CFG_9),
+ REGNAME(top, 0x00B0, CLK_CFG_10),
+ REGNAME(top, 0x00C0, CLK_CFG_11),
+ REGNAME(top, 0x00D0, CLK_CFG_12),
+ REGNAME(top, 0x0320, CLK_AUDDIV_0),
+ REGNAME(top, 0x0328, CLK_AUDDIV_2),
+ REGNAME(top, 0x0334, CLK_AUDDIV_3),
+ /* DBGSYS_DEM register */
+ REGNAME(dbgsys_dem, 0x70, ATB),
+ REGNAME(dbgsys_dem, 0x2c, DBGBUSCLK_EN),
+ REGNAME(dbgsys_dem, 0x30, DBGSYSCLK_EN),
+ /* INFRACFG_AO register */
+ REGNAME(ifrao, 0x70, INFRA_BUS_DCM_CTRL),
+ REGNAME(ifrao, 0x90, MODULE_SW_CG_0),
+ REGNAME(ifrao, 0x94, MODULE_SW_CG_1),
+ REGNAME(ifrao, 0xac, MODULE_SW_CG_2),
+ REGNAME(ifrao, 0xc8, MODULE_SW_CG_3),
+ REGNAME(ifrao, 0xe8, MODULE_SW_CG_4),
+ REGNAME(ifrao, 0x74, PERI_BUS_DCM_CTRL),
+ /* INFRACFG_AO_BUS register */
+ REGNAME(infracfg_ao_bus, 0x0710, INFRA_TOPAXI_PROTECTEN_2),
+ REGNAME(infracfg_ao_bus, 0x0720, INFRA_TOPAXI_PROTECTEN_STA0_2),
+ REGNAME(infracfg_ao_bus, 0x0724, INFRA_TOPAXI_PROTECTEN_STA1_2),
+ REGNAME(infracfg_ao_bus, 0x0220, INFRA_TOPAXI_PROTECTEN),
+ REGNAME(infracfg_ao_bus, 0x0224, INFRA_TOPAXI_PROTECTEN_STA0),
+ REGNAME(infracfg_ao_bus, 0x0228, INFRA_TOPAXI_PROTECTEN_STA1),
+ REGNAME(infracfg_ao_bus, 0x0250, INFRA_TOPAXI_PROTECTEN_1),
+ REGNAME(infracfg_ao_bus, 0x0254, INFRA_TOPAXI_PROTECTEN_STA0_1),
+ REGNAME(infracfg_ao_bus, 0x0258, INFRA_TOPAXI_PROTECTEN_STA1_1),
+ REGNAME(infracfg_ao_bus, 0x0B80, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR),
+ REGNAME(infracfg_ao_bus, 0x0B8c, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA0),
+ REGNAME(infracfg_ao_bus, 0x0B90, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA1),
+ REGNAME(infracfg_ao_bus, 0x0BA0, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1),
+ REGNAME(infracfg_ao_bus, 0x0BAc, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_STA0),
+ REGNAME(infracfg_ao_bus, 0x0BB0, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_STA1),
+ REGNAME(infracfg_ao_bus, 0x0BB4, INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR),
+ REGNAME(infracfg_ao_bus, 0x0BC0, INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_STA0),
+ REGNAME(infracfg_ao_bus, 0x0BC4, INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_STA1),
+ REGNAME(infracfg_ao_bus, 0x02D0, INFRA_TOPAXI_PROTECTEN_MM),
+ REGNAME(infracfg_ao_bus, 0x02E8, INFRA_TOPAXI_PROTECTEN_MM_STA0),
+ REGNAME(infracfg_ao_bus, 0x02EC, INFRA_TOPAXI_PROTECTEN_MM_STA1),
+ /* PERICFG register */
+ REGNAME(peri, 0x20c, PERIAXI_SI0_CTL),
+ /* SPM register */
+ REGNAME(spm, 0x308, MFG0_PWR_CON),
+ REGNAME(spm, 0x324, IFR_PWR_CON),
+ REGNAME(spm, 0x32C, DPY_PWR_CON),
+ REGNAME(spm, 0x330, PEXTP_D_2LX1_PWR_CON),
+ REGNAME(spm, 0x334, PEXTP_R_2LX1_PWR_CON),
+ REGNAME(spm, 0x338, PEXTP_R_1LX2_PWR_CON),
+ REGNAME(spm, 0x33C, ETH_PWR_CON),
+ REGNAME(spm, 0x34C, NETSYS_PWR_CON),
+ REGNAME(spm, 0x350, DIS_PWR_CON),
+ REGNAME(spm, 0x354, AUDIO_PWR_CON),
+ REGNAME(spm, 0x300, MD1_PWR_CON),
+ REGNAME(spm, 0x328, EIP97_PWR_CON),
+ REGNAME(spm, 0x304, CONN_PWR_CON),
+ REGNAME(spm, 0x3C4, DPY2_PWR_CON),
+ REGNAME(spm, 0x3C0, MCUPM_PWR_CON),
+ REGNAME(spm, 0x3A4, MSDC_PWR_CON),
+ REGNAME(spm, 0x3D0, PERI_PWR_CON),
+ REGNAME(spm, 0x344, HSMTOP_PWR_CON),
+ REGNAME(spm, 0x340, SSUSB_PWR_CON),
+ REGNAME(spm, 0x31C, SSUSB_PHY_PWR_CON),
+ REGNAME(spm, 0x358, SGMII_0_PHY_PWR_CON),
+ REGNAME(spm, 0x360, SGMII_0_TOP_PWR_CON),
+ REGNAME(spm, 0x35C, SGMII_1_PHY_PWR_CON),
+ REGNAME(spm, 0x364, SGMII_1_TOP_PWR_CON),
+ REGNAME(spm, 0x30C, PEXTP_D_2LX1_PHY_PWR_CON),
+ REGNAME(spm, 0x310, PEXTP_R_2LX1_PHY_PWR_CON),
+ REGNAME(spm, 0x314, PEXTP_R_1LX2_0P_PHY_PWR_CON),
+ REGNAME(spm, 0x318, PEXTP_R_1LX2_1P_PHY_PWR_CON),
+ REGNAME(spm, 0x368, DRAMC_MD32_PWR_CON),
+ /* APMIXEDSYS register */
+ REGNAME(apmixed, 0x204, ARMPLL_LL_CON0),
+ REGNAME(apmixed, 0x208, ARMPLL_LL_CON1),
+ REGNAME(apmixed, 0x20c, ARMPLL_LL_CON2),
+ REGNAME(apmixed, 0x210, ARMPLL_LL_CON3),
+ REGNAME(apmixed, 0x214, ARMPLL_LL_CON4),
+ REGNAME(apmixed, 0x218, CCIPLL_CON0),
+ REGNAME(apmixed, 0x21c, CCIPLL_CON1),
+ REGNAME(apmixed, 0x220, CCIPLL_CON2),
+ REGNAME(apmixed, 0x224, CCIPLL_CON3),
+ REGNAME(apmixed, 0x228, CCIPLL_CON4),
+ REGNAME(apmixed, 0x604, MPLL_CON0),
+ REGNAME(apmixed, 0x608, MPLL_CON1),
+ REGNAME(apmixed, 0x60c, MPLL_CON2),
+ REGNAME(apmixed, 0x610, MPLL_CON3),
+ REGNAME(apmixed, 0x614, MPLL_CON4),
+ REGNAME(apmixed, 0x404, MAINPLL_CON0),
+ REGNAME(apmixed, 0x408, MAINPLL_CON1),
+ REGNAME(apmixed, 0x40c, MAINPLL_CON2),
+ REGNAME(apmixed, 0x410, MAINPLL_CON3),
+ REGNAME(apmixed, 0x414, MAINPLL_CON4),
+ REGNAME(apmixed, 0x418, UNIVPLL_CON0),
+ REGNAME(apmixed, 0x41c, UNIVPLL_CON1),
+ REGNAME(apmixed, 0x420, UNIVPLL_CON2),
+ REGNAME(apmixed, 0x424, UNIVPLL_CON3),
+ REGNAME(apmixed, 0x428, UNIVPLL_CON4),
+ REGNAME(apmixed, 0x22c, MSDCPLL_CON0),
+ REGNAME(apmixed, 0x230, MSDCPLL_CON1),
+ REGNAME(apmixed, 0x234, MSDCPLL_CON2),
+ REGNAME(apmixed, 0x238, MSDCPLL_CON3),
+ REGNAME(apmixed, 0x23c, MSDCPLL_CON4),
+ REGNAME(apmixed, 0x42c, MMPLL_CON0),
+ REGNAME(apmixed, 0x430, MMPLL_CON1),
+ REGNAME(apmixed, 0x434, MMPLL_CON2),
+ REGNAME(apmixed, 0x438, MMPLL_CON3),
+ REGNAME(apmixed, 0x43c, MMPLL_CON4),
+ REGNAME(apmixed, 0x618, MFGPLL_CON0),
+ REGNAME(apmixed, 0x61c, MFGPLL_CON1),
+ REGNAME(apmixed, 0x620, MFGPLL_CON2),
+ REGNAME(apmixed, 0x624, MFGPLL_CON3),
+ REGNAME(apmixed, 0x628, MFGPLL_CON4),
+ REGNAME(apmixed, 0x454, APLL1_CON0),
+ REGNAME(apmixed, 0x458, APLL1_CON1),
+ REGNAME(apmixed, 0x45c, APLL1_CON2),
+ REGNAME(apmixed, 0x460, APLL1_CON3),
+ REGNAME(apmixed, 0x464, APLL1_CON4),
+ REGNAME(apmixed, 0x468, APLL1_CON5),
+ REGNAME(apmixed, 0x46c, APLL2_CON0),
+ REGNAME(apmixed, 0x470, APLL2_CON1),
+ REGNAME(apmixed, 0x474, APLL2_CON2),
+ REGNAME(apmixed, 0x478, APLL2_CON3),
+ REGNAME(apmixed, 0x47c, APLL2_CON4),
+ REGNAME(apmixed, 0x480, APLL2_CON5),
+ REGNAME(apmixed, 0x804, NET1PLL_CON0),
+ REGNAME(apmixed, 0x808, NET1PLL_CON1),
+ REGNAME(apmixed, 0x80c, NET1PLL_CON2),
+ REGNAME(apmixed, 0x810, NET1PLL_CON3),
+ REGNAME(apmixed, 0x814, NET1PLL_CON4),
+ REGNAME(apmixed, 0x818, NET2PLL_CON0),
+ REGNAME(apmixed, 0x81c, NET2PLL_CON1),
+ REGNAME(apmixed, 0x820, NET2PLL_CON2),
+ REGNAME(apmixed, 0x824, NET2PLL_CON3),
+ REGNAME(apmixed, 0x828, NET2PLL_CON4),
+ REGNAME(apmixed, 0x82c, WEDMCUPLL_CON0),
+ REGNAME(apmixed, 0x830, WEDMCUPLL_CON1),
+ REGNAME(apmixed, 0x834, WEDMCUPLL_CON2),
+ REGNAME(apmixed, 0x838, WEDMCUPLL_CON3),
+ REGNAME(apmixed, 0x83c, WEDMCUPLL_CON4),
+ REGNAME(apmixed, 0x840, MEDMCUPLL_CON0),
+ REGNAME(apmixed, 0x844, MEDMCUPLL_CON1),
+ REGNAME(apmixed, 0x848, MEDMCUPLL_CON2),
+ REGNAME(apmixed, 0x84c, MEDMCUPLL_CON3),
+ REGNAME(apmixed, 0x850, MEDMCUPLL_CON4),
+ REGNAME(apmixed, 0x240, SGMIIPLL_CON0),
+ REGNAME(apmixed, 0x244, SGMIIPLL_CON1),
+ REGNAME(apmixed, 0x248, SGMIIPLL_CON2),
+ REGNAME(apmixed, 0x24c, SGMIIPLL_CON3),
+ REGNAME(apmixed, 0x250, SGMIIPLL_CON4),
+ /* GCE register */
+ REGNAME(gce, 0xf0, GCE_CTL_INT0),
+ /* AUDIO register */
+ REGNAME(audsys, 0x0, AUDIO_TOP_0),
+ REGNAME(audsys, 0x4, AUDIO_TOP_1),
+ REGNAME(audsys, 0x8, AUDIO_TOP_2),
+ /* IMP_IIC_WRAP_E register */
+ REGNAME(impe, 0xe00, AP_CLOCK_CG_RO_EST),
+ /* MFGCFG register */
+ REGNAME(mfgcfg, 0x0, MFG_CG),
+ /* MMSYS CONFIG register */
+ REGNAME(mm, 0x100, MMSYS_CG_CON0),
+ REGNAME(mm, 0x110, MMSYS_CG_CON1),
+ REGNAME(mm, 0x120, MMSYS_CG_CON2),
+ {},
+};
+
+/*
+ * clkdbg vf table
+ */
+
+struct mtk_vf {
+ const char *name;
+ int freq_table[4];
+};
+
+#define MTK_VF_TABLE(_n, _freq0, _freq1, _freq2, _freq3) { \
+ .name = _n, \
+ .freq_table = {_freq0, _freq1, _freq2, _freq3}, \
+ }
+
+/*
+ * Opp0 : 0p75v
+ * Opp1 : 0p65v
+ * Opp2 : 0p60v
+ * Opp3 : 0p55v
+ *//*
+static struct mtk_vf vf_table[] = {
+ // Opp0, Opp1, Opp2, Opp3
+ MTK_VF_TABLE("axi_sel", 156000, 156000, 156000, 136500),
+ MTK_VF_TABLE("spm_sel", 78000, 78000, 78000, 78000),
+ MTK_VF_TABLE("bus_aximem_sel", 218400, 156000,156000, 156000),
+ MTK_VF_TABLE("mm_sel", 208000, 178285, 178285, 178285),
+ MTK_VF_TABLE("mfg_ref_sel", 416000, 416000, 218400, 218400),
+ MTK_VF_TABLE("uart_sel", 52000, 52000, 52000, 52000),
+ MTK_VF_TABLE("msdc50_0_hclk_sel", 273000, 273000, 273000, 273000),
+ MTK_VF_TABLE("msdc50_0_sel", 416000, 416000, 416000, 416000),
+ MTK_VF_TABLE("msdc30_1_sel", 208000, 208000, 208000, 208000),
+ MTK_VF_TABLE("audio_sel", 54600, 54600, 54600, 54600),
+ MTK_VF_TABLE("aud_intbus_sel", 136500, 136500, 136500, 136500),
+ MTK_VF_TABLE("aud_engen1_sel", 22579, 22579, 22579, 22579),
+ MTK_VF_TABLE("aud_engen2_sel", 24576, 24576,24576, 24576),
+ MTK_VF_TABLE("aud_1_sel", 180633, 180633, 180633, 180633),
+ MTK_VF_TABLE("aud_2_sel", 196608, 196608, 196608, 196608),
+ MTK_VF_TABLE("pwrap_ulposc_sel", 65000, 65000, 65000, 65000),
+ MTK_VF_TABLE("atb_sel", 273000, 273000, 273000, 273000),
+ MTK_VF_TABLE("pwrmcu_sel", 364000, 312000, 312000, 273000),
+ MTK_VF_TABLE("dbi_sel", 124800, 124800, 124800, 124800),
+ MTK_VF_TABLE("disp_pwm_sel", 130000, 130000, 130000, 130000),
+ MTK_VF_TABLE("usb_top_sel", 124800, 124800, 124800, 124800),
+ MTK_VF_TABLE("ssusb_xhci_sel", 124800, 124800, 124800, 124800),
+ MTK_VF_TABLE("i2c_sel", 124800, 124800, 124800, 124800),
+ MTK_VF_TABLE("tl_sel", 136500, 136500, 136500, 136500),
+ MTK_VF_TABLE("dpmaif_main_sel", 364000, 364000, 364000, 273000),
+ MTK_VF_TABLE("pwm_sel", 78000, 78000, 78000, 78000),
+ MTK_VF_TABLE("spmi_m_mst_sel", 32500, 32500, 32500, 32500),
+ MTK_VF_TABLE("spmi_p_mst_sel", 32500, 32500, 32500, 32500),
+ MTK_VF_TABLE("dvfsrc_sel", 26000, 26000, 26000, 26000),
+ MTK_VF_TABLE("mcupm_sel", 182000, 182000, 182000, 182000),
+ MTK_VF_TABLE("sflash_sel", 62400, 62400, 62400, 62400),
+ MTK_VF_TABLE("gcpu_sel", 416000, 364000, 364000, 273000),
+ MTK_VF_TABLE("spi_sel", 208000, 208000, 208000, 178285),
+ MTK_VF_TABLE("spis_sel", 416000, 416000, 312000, 104000),
+ MTK_VF_TABLE("ecc_sel", 312000, 242666, 242666, 136500),
+ MTK_VF_TABLE("nfi1x_sel", 182000, 182000, 182000, 182000),
+ MTK_VF_TABLE("spinfi_bclk_sel", 124800, 124800, 124800, 124800),
+ MTK_VF_TABLE("netsys_sel", 78000, 356571, 242666, 156000),
+ MTK_VF_TABLE("medsys_sel", 78000, 356571, 242666, 156000),
+ MTK_VF_TABLE("hsm_crypto_sel", 312000, 312000, 26000, 26000),
+ MTK_VF_TABLE("hsm_arc_sel", 26000, 26000, 182000, 182000),
+ MTK_VF_TABLE("eip97_sel", 800000, 546000, 364000, 218400),
+ MTK_VF_TABLE("snps_eth_312p5m_sel", 312500, 312500, 312500, 312500),
+ MTK_VF_TABLE("snps_eth_250m_sel", 250000, 250000, 250000, 250000),
+ MTK_VF_TABLE("snps_eth_62p4m_ptp_sel", 62400, 62400, 62400, 62400),
+ MTK_VF_TABLE("snps_eth_50m_rmii_sel", 50000, 50000, 50000, 50000),
+ MTK_VF_TABLE("netsys_500m_sel", 500000, 500000, 500000, 500000),
+ MTK_VF_TABLE("netsys_med_mcu_sel", 580000, 356571, 273000, 104000),
+ MTK_VF_TABLE("netsys_wed_mcu_sel", 760000, 436800, 364000, 182000),
+ MTK_VF_TABLE("netsys_2x_sel", 800000, 546000, 273000, 124800),
+ MTK_VF_TABLE("sgmii_sel", 325000, 325000, 325000, 325000),
+ MTK_VF_TABLE("sgmii_sbus_sel", 78000, 78000,78000, 78000),
+};*/
+
+/*
+ * clkdbg fmeter
+ */
+
+#define clk_readl(addr) readl(addr)
+#define clk_writel(addr, val) \
+ do { writel(val, addr); wmb(); } while (0) /* sync write */
+
+#define FMCLK2(_t, _i, _n, _o, _p) { .type = _t, \
+ .id = _i, .name = _n, .ofs = _o, .pdn = _p}
+#define FMCLK(_t, _i, _n) { .type = _t, .id = _i, .name = _n }
+
+static const struct fmeter_clk fclks[] = {
+ /* CKGEN Part */
+ FMCLK2(CKGEN, FM_AXI_CK, "fm_axi_ck", 0x0010, 7),
+ FMCLK2(CKGEN, FM_SPM_CK, "fm_spm_ck", 0x0010, 15),
+ FMCLK2(CKGEN, FM_BUS_CK, "fm_bus_ck", 0x0010, 23),
+ FMCLK2(CKGEN, FM_MM_CK, "fm_mm_ck", 0x0010, 31),
+ FMCLK2(CKGEN, FM_MFG_REF_CK, "fm_mfg_ref_ck", 0x0020, 7),
+ FMCLK2(CKGEN, FM_FUART_CK, "fm_fuart_ck", 0x0020, 15),
+ FMCLK2(CKGEN, FM_MSDC50_0_H_CK, "fm_msdc50_0_h_ck", 0x0020, 23),
+ FMCLK2(CKGEN, FM_MSDC50_0_CK, "fm_msdc50_0_ck", 0x0020, 31),
+ FMCLK2(CKGEN, FM_MSDC30_1_CK, "fm_msdc30_1_ck", 0x0030, 7),
+ FMCLK2(CKGEN, FM_AUDIO_CK, "fm_audio_ck", 0x0030, 15),
+ FMCLK2(CKGEN, FM_AUD_INTBUS_CK, "fm_aud_intbus_ck", 0x0030, 23),
+ FMCLK2(CKGEN, FM_AUD_ENGEN1_CK, "fm_aud_engen1_ck", 0x0030, 31),
+ FMCLK2(CKGEN, FM_AUD_ENGEN2_CK, "fm_aud_engen2_ck", 0x0040, 7),
+ FMCLK2(CKGEN, FM_AUD1_CK, "fm_aud1_ck", 0x0040, 15),
+ FMCLK2(CKGEN, FM_AUD2_CK, "fm_aud2_ck", 0x0040, 23),
+ FMCLK2(CKGEN, FM_FPWRAP_ULPOSC_CK, "fm_fpwrap_ulposc_ck", 0x0040, 31),
+ FMCLK2(CKGEN, FM_ATB_CK, "fm_atb_ck", 0x0050, 7),
+ FMCLK2(CKGEN, FM_PWRMCU_CK, "fm_pwrmcu_ck", 0x0050, 15),
+ FMCLK2(CKGEN, FM_DBI_CK, "fm_dbi_ck", 0x0050, 23),
+ FMCLK2(CKGEN, FM_FDISP_PWM_CK, "fm_fdisp_pwm_ck", 0x0050, 31),
+ FMCLK2(CKGEN, FM_FUSB_CK, "fm_fusb_ck", 0x0060, 7),
+ FMCLK2(CKGEN, FM_FSSUSB_XHCI_CK, "fm_fssusb_xhci_ck", 0x0060, 15),
+ FMCLK2(CKGEN, FM_I2C_CK, "fm_i2c_ck", 0x0060, 23),
+ FMCLK2(CKGEN, FM_TL_CK, "fm_tl_ck", 0x0060, 31),
+ FMCLK2(CKGEN, FM_DPMAIF_MAIN_CK, "fm_dpmaif_main_ck", 0x0070, 7),
+ FMCLK2(CKGEN, FM_PWM_CK, "fm_pwm_ck", 0x0070, 15),
+ FMCLK2(CKGEN, FM_SPMI_M_MST_CK, "fm_spmi_m_mst_ck", 0x0070, 23),
+ FMCLK2(CKGEN, FM_SPMI_P_MST_CK, "fm_spmi_p_mst_ck", 0x0070, 31),
+ FMCLK2(CKGEN, FM_DVFSRC_CK, "fm_dvfsrc_ck", 0x0080, 7),
+ FMCLK2(CKGEN, FM_MCUPM_CK, "fm_mcupm_ck", 0x0080, 15),
+ FMCLK2(CKGEN, FM_SFLASH_CK, "fm_sflash_ck", 0x0080, 23),
+ FMCLK2(CKGEN, FM_GCPU_CK, "fm_gcpu_ck", 0x0080, 31),
+ FMCLK2(CKGEN, FM_SPI_CK, "fm_spi_ck", 0x0090, 7),
+ FMCLK2(CKGEN, FM_SPIS_CK, "fm_spis_ck", 0x0090, 15),
+ FMCLK2(CKGEN, FM_ECC_CK, "fm_ecc_ck", 0x0090, 23),
+ FMCLK2(CKGEN, FM_NFI1X_CK, "fm_nfi1x_ck", 0x0090, 31),
+ FMCLK2(CKGEN, FM_SPINFI_BCLK_CK, "fm_spinfi_bclk_ck", 0x00A0, 7),
+ FMCLK2(CKGEN, FM_NETSYS_CK, "fm_netsys_ck", 0x00A0, 15),
+ FMCLK2(CKGEN, FM_MEDSYS_CK, "fm_medsys_ck", 0x00A0, 23),
+ FMCLK2(CKGEN, FM_HSM_CRYPTO_CK, "fm_hsm_crypto_ck", 0x00A0, 31),
+ FMCLK2(CKGEN, FM_HSM_ARC_CK, "fm_hsm_arc_ck", 0x00B0, 7),
+ FMCLK2(CKGEN, FM_EIP97_CK, "fm_eip97_ck", 0x00B0, 15),
+ FMCLK2(CKGEN, FM_SNPS_ETH_312P5M_CK, "fm_snps_eth_312p5m_ck", 0x00B0, 23),
+ FMCLK2(CKGEN, FM_SNPS_ETH_250M_CK, "fm_snps_eth_250m_ck", 0x00B0, 31),
+ FMCLK2(CKGEN, FM_SNPS_PTP_CK, "fm_snps_ptp_ck", 0x00C0, 7),
+ FMCLK2(CKGEN, FM_SNPS_ETH_50M_RMII_CK, "fm_snps_eth_50m_rmii_ck", 0x00C0, 15),
+ FMCLK2(CKGEN, FM_NETSYS_500M_CK, "fm_netsys_500m_ck", 0x00C0, 23),
+ FMCLK2(CKGEN, FM_NETSYS_MED_MCU_CK, "fm_netsys_med_mcu_ck", 0x00C0, 31),
+ FMCLK2(CKGEN, FM_NETSYS_WED_MCU_CK, "fm_netsys_wed_mcu_ck", 0x00D0, 7),
+ FMCLK2(CKGEN, FM_NETSYS_2X_CK, "fm_netsys_2x_ck", 0x00D0, 15),
+ FMCLK2(CKGEN, FM_SGMII_CK, "fm_sgmii_ck", 0x00D0, 23),
+ FMCLK2(CKGEN, FM_SGMII_SBUS_CK, "fm_sgmii_sbus_ck", 0x00D0, 31),
+ /* ABIST Part */
+ FMCLK(ABIST, FM_APLL1_CK, "fm_apll1_ck"),
+ FMCLK(ABIST, FM_APLL2_CK, "fm_apll2_ck"),
+ FMCLK(ABIST, FM_APPLLGP_MON_FM_CK, "fm_appllgp_mon_fm_ck"),
+ FMCLK(ABIST, FM_ARMPLL_LL_CK, "fm_armpll_ll_ck"),
+ FMCLK(ABIST, FM_CCIPLL_CK, "fm_ccipll_ck"),
+ FMCLK(ABIST, FM_NET1PLL_CK, "fm_net1pll_ck"),
+ FMCLK(ABIST, FM_NET2PLL_CK, "fm_net2pll_ck"),
+ FMCLK(ABIST, FM_WEDMCUPLL_CK, "fm_wedmcupll_ck"),
+ FMCLK(ABIST, FM_MEDMCUPLL_CK, "fm_medmcupll_ck"),
+ FMCLK(ABIST, FM_SGMIIPLL_CK, "fm_sgmiipll_ck"),
+ FMCLK(ABIST, FM_SNPSETHPLL_CK, "fm_snpsethpll_ck"),
+ FMCLK(ABIST, FM_DSI0_LNTC_DSICLK, "fm_dsi0_lntc_dsiclk"),
+ FMCLK(ABIST, FM_DSI0_MPPLL_TST_CK, "fm_dsi0_mppll_tst_ck"),
+ FMCLK(ABIST, FM_MDPLL1_FS26M_DRF_GUIDE, "fm_mdpll1_fs26m_drf_guide"),
+ FMCLK(ABIST, FM_MFG_CK, "fm_mfg_ck"),
+ FMCLK(ABIST, FM_MAINPLL_CK, "fm_mainpll_ck"),
+ FMCLK(ABIST, FM_MDPLL1_FS26M_GUIDE, "fm_mdpll1_fs26m_guide"),
+ FMCLK(ABIST, FM_MFGPLL_CK, "fm_mfgpll_ck"),
+ FMCLK(ABIST, FM_MMPLL_CK, "fm_mmpll_ck"),
+ FMCLK(ABIST, FM_MMPLL_D3_CK, "fm_mmpll_d3_ck"),
+ FMCLK(ABIST, FM_MPLL_CK, "fm_mpll_ck"),
+ FMCLK(ABIST, FM_MSDCPLL_CK, "fm_msdcpll_ck"),
+ FMCLK(ABIST, FM_RCLRPLL_DIV4_CK, "fm_rclrpll_div4_ck"),
+ FMCLK(ABIST, FM_RPHYPLL_DIV4_CK, "fm_rphypll_div4_ck"),
+ FMCLK(ABIST, FM_ULPOSC_CK, "fm_ulposc_ck"),
+ FMCLK(ABIST, FM_UNIVPLL_CK, "fm_univpll_ck"),
+ FMCLK(ABIST, FMEM_AFT_CH0, "fmem_aft_ch0"),
+ FMCLK(ABIST, FMEM_AFT_CH1, "fmem_aft_ch1"),
+ FMCLK(ABIST, FM_TRNG_FREQ_DEBUG_OUT0, "fm_trng_freq_debug_out0"),
+ FMCLK(ABIST, FM_TRNG_FREQ_DEBUG_OUT1, "fm_trng_freq_debug_out1"),
+ FMCLK(ABIST, FMEM_BFE_CH0, "fmem_bfe_ch0"),
+ FMCLK(ABIST, FMEM_BFE_CH1, "fmem_bfe_ch1"),
+ FMCLK(ABIST, FM_466M_FMEM_INFRASYS, "fm_466m_fmem_infrasys"),
+ FMCLK(ABIST, FM_MCUSYS_ARM_OUT_ALL, "fm_mcusys_arm_out_all"),
+ FMCLK(ABIST, FM_RTC32K_I_VAO, "fm_rtc32k_i_vao"),
+ /* ABIST_2 Part */
+ FMCLK(ABIST_2, FM_MCUPM_CK, "fm_mcupm_ck"),
+ FMCLK(ABIST_2, FM_SFLASH_CK, "fm_sflash_ck"),
+ FMCLK(ABIST_2, FM_UNIPLL_SES_CK, "fm_unipll_ses_ck"),
+ FMCLK(ABIST_2, FM_ULPOSC_CK, "fm_ulposc_ck"),
+ FMCLK(ABIST_2, FM_ULPOSC_CORE_CK, "fm_ulposc_core_ck"),
+ FMCLK(ABIST_2, FM_SRCK_CK, "fm_srck_ck"),
+ FMCLK(ABIST_2, FM_MAINPLL_H728M_CK, "fm_mainpll_h728m_ck"),
+ FMCLK(ABIST_2, FM_MAINPLL_H546M_CK, "fm_mainpll_h546m_ck"),
+ FMCLK(ABIST_2, FM_MAINPLL_H436P8M_CK, "fm_mainpll_h436p8m_ck"),
+ FMCLK(ABIST_2, FM_MAINPLL_H364M_CK, "fm_mainpll_h364m_ck"),
+ FMCLK(ABIST_2, FM_MAINPLL_H312M_CK, "fm_mainpll_h312m_ck"),
+ FMCLK(ABIST_2, FM_UNIVPLL_1248M_CK, "fm_univpll_1248m_ck"),
+ FMCLK(ABIST_2, FM_UNIVPLL_832M_CK, "fm_univpll_832m_ck"),
+ FMCLK(ABIST_2, FM_UNIVPLL_624M_CK, "fm_univpll_624m_ck"),
+ FMCLK(ABIST_2, FM_UNIVPLL_499M_CK, "fm_univpll_499m_ck"),
+ FMCLK(ABIST_2, FM_UNIVPLL_416M_CK, "fm_univpll_416m_ck"),
+ FMCLK(ABIST_2, FM_UNIVPLL_356P6M_CK, "fm_univpll_356p6m_ck"),
+ FMCLK(ABIST_2, FM_MMPLL_D3_CK, "fm_mmpll_d3_ck"),
+ FMCLK(ABIST_2, FM_MMPLL_D4_CK, "fm_mmpll_d4_ck"),
+ FMCLK(ABIST_2, FM_MMPLL_D5_CK, "fm_mmpll_d5_ck"),
+ FMCLK(ABIST_2, FM_MMPLL_D6_CK, "fm_mmpll_d6_ck"),
+ FMCLK(ABIST_2, FM_MMPLL_D7_CK, "fm_mmpll_d7_ck"),
+ FMCLK(ABIST_2, FM_MMPLL_D9_CK, "fm_mmpll_d9_ck"),
+ FMCLK(ABIST_2, FM_NET1PLL_CK, "fm_net1pll_ck"),
+ FMCLK(ABIST_2, FM_NET2PLL_CK, "fm_net2pll_ck"),
+ FMCLK(ABIST_2, FM_WEDMCUPLL_CK, "fm_wedmcupll_ck"),
+ FMCLK(ABIST_2, FM_MEDMCUPLL_CK, "fm_medmcupll_ck"),
+ FMCLK(ABIST_2, FM_SGMIIPLL_CK, "fm_sgmiipll_ck"),
+ {},
+};
+
+#define _CKGEN(x) (rb[top].virt + (x))
+#define CLK_CFG_0 _CKGEN(0x10)
+#define CLK_CFG_1 _CKGEN(0x20)
+#define CLK_CFG_2 _CKGEN(0x30)
+#define CLK_CFG_3 _CKGEN(0x40)
+#define CLK_CFG_4 _CKGEN(0x50)
+#define CLK_CFG_5 _CKGEN(0x60)
+#define CLK_CFG_6 _CKGEN(0x70)
+#define CLK_CFG_7 _CKGEN(0x80)
+#define CLK_CFG_8 _CKGEN(0x90)
+#define CLK_CFG_9 _CKGEN(0xA0)
+#define CLK_CFG_10 _CKGEN(0xB0)
+#define CLK_CFG_11 _CKGEN(0xC0)
+#define CLK_CFG_12 _CKGEN(0xD0)
+//#define CLK_CFG_13 _CKGEN(0xE0)
+#define CLK_MISC_CFG_0 _CKGEN(0x140)
+#define CLK_DBG_CFG _CKGEN(0x17C)
+#define CLK26CALI_0 _CKGEN(0x220)
+#define CLK26CALI_1 _CKGEN(0x224)
+
+/*
+ * clkdbg dump_clks
+ */
+
+ static const char * const *get_pwr_names(void)
+{
+ static const char * const pwr_names[] = {
+ [0] = "md1",
+ [1] = "conn",
+ [2] = "mfg0",
+ [3] = "pextp_d_2lx1_phy",
+ [4] = "pextp_r_2lx1_phy",
+ [5] = "pextp_r_1lx2_0p_phy",
+ [6] = "pextp_r_1lx2_1p_phy",
+ [7] = "ssusb_phy",
+ [8] = "sgmii_0_phy",
+ [9] = "infra",
+ [10] = "sgmii_1_phy",
+ [11] = "dpy",
+ [12] = "pextp_d_2lx1",
+ [13] = "pextp_r_2lx1",
+ [14] = "pextp_r_1lx2",
+ [15] = "eth",
+ [16] = "ssusb",
+ [17] = "sgmii_0_top",
+ [18] = "sgmii_1_top",
+ [19] = "netsys",
+ [20] = "dis",
+ [21] = "audio",
+ [22] = "eip97",
+ [23] = "hsmtop",
+ [24] = "dramc_md32",
+ [25] = "(Reserved)",
+ [26] = "(Reserved)",
+ [27] = "(Reserved)",
+ [28] = "dpy2",
+ [29] = "mcupm",
+ [30] = "msdc",
+ [31] = "peri",
+ };
+ return pwr_names;
+}
+
+ static const char * const *get_all_clk_names(void)
+{
+ return get_mt6890_all_clk_names();
+}
+
+ static const struct regname *get_all_regnames(void)
+{
+ return rn;
+}
+
+static void __init init_regbase(void)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(rb); i++) {
+ if (!rb[i].phys)
+ continue;
+ rb[i].virt = ioremap_nocache(rb[i].phys, 0x1000);
+ }
+}
+
+unsigned int mt_get_abist_freq(unsigned int ID)
+{
+ int output = 0, i = 0;
+ unsigned long flags;
+ unsigned int temp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1 = 0;
+ fmeter_lock(flags);
+ while (clk_readl(CLK26CALI_0) & 0x1000) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ ;
+ clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
+ clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFC0FFFC)|(ID << 16));
+ clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
+ clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (3 << 24));
+ clk26cali_1 = clk_readl(CLK26CALI_1);
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+ /* wait frequency meter finish */
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ /* illegal pass */
+ if (i == 0) {
+ clk_writel(CLK26CALI_0, 0x0000);
+ //re-trigger
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ }
+ temp = clk_readl(CLK26CALI_1) & 0xFFFF;
+ output = (temp * 26000) / 1024;
+ clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
+ clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
+ /*clk_writel(CLK26CALI_0, clk26cali_0);*/
+ /*clk_writel(CLK26CALI_1, clk26cali_1);*/
+ clk_writel(CLK26CALI_0, 0x0000);
+ fmeter_unlock(flags);
+ if (i > 30)
+ return 0;
+ else {
+ if ((output * 4) < 25000) {
+ pr_notice("%s: CLK_DBG_CFG = 0x%x, CLK_MISC_CFG_0 = 0x%x, CLK26CALI_0 = 0x%x, CLK26CALI_1 = 0x%x\n",
+ __func__,
+ clk_readl(CLK_DBG_CFG),
+ clk_readl(CLK_MISC_CFG_0),
+ clk_readl(CLK26CALI_0),
+ clk_readl(CLK26CALI_1));
+ }
+ return (output * 4);
+ }
+}
+
+static unsigned int mt_get_abist2_freq(unsigned int ID)
+{
+ int output = 0, i = 0;
+ unsigned long flags;
+ unsigned int temp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1 = 0;
+ fmeter_lock(flags);
+ while (clk_readl(CLK26CALI_0) & 0x1000) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ ;
+ clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
+ clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xC0FFFFFC)
+ | (ID << 24) | (0x2));
+ clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
+ clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (1 << 24));
+ clk26cali_1 = clk_readl(CLK26CALI_1);
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+ // wait frequency meter finish
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ // illegal pass
+ if (i == 0) {
+ clk_writel(CLK26CALI_0, 0x0000);
+ //re-trigger
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ }
+ temp = clk_readl(CLK26CALI_1) & 0xFFFF;
+ output = (temp * 26000) / 1024;
+ clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
+ clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
+ //clk_writel(CLK26CALI_0, clk26cali_0);
+ //clk_writel(CLK26CALI_1, clk26cali_1);
+ clk_writel(CLK26CALI_0, 0x0000);
+ //pr_debug("%s = %d Khz\n", abist_array[ID-1], output);
+ fmeter_unlock(flags);
+ if (i > 30)
+ return 0;
+ else
+ return (output * 2);
+}
+
+static unsigned int check_mux_pdn(unsigned int ID)
+{
+ int i;
+ if ((ID > 0) && (ID < 64)) {
+ for (i = 0; i < ARRAY_SIZE(fclks); i++)
+ if (fclks[i].id == ID)
+ break;
+ if (i >= ARRAY_SIZE(fclks))
+ return 1;
+ if ((clk_readl(rb[top].virt + fclks[i].ofs)
+ & BIT(fclks[i].pdn)))
+ return 1;
+ else
+ return 0;
+ } else
+ return 1;
+}
+
+unsigned int mt_get_ckgen_freq(unsigned int ID)
+{
+ int output = 0, i = 0;
+ unsigned int temp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1 = 0;
+ unsigned long flags;
+ if (check_mux_pdn(ID)) {
+ pr_notice("ID-%d: MUX PDN, return 0.\n", ID);
+ return 0;
+ }
+ fmeter_lock(flags);
+ while (clk_readl(CLK26CALI_0) & 0x1000) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
+ clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFFFC0FC)|(ID << 8)|(0x1));
+ clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
+ clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (3 << 24));
+ clk26cali_1 = clk_readl(CLK26CALI_1);
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+ /* wait frequency meter finish */
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ /* illegal pass */
+ if (i == 0) {
+ clk_writel(CLK26CALI_0, 0x0000);
+ //re-trigger
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ udelay(10);
+ i++;
+ if (i > 30)
+ break;
+ }
+ }
+ temp = clk_readl(CLK26CALI_1) & 0xFFFF;
+ output = (temp * 26000) / 1024;
+ clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
+ clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
+ /*clk_writel(CLK26CALI_0, clk26cali_0);*/
+ /*clk_writel(CLK26CALI_1, clk26cali_1);*/
+ clk_writel(CLK26CALI_0, 0x0000);
+ fmeter_unlock(flags);
+ /*print("ckgen meter[%d] = %d Khz\n", ID, output);*/
+ if (i > 30)
+ return 0;
+ else {
+ if ((output * 4) < 25000) {
+ pr_notice("%s: CLK_DBG_CFG = 0x%x, CLK_MISC_CFG_0 = 0x%x, CLK26CALI_0 = 0x%x, CLK26CALI_1 = 0x%x\n",
+ __func__,
+ clk_readl(CLK_DBG_CFG),
+ clk_readl(CLK_MISC_CFG_0),
+ clk_readl(CLK26CALI_0),
+ clk_readl(CLK26CALI_1));
+ }
+ return (output * 4);
+ }
+}
+
+ static u32 fmeter_freq_op(const struct fmeter_clk *fclk)
+{
+ if (fclk->type == ABIST)
+ return mt_get_abist_freq(fclk->id);
+ else if (fclk->type == ABIST_2)
+ return mt_get_abist2_freq(fclk->id);
+ else if (fclk->type == CKGEN)
+ return mt_get_ckgen_freq(fclk->id);
+ return 0;
+}
+
+static const struct fmeter_clk *get_all_fmeter_clks(void)
+{
+ return fclks;
+}
+
+void setup_provider_clk(struct provider_clk *pvdck)
+{
+ static const struct {
+ const char *pvdname;
+ u32 pwr_mask;
+ } pvd_pwr_mask[] = {
+ };
+
+ int i;
+ const char *pvdname = pvdck->provider_name;
+
+ if (!pvdname)
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(pvd_pwr_mask); i++) {
+ if (strcmp(pvdname, pvd_pwr_mask[i].pvdname) == 0) {
+ pvdck->pwr_mask = pvd_pwr_mask[i].pwr_mask;
+ return;
+ }
+ }
+}
+
+/*
+ * chip_ver functions
+ */
+/*
+static int clkdbg_chip_ver(struct seq_file *s, void *v)
+{
+ static const char * const sw_ver_name[] = {
+ "CHIP_SW_VER_01",
+ "CHIP_SW_VER_02",
+ "CHIP_SW_VER_03",
+ "CHIP_SW_VER_04",
+ };
+
+ seq_printf(s, "mt_get_chip_sw_ver(): %d (%s)\n", 0, sw_ver_name[0]);
+
+ return 0;
+}*/
+
+/*
+ * init functions
+ */
+
+static struct clkdbg_ops clkdbg_mt6890_ops = {
+ .get_all_fmeter_clks = get_all_fmeter_clks,
+ .prepare_fmeter = NULL,
+ .unprepare_fmeter = NULL,
+ .fmeter_freq = fmeter_freq_op,
+ .get_all_regnames = get_all_regnames,
+ .get_all_clk_names = get_all_clk_names,
+ .get_pwr_names = get_pwr_names,
+ .setup_provider_clk = setup_provider_clk,
+};
+
+static void __init init_custom_cmds(void)
+{
+ /*static const struct cmd_fn cmds[] = {
+ CMDFN("chip_ver", clkdbg_chip_ver),
+ {}
+ };
+
+ set_custom_cmds(cmds);*/
+}
+
+static int __init clkdbg_mt6890_init(void)
+{
+/* if (!of_machine_is_compatible("mediatek,MT6890"))
+ return -ENODEV;
+*/
+ init_regbase();
+
+ init_custom_cmds();
+ set_clkdbg_ops(&clkdbg_mt6890_ops);
+
+#ifdef CONFIG_MTK_DEVAPC
+// register_devapc_vio_callback(&devapc_vio_handle);
+#endif
+
+#if DUMP_INIT_STATE
+ print_regs();
+ print_fmeter_all();
+#endif /* DUMP_INIT_STATE */
+
+ return 0;
+}
+subsys_initcall(clkdbg_mt6890_init);
+
+/*
+ * MT6890: for mtcmos debug
+ */
+static bool is_valid_reg(void __iomem *addr)
+{
+#ifdef CONFIG_64BIT
+ return ((u64)addr & 0xf0000000) != 0UL ||
+ (((u64)addr >> 32U) & 0xf0000000) != 0UL;
+#else
+ return ((u32)addr & 0xf0000000) != 0U;
+#endif
+}
+
+void print_subsys_reg(enum dbg_sys_id id)
+{
+ struct regbase *rb_dump;
+ const struct regname *rns = &rn[0];
+ int i;
+ /*if (rns == NULL)
+ return;*/
+ if (id >= dbg_sys_num || id < 0) {
+ pr_info("wrong id:%d\n", id);
+ return;
+ }
+ rb_dump = &rb[id];
+ for (i = 0; i < ARRAY_SIZE(rn) - 1; i++, rns++) {
+ if (!is_valid_reg(ADDR(rns)))
+ return;
+ /* filter out the subsys that we don't want */
+ if (rns->base != rb_dump)
+ continue;
+ pr_info("%-18s: [0x%08x] = 0x%08x\n",
+ rns->name, PHYSADDR(rns), clk_readl(ADDR(rns)));
+ }
+}
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt6890.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt6890.h
new file mode 100755
index 0000000..fd40563
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt6890.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+
+#ifndef __DRV_CLKDBG_MT6890_H
+#define __DRV_CLKDBG_MT6890_H
+
+enum dbg_sys_id {
+ top,
+ dbgsys_dem,
+ ifrao,
+ infracfg_ao_bus,
+ peri,
+ spm,
+ apmixed,
+ gce,
+ audsys,
+ impe,
+ mfgcfg,
+ mm,
+ dbg_sys_num,
+};
+
+extern void subsys_if_on(void);
+
+extern unsigned int mt_get_ckgen_freq(unsigned int ID);
+
+/*ram console api*/
+#ifdef CONFIG_MTK_RAM_CONSOLE
+extern void aee_rr_rec_clk(int id, u32 val);
+#endif
+
+extern const char * const *get_mt6890_all_clk_names(void);
+extern void print_enabled_clks_once(void);
+extern void print_subsys_reg(enum dbg_sys_id id);
+
+#endif /* __DRV_CLKDBG_MT6758_H */
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt8168.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt8168.c
new file mode 100644
index 0000000..2d142a7
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg-mt8168.c
@@ -0,0 +1,772 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+
+#include "clkdbg.h"
+
+#define DUMP_INIT_STATE 0
+#define DEFAULT_CYCLE_COUNT 0x1FF
+/*
+ * clkdbg dump_regs
+ */
+
+enum {
+ topckgen,
+ infracfg,
+ scpsys,
+ apmixedsys,
+ audiosys,
+ mfgsys,
+ mmsys,
+ camsys,
+ vdecsys,
+ vencsys,
+};
+
+#define REGBASE_V(_phys, _id_name) { .phys = _phys, .name = #_id_name }
+
+/*
+ * checkpatch.pl ERROR:COMPLEX_MACRO
+ *
+ * #define REGBASE(_phys, _id_name) [_id_name] = REGBASE_V(_phys, _id_name)
+ */
+
+static struct regbase rb[] = {
+ [topckgen] = REGBASE_V(0x10000000, topckgen),
+ [infracfg] = REGBASE_V(0x10001000, infracfg),
+ [scpsys] = REGBASE_V(0x10006000, scpsys),
+ [apmixedsys] = REGBASE_V(0x1000c000, apmixedsys),
+ [audiosys] = REGBASE_V(0x11220000, audiosys),
+ [mfgsys] = REGBASE_V(0x13000000, mfgsys),
+ [mmsys] = REGBASE_V(0x14000000, mmsys),
+ [camsys] = REGBASE_V(0x15000000, camsys),
+ [vdecsys] = REGBASE_V(0x16000000, vdecsys),
+ [vencsys] = REGBASE_V(0x17000000, vencsys),
+};
+
+#define REGNAME(_base, _ofs, _name) \
+ { .base = &rb[_base], .ofs = _ofs, .name = #_name }
+
+static struct regname rn[] = {
+ REGNAME(topckgen, 0x040, CLK_CFG_0),
+ REGNAME(topckgen, 0x050, CLK_CFG_1),
+ REGNAME(topckgen, 0x060, CLK_CFG_2),
+ REGNAME(topckgen, 0x070, CLK_CFG_3),
+ REGNAME(topckgen, 0x080, CLK_CFG_4),
+ REGNAME(topckgen, 0x090, CLK_CFG_5),
+ REGNAME(topckgen, 0x0a0, CLK_CFG_6),
+ REGNAME(topckgen, 0x0b0, CLK_CFG_7),
+ REGNAME(topckgen, 0x0c0, CLK_CFG_8),
+ REGNAME(topckgen, 0x0d0, CLK_CFG_9),
+ REGNAME(topckgen, 0x0e0, CLK_CFG_10),
+ REGNAME(topckgen, 0x0ec, CLK_CFG_11),
+ REGNAME(audiosys, 0x000, AUDIO_TOP_CON0),
+ REGNAME(audiosys, 0x004, AUDIO_TOP_CON1),
+ REGNAME(camsys, 0x000, CAMSYS_CG),
+ REGNAME(infracfg, 0x090, MODULE_SW_CG_0),
+ REGNAME(infracfg, 0x094, MODULE_SW_CG_1),
+ REGNAME(infracfg, 0x0ac, MODULE_SW_CG_2),
+ REGNAME(infracfg, 0x0c8, MODULE_SW_CG_3),
+ REGNAME(infracfg, 0x0d8, MODULE_SW_CG_4),
+ REGNAME(mfgsys, 0x000, MFG_CG),
+ REGNAME(mmsys, 0x100, MMSYS_CG_CON0),
+ REGNAME(mmsys, 0x110, MMSYS_CG_CON1),
+ REGNAME(vencsys, 0x004, VENCSYS_CG),
+ REGNAME(vdecsys, 0x000, VDEC_CKEN),
+ REGNAME(vdecsys, 0x008, VDEC_LARB3_CKEN),
+ REGNAME(apmixedsys, 0x30C, ARMPLL_CON0),
+ REGNAME(apmixedsys, 0x310, ARMPLL_CON1),
+ REGNAME(apmixedsys, 0x318, ARMPLL_PWR_CON0),
+ REGNAME(apmixedsys, 0x228, MAINPLL_CON0),
+ REGNAME(apmixedsys, 0x22C, MAINPLL_CON1),
+ REGNAME(apmixedsys, 0x234, MAINPLL_PWR_CON0),
+ REGNAME(apmixedsys, 0x208, UNIVPLL_CON0),
+ REGNAME(apmixedsys, 0x20C, UNIVPLL_CON1),
+ REGNAME(apmixedsys, 0x214, UNIVPLL_PWR_CON0),
+ REGNAME(apmixedsys, 0x218, MFGPLL_CON0),
+ REGNAME(apmixedsys, 0x21C, MFGPLL_CON1),
+ REGNAME(apmixedsys, 0x224, MFGPLL_PWR_CON0),
+ REGNAME(apmixedsys, 0x350, MSDCPLL_CON0),
+ REGNAME(apmixedsys, 0x354, MSDCPLL_CON1),
+ REGNAME(apmixedsys, 0x35C, MSDCPLL_PWR_CON0),
+ REGNAME(apmixedsys, 0x330, MMPLL_CON0),
+ REGNAME(apmixedsys, 0x334, MMPLL_CON1),
+ REGNAME(apmixedsys, 0x33C, MMPLL_PWR_CON0),
+ REGNAME(apmixedsys, 0x31C, APLL1_CON0),
+ REGNAME(apmixedsys, 0x320, APLL1_CON1),
+ REGNAME(apmixedsys, 0x32C, APLL1_PWR_CON0),
+ REGNAME(apmixedsys, 0x360, APLL2_CON0),
+ REGNAME(apmixedsys, 0x364, APLL2_CON1),
+ REGNAME(apmixedsys, 0x370, APLL2_PWR_CON0),
+ REGNAME(apmixedsys, 0x340, MPLL_CON0),
+ REGNAME(apmixedsys, 0x344, MPLL_CON1),
+ REGNAME(apmixedsys, 0x34C, MPLL_PWR_CON0),
+ REGNAME(apmixedsys, 0x374, LVDSPLL_CON0),
+ REGNAME(apmixedsys, 0x378, LVDSPLL_CON1),
+ REGNAME(apmixedsys, 0x380, LVDSPLL_PWR_CON0),
+ REGNAME(apmixedsys, 0x390, DSPPLL_CON0),
+ REGNAME(apmixedsys, 0x394, DSPPLL_CON1),
+ REGNAME(apmixedsys, 0x39C, DSPPLL_PWR_CON0),
+ REGNAME(apmixedsys, 0x3A0, APUPLL_CON0),
+ REGNAME(apmixedsys, 0x3A4, APUPLL_CON1),
+ REGNAME(apmixedsys, 0x3AC, APUPLL_PWR_CON0),
+ REGNAME(scpsys, 0x0180, PWR_STATUS),
+ REGNAME(scpsys, 0x0184, PWR_STATUS_2ND),
+ REGNAME(scpsys, 0x0338, MFG_PWR_CON),
+ REGNAME(scpsys, 0x032C, CONN_PWR_CON),
+ REGNAME(scpsys, 0x0314, AUD_PWR_CON),
+ REGNAME(scpsys, 0x030C, DIS_PWR_CON),
+ REGNAME(scpsys, 0x0344, CAM_PWR_CON),
+ REGNAME(scpsys, 0x0300, VDEC_PWR_CON),
+ REGNAME(scpsys, 0x0304, VENC_PWR_CON),
+ REGNAME(scpsys, 0x0378, APU_PWR_CON),
+ REGNAME(scpsys, 0x037C, DSP_PWR_CON),
+ {}
+};
+
+static const struct regname *get_all_regnames(void)
+{
+ return rn;
+}
+
+static void __init init_regbase(void)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(rb); i++)
+ rb[i].virt = ioremap(rb[i].phys, PAGE_SIZE);
+}
+
+/*
+ * clkdbg fmeter
+ */
+
+#include <linux/delay.h>
+
+#define clk_readl(addr) readl(addr)
+#define clk_writel(addr, val) \
+ do { writel(val, addr); wmb(); } while (0) /* sync write */
+
+#define FMCLK(_t, _i, _n) { .type = _t, .id = _i, .name = _n }
+#define CKGEN_K1 0x3
+
+static const struct fmeter_clk fclks[] = {
+ FMCLK(CKGEN, 1, "axi_ck"),
+ FMCLK(CKGEN, 2, "mem_ck"),
+ FMCLK(CKGEN, 3, "mm_ck"),
+ FMCLK(CKGEN, 4, "scp_ck"),
+ FMCLK(CKGEN, 5, "mfg_ck"),
+ FMCLK(CKGEN, 7, "camtg_ck"),
+ FMCLK(CKGEN, 8, "camtg1_ck"),
+ FMCLK(CKGEN, 9, "uart_ck"),
+ FMCLK(CKGEN, 10, "f_fspi_ck"),
+ FMCLK(CKGEN, 11, "msdc50_0_hclk_ck"),
+ FMCLK(CKGEN, 12, "fmsdc2_2_hclk_ck"),
+ FMCLK(CKGEN, 13, "msdc50_0_ck"),
+ FMCLK(CKGEN, 14, "msdc50_2_ck"),
+ FMCLK(CKGEN, 15, "msdc30_1_ck"),
+ FMCLK(CKGEN, 16, "audio_ck"),
+ FMCLK(CKGEN, 17, "aud_intbus_ck"),
+ FMCLK(CKGEN, 18, "aud_1_ck"),
+ FMCLK(CKGEN, 19, "aud_2_ck"),
+ FMCLK(CKGEN, 20, "aud_engen1_ck"),
+ FMCLK(CKGEN, 21, "aud_engen2_ck"),
+ FMCLK(CKGEN, 22, "hf_faud_spdif_ck"),
+ FMCLK(CKGEN, 23, "disp_pwm_ck"),
+ FMCLK(CKGEN, 24, "sspm_ck"),
+ FMCLK(CKGEN, 25, "dxcc_ck"),
+ FMCLK(CKGEN, 26, "ssusb_sys_ck"),
+ FMCLK(CKGEN, 27, "ssusb_xhci_ck"),
+ FMCLK(CKGEN, 28, "spm_ck"),
+ FMCLK(CKGEN, 29, "i2c_ck"),
+ FMCLK(CKGEN, 30, "pwm_ck"),
+ FMCLK(CKGEN, 31, "seninf_ck"),
+ FMCLK(CKGEN, 32, "aes_fde_ck"),
+ FMCLK(CKGEN, 33, "camtm_ck"),
+ FMCLK(CKGEN, 34, "dpi0_ck"),
+ FMCLK(CKGEN, 35, "dpi1_ck"),
+ FMCLK(CKGEN, 36, "dsp_ck"),
+ FMCLK(CKGEN, 37, "nfi2x_ck"),
+ FMCLK(CKGEN, 38, "nfiecc_ck"),
+ FMCLK(CKGEN, 39, "ecc_ck"),
+ FMCLK(CKGEN, 40, "eth_ck"),
+ FMCLK(CKGEN, 41, "gcpu_ck"),
+ FMCLK(CKGEN, 42, "gcpu_cpm_ck"),
+ FMCLK(CKGEN, 43, "apu_ck"),
+ FMCLK(CKGEN, 44, "apu_if_ck"),
+ FMCLK(CKGEN, 45, "mbist_diag_clk"),
+ FMCLK(CKGEN, 48, "f_ufs_mp_sap_cfg_ck"),
+ FMCLK(CKGEN, 49, "f_ufs_tick1us_ck"),
+ FMCLK(CKGEN, 50, "hd_faxi_east_ck"),
+ FMCLK(CKGEN, 51, "hd_faxi_west_ck"),
+ FMCLK(CKGEN, 52, "hd_faxi_north_ck"),
+ FMCLK(CKGEN, 53, "hd_faxi_south_ck"),
+ FMCLK(CKGEN, 54, "hd_fmipicfg_tx_ck"),
+ FMCLK(CKGEN, 55, "fmem_ck_bfe_dcm_ch0"),
+ FMCLK(CKGEN, 56, "fmem_ck_aft_dcm_ch0"),
+ FMCLK(CKGEN, 57, "fmem_ck_bfe_dcm_ch1"),
+ FMCLK(CKGEN, 58, "fmem_ck_aft_dcm_ch1"),
+ FMCLK(ABIST, 1, "AD_ARMPLL_CK"),
+ FMCLK(ABIST, 2, "0"),
+ FMCLK(ABIST, 3, "AD_MAINPLL_CK"),
+ FMCLK(ABIST, 4, "AD_CSI0A_CDPHY_DELAYCAL_CK"),
+ FMCLK(ABIST, 5, "AD_CSI0B_CDPHY_DELAYCAL_CK"),
+ FMCLK(ABIST, 7, "AD_USB20_CLK480M"),
+ FMCLK(ABIST, 8, "AD_USB20_CLK480M_1P"),
+ FMCLK(ABIST, 9, "AD_MADADC_26MCKO"),
+ FMCLK(ABIST, 10, "AD_MAINPLL_H546M_CK"),
+ FMCLK(ABIST, 11, "AD_MAINPLL_H364M_CK"),
+ FMCLK(ABIST, 12, "AD_MAINPLL_H218P4M_CK"),
+ FMCLK(ABIST, 13, "AD_MAINPLL_H156M_CK"),
+ FMCLK(ABIST, 14, "AD_UNIVPLL_1248M_CK"),
+ FMCLK(ABIST, 15, "AD_USB20_192M_CK"),
+ FMCLK(ABIST, 16, "AD_UNIVPLL_624M_CK"),
+ FMCLK(ABIST, 17, "AD_UNIVPLL_416M_CK"),
+ FMCLK(ABIST, 18, "AD_UNIVPLL_249P6M_CK"),
+ FMCLK(ABIST, 19, "AD_UNIVPLL_178P3M_CK"),
+ FMCLK(ABIST, 20, "AD_SYS_26M_CK"),
+ FMCLK(ABIST, 21, "AD_CSI1A_DPHY_DELAYCAL_CK"),
+ FMCLK(ABIST, 22, "AD_CSI1B_DPHY_DELAYCAL_CK"),
+ FMCLK(ABIST, 23, "AD_CSI2A_DPHY_DELAYCAL_CK"),
+ FMCLK(ABIST, 24, "AD_CSI2B_DPHY_DELAYCAL_CK"),
+ FMCLK(ABIST, 25, "RTC32K"),
+ FMCLK(ABIST, 26, "AD_MMPLL_CK"),
+ FMCLK(ABIST, 27, "AD_MFGPLL_CK"),
+ FMCLK(ABIST, 28, "AD_MSDCPLL_CK"),
+ FMCLK(ABIST, 29, "AD_DSI0_LNTC_DSICLK"),
+ FMCLK(ABIST, 30, "AD_DSI0_MPPLL_TST_CK"),
+ FMCLK(ABIST, 31, "AD_APPLLGP_TST_CK"),
+ FMCLK(ABIST, 32, "AD_APLL1_CK"),
+ FMCLK(ABIST, 33, "AD_APLL2_CK"),
+ FMCLK(ABIST, 34, "AD_MADCKO_TEST"),
+ FMCLK(ABIST, 35, "AD_MPLL_208M_CK"),
+ FMCLK(ABIST, 36, "Armpll_ll_mon_ck"),
+ FMCLK(ABIST, 37, "vad_clk_i"),
+ FMCLK(ABIST, 38, "msdc01_in_ck"),
+ FMCLK(ABIST, 40, "msdc11_in_ck"),
+ FMCLK(ABIST, 41, "msdc12_in_ck"),
+ FMCLK(ABIST, 42, "AD_PLLGP_TST_CK"),
+ FMCLK(ABIST, 43, "AD_LVDSTX_CLKDIG_CTS"),
+ FMCLK(ABIST, 44, "AD_LVDSTX_CLKDIG"),
+ FMCLK(ABIST, 45, "AD_VPLL_DPIX_CK"),
+ FMCLK(ABIST, 46, "DA_USB20_48M_DIV_CK"),
+ FMCLK(ABIST, 47, "DA_UNIV_48M_DIV_CK"),
+ FMCLK(ABIST, 48, "DA_MPLL_104M_DIV_CK"),
+ FMCLK(ABIST, 49, "DA_MPLL_52M_DIV_CK"),
+ FMCLK(ABIST, 50, "DA_PLLGP_CPU_CK_MON"),
+ FMCLK(ABIST, 51, "trng_freq_debug_out0"),
+ FMCLK(ABIST, 52, "trng_freq_debug_out1"),
+ FMCLK(ABIST, 53, "AD_LVDSTX_MONCLK"),
+ FMCLK(ABIST, 54, "AD_VPLL_MONREF_CK"),
+ FMCLK(ABIST, 55, "AD_VPLL_MONFBK_CK"),
+ FMCLK(ABIST, 56, "AD_LVDSPLL_300M_CK"),
+ FMCLK(ABIST, 57, "AD_DSPPLL_CK"),
+ FMCLK(ABIST, 58, "AD_APUPLL_CK"),
+ {}
+};
+
+#define CLK_MISC_CFG_0 (rb[topckgen].virt + 0x104)
+#define CLK_DBG_CFG (rb[topckgen].virt + 0x10C)
+#define CLK26CALI_0 (rb[topckgen].virt + 0x220)
+#define CLK26CALI_1 (rb[topckgen].virt + 0x224)
+
+static unsigned int mt_get_ckgen_freq(unsigned int ID)
+{
+ int output = 0, i = 0;
+ unsigned int tmp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1, clk26cali_0;
+
+ clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
+ clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFFFC0FC) | (ID << 8) | (0x1));
+
+ clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
+ clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF));
+
+ clk26cali_0 = clk_readl(CLK26CALI_0);
+ clk26cali_1 = clk_readl(CLK26CALI_1);
+ clk_writel(CLK26CALI_1,
+ (clk26cali_1 & ~(0x3FF0000)) | (DEFAULT_CYCLE_COUNT << 16));
+ mdelay(1);
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ mdelay(10);
+ i++;
+ if (i > 10)
+ break;
+ }
+
+ tmp = clk_readl(CLK26CALI_1);
+ output = ((tmp & 0xFFFF) * 26000) / (DEFAULT_CYCLE_COUNT + 1);
+
+ clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
+ clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
+ clk_writel(CLK26CALI_0, clk26cali_0);
+ clk_writel(CLK26CALI_1, clk26cali_1);
+
+ if (i > 10)
+ return 0;
+ else
+ return output;
+
+}
+
+static unsigned int mt_get_abist_freq(unsigned int ID)
+{
+ int output = 0, i = 0;
+ unsigned int tmp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1, clk26cali_0;
+
+ clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
+ clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFC0FFFC) | (ID << 16));
+
+ clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
+ clk_writel(CLK_MISC_CFG_0,
+ (clk_misc_cfg_0 & 0x00FFFFFF) | (CKGEN_K1 << 24));
+
+ clk26cali_0 = clk_readl(CLK26CALI_0);
+ clk26cali_1 = clk_readl(CLK26CALI_1);
+ clk_writel(CLK26CALI_1,
+ (clk26cali_1 & ~(0x3FF0000)) | (DEFAULT_CYCLE_COUNT << 16));
+ mdelay(1);
+ clk_writel(CLK26CALI_0, 0x1000);
+ clk_writel(CLK26CALI_0, 0x1010);
+
+ while (clk_readl(CLK26CALI_0) & 0x10) {
+ mdelay(10);
+ i++;
+ if (i > 10)
+ break;
+ }
+
+ tmp = clk_readl(CLK26CALI_1);
+ output = ((tmp & 0xFFFF) * 26000) / (DEFAULT_CYCLE_COUNT + 1);
+
+ clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
+ clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
+ clk_writel(CLK26CALI_0, clk26cali_0);
+ clk_writel(CLK26CALI_1, clk26cali_1);
+
+ if (i > 10)
+ return 0;
+ else
+ return (output * (CKGEN_K1 + 1));
+}
+
+static u32 fmeter_freq_op(const struct fmeter_clk *fclk)
+{
+ if (fclk->type == ABIST)
+ return mt_get_abist_freq(fclk->id);
+ else if (fclk->type == CKGEN)
+ return mt_get_ckgen_freq(fclk->id);
+ return 0;
+}
+
+static const struct fmeter_clk *get_all_fmeter_clks(void)
+{
+ return fclks;
+}
+
+/*
+ * clkdbg dump_state
+ */
+
+static const char * const *get_all_clk_names(void)
+{
+ static const char * const clks[] = {
+
+ "i2s0_bck",
+ "dsi0_lntc_dsick",
+ "vpll_dpix",
+ "lvdstx_dig_cts",
+ "mfgpll_ck",
+ "syspll_d2",
+ "syspll1_d2",
+ "syspll1_d4",
+ "syspll1_d8",
+ "syspll1_d16",
+ "syspll_d3",
+ "syspll2_d2",
+ "syspll2_d4",
+ "syspll2_d8",
+ "syspll_d5",
+ "syspll3_d2",
+ "syspll3_d4",
+ "syspll_d7",
+ "syspll4_d2",
+ "syspll4_d4",
+ "univpll_d2",
+ "univpll1_d2",
+ "univpll1_d4",
+ "univpll_d3",
+ "univpll2_d2",
+ "univpll2_d4",
+ "univpll2_d8",
+ "univpll2_d32",
+ "univpll_d5",
+ "univpll3_d2",
+ "univpll3_d4",
+ "mmpll_ck",
+ "mmpll_d2",
+ "lvdspll_d2",
+ "lvdspll_d4",
+ "lvdspll_d8",
+ "lvdspll_d16",
+ "usb20_192m_ck",
+ "usb20_192m_d4",
+ "usb20_192m_d8",
+ "usb20_192m_d16",
+ "usb20_192m_d32",
+ "apll1_ck",
+ "apll1_d2",
+ "apll1_d4",
+ "apll1_d8",
+ "apll2_ck",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8",
+ "clk26m_ck",
+ "sys_26m_d2",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "dsppll_ck",
+ "dsppll_d2",
+ "dsppll_d4",
+ "dsppll_d8",
+ "apupll_ck",
+ "mpll_d2",
+ "mpll_d4",
+ "clk26m_d52",
+ "axi_sel",
+ "mem_sel",
+ "mm_sel",
+ "scp_sel",
+ "mfg_sel",
+ "atb_sel",
+ "camtg_sel",
+ "camtg1_sel",
+ "uart_sel",
+ "spi_sel",
+ "msdc50_0_hc_sel",
+ "msdc2_2_hc_sel",
+ "msdc50_0_sel",
+ "msdc50_2_sel",
+ "msdc30_1_sel",
+ "audio_sel",
+ "aud_intbus_sel",
+ "aud_1_sel",
+ "aud_2_sel",
+ "aud_engen1_sel",
+ "aud_engen2_sel",
+ "aud_spdif_sel",
+ "disp_pwm_sel",
+ "dxcc_sel",
+ "ssusb_sys_sel",
+ "ssusb_xhci_sel",
+ "spm_sel",
+ "i2c_sel",
+ "pwm_sel",
+ "senif_sel",
+ "aes_fde_sel",
+ "camtm_sel",
+ "dpi0_sel",
+ "dpi1_sel",
+ "dsp_sel",
+ "nfi2x_sel",
+ "nfiecc_sel",
+ "ecc_sel",
+ "eth_sel",
+ "gcpu_sel",
+ "gcpu_cpm_sel",
+ "apu_sel",
+ "apu_if_sel",
+ "mbist_diag_sel",
+ "apll_i2s0_sel",
+ "apll_i2s1_sel",
+ "apll_i2s2_sel",
+ "apll_i2s3_sel",
+ "apll_tdmout_sel",
+ "apll_tdmin_sel",
+ "apll_spdif_sel",
+ "apll12_ck_div0",
+ "apll12_ck_div1",
+ "apll12_ck_div2",
+ "apll12_ck_div3",
+ "apll12_ck_div4",
+ "apll12_ck_div4b",
+ "apll12_ck_div5",
+ "apll12_ck_div5b",
+ "apll12_ck_div6",
+ "aud_i2s0_m_ck",
+ "aud_i2s1_m_ck",
+ "aud_i2s2_m_ck",
+ "aud_i2s3_m_ck",
+ "aud_tdmout_m_ck",
+ "aud_tdmout_b_ck",
+ "aud_tdmin_m_ck",
+ "aud_tdmin_b_ck",
+ "aud_spdif_m_ck",
+ "usb20_48m_en",
+ "univpll_48m_en",
+ "lvdstx_dig_en",
+ "vpll_dpix_en",
+ "ssusb_top_ck_en",
+ "ssusb_phy_ck_en",
+ "conn_32k",
+ "conn_26m",
+ "dsp_32k",
+ "dsp_26m",
+ "ifr_pmic_tmr",
+ "ifr_pmic_ap",
+ "ifr_pmic_md",
+ "ifr_pmic_conn",
+ "ifr_sej",
+ "ifr_apxgpt",
+ "ifr_icusb",
+ "ifr_gce",
+ "ifr_therm",
+ "ifr_pwm_hclk",
+ "ifr_pwm1",
+ "ifr_pwm2",
+ "ifr_pwm3",
+ "ifr_pwm4",
+ "ifr_pwm5",
+ "ifr_pwm",
+ "ifr_uart0",
+ "ifr_uart1",
+ "ifr_gce_26m",
+ "ifr_cq_dma_fpc",
+ "ifr_btif",
+ "ifr_spi0",
+ "ifr_msdc",
+ "ifr_msdc1",
+ "ifr_dvfsrc",
+ "ifr_gcpu",
+ "ifr_trng",
+ "ifr_auxadc",
+ "ifr_auxadc_md",
+ "ifr_ap_dma",
+ "ifr_device_apc",
+ "ifr_debugsys",
+ "ifr_audio",
+ "ifr_dramc_f26m",
+ "ifr_pwm_fbclk6",
+ "ifr_disp_pwm",
+ "ifr_aud_26m_bk",
+ "ifr_cq_dma",
+ "ifr_msdc0_sf",
+ "ifr_msdc1_sf",
+ "ifr_msdc2_sf",
+ "ifr_ap_msdc0",
+ "ifr_md_msdc0",
+ "ifr_msdc0_src",
+ "ifr_msdc1_src",
+ "ifr_msdc2_src",
+ "ifr_pwrap_tmr",
+ "ifr_pwrap_spi",
+ "ifr_pwrap_sys",
+ "ifr_sej_f13m",
+ "ifr_mcu_pm_bk",
+ "ifr_irrx_26m",
+ "ifr_irrx_32k",
+ "ifr_i2c0_axi",
+ "ifr_i2c1_axi",
+ "ifr_i2c2_axi",
+ "ifr_i2c3_axi",
+ "ifr_nic_axi",
+ "ifr_nic_slv_axi",
+ "ifr_apu_axi",
+ "ifr_nfiecc",
+ "ifr_nfiecc_bk",
+ "ifr_nfi1x_bk",
+ "ifr_nfi_bk",
+ "ifr_msdc2_ap_bk",
+ "ifr_msdc2_md_bk",
+ "ifr_msdc2_bk",
+ "ifr_susb_133_bk",
+ "ifr_susb_66_bk",
+ "ifr_ssusb_sys",
+ "ifr_ssusb_ref",
+ "ifr_ssusb_xhci",
+ "armpll",
+ "mainpll",
+ "univpll",
+ "mfgpll",
+ "msdcpll",
+ "mmpll",
+ "apll1",
+ "apll2",
+ "mpll",
+ "lvdspll",
+ "dsppll",
+ "apupll",
+ "mfg_bg3d",
+ "mfg_mbist_diag",
+ "mm_mdp_rdma0",
+ "mm_mdp_ccorr0",
+ "mm_mdp_rsz0",
+ "mm_mdp_rsz1",
+ "mm_mdp_tdshp0",
+ "mm_mdp_wrot0",
+ "mm_mdp_wdma0",
+ "mm_disp_ovl0",
+ "mm_disp_ovl0_21",
+ "mm_disp_rsz0",
+ "mm_disp_rdma0",
+ "mm_disp_wdma0",
+ "mm_disp_color0",
+ "mm_disp_ccorr0",
+ "mm_disp_aal0",
+ "mm_disp_gamma0",
+ "mm_disp_dither0",
+ "mm_dsi0",
+ "mm_disp_rdma1",
+ "mm_mdp_rdma1",
+ "mm_dpi0_dpi0",
+ "mm_fake",
+ "mm_smi_common",
+ "mm_smi_larb0",
+ "mm_smi_comm0",
+ "mm_smi_comm1",
+ "mm_cam_mdp",
+ "mm_smi_img",
+ "mm_smi_cam",
+ "mm_dl_relay",
+ "mm_dl_async_top",
+ "mm_dsi0_dig_dsi",
+ "mm_f26m_hrtwt",
+ "mm_dpi0",
+ "mm_flvdstx_pxl",
+ "mm_flvdstx_cts",
+ "cam_larb2",
+ "cam",
+ "camtg",
+ "cam_senif",
+ "camsv0",
+ "camsv1",
+ "cam_fdvt",
+ "cam_wpe",
+ "vdec_fvdec_ck",
+ "vdec_flarb1_ck",
+ "venc_fvenc_ck",
+ "venc_jpgenc_ck",
+ /* end */
+ NULL
+ };
+
+ return clks;
+}
+
+/*
+ * clkdbg pwr_status
+ */
+
+static const char * const *get_pwr_names(void)
+{
+ static const char * const pwr_names[] = {
+ [0] = "",
+ [1] = "CONN",
+ [2] = "DDRPHY",
+ [3] = "DISP",
+ [4] = "MFG",
+ [5] = "",
+ [6] = "INFRA",
+ [7] = "",
+ [8] = "MP0_CPUTOP",
+ [9] = "MP0_CPU0",
+ [10] = "MP0_CPU1",
+ [11] = "MP0_CPU2",
+ [12] = "MP0_CPU3",
+ [13] = "",
+ [14] = "MCUSYS",
+ [15] = "",
+ [16] = "APU",
+ [17] = "DSP",
+ [18] = "",
+ [19] = "",
+ [20] = "",
+ [21] = "VENC",
+ [22] = "",
+ [23] = "",
+ [24] = "AUDIO",
+ [25] = "CAM",
+ [26] = "",
+ [27] = "",
+ [28] = "",
+ [29] = "",
+ [30] = "",
+ [31] = "VDEC",
+ };
+
+ return pwr_names;
+}
+
+/*
+ * clkdbg dump_clks
+ */
+
+static void setup_provider_clk(struct provider_clk *pvdck)
+{
+ static const struct {
+ const char *pvdname;
+ u32 pwr_mask;
+ } pvd_pwr_mask[] = {
+ };
+
+ size_t i;
+ const char *pvdname = pvdck->provider_name;
+
+ if (pvdname == NULL)
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(pvd_pwr_mask); i++) {
+ if (strcmp(pvdname, pvd_pwr_mask[i].pvdname) == 0) {
+ pvdck->pwr_mask = pvd_pwr_mask[i].pwr_mask;
+ return;
+ }
+ }
+}
+
+/*
+ * init functions
+ */
+
+static struct clkdbg_ops clkdbg_mt8168_ops = {
+ .get_all_fmeter_clks = get_all_fmeter_clks,
+ .fmeter_freq = fmeter_freq_op,
+ .get_all_regnames = get_all_regnames,
+ .get_all_clk_names = get_all_clk_names,
+ .get_pwr_names = get_pwr_names,
+ .setup_provider_clk = setup_provider_clk,
+};
+
+static void __init init_custom_cmds(void)
+{
+ static const struct cmd_fn cmds[] = {
+ {}
+ };
+
+ set_custom_cmds(cmds);
+}
+
+static int __init clkdbg_mt8168_init(void)
+{
+ if (of_machine_is_compatible("mediatek,mt8168") == 0)
+ return -ENODEV;
+
+ init_regbase();
+
+ init_custom_cmds();
+ set_clkdbg_ops(&clkdbg_mt8168_ops);
+
+#if DUMP_INIT_STATE
+ print_regs();
+ print_fmeter_all();
+#endif /* DUMP_INIT_STATE */
+
+ return 0;
+}
+device_initcall(clkdbg_mt8168_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg.c
new file mode 100644
index 0000000..1c7e688
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg.c
@@ -0,0 +1,1765 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+
+ * Copyright (c) 2020 MediaTek Inc.
+
+ */
+#define pr_fmt(fmt) "[clkdbg] " fmt
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/proc_fs.h>
+#include <linux/fs.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include "clkdbg.h"
+#if defined(CONFIG_PM_DEBUG)
+#define CLKDBG_PM_DOMAIN 1
+#else
+#define CLKDBG_PM_DOMAIN 1 /*WTF*/
+#endif
+#define CLKDBG_PM_DOMAIN_API_4_9 1
+#define CLKDBG_CCF_API_4_4 1
+#define CLKDBG_HACK_CLK 0
+#define CLKDBG_HACK_CLK_CORE 1
+#if !CLKDBG_CCF_API_4_4
+/* backward compatible */
+static const char *clk_hw_get_name(const struct clk_hw *hw)
+{
+ return __clk_get_name(hw->clk);
+}
+static bool clk_hw_is_prepared(const struct clk_hw *hw)
+{
+ return __clk_is_prepared(hw->clk);
+}
+static bool clk_hw_is_enabled(const struct clk_hw *hw)
+{
+ return __clk_is_enabled(hw->clk);
+}
+static unsigned long clk_hw_get_rate(const struct clk_hw *hw)
+{
+ return __clk_get_rate(hw->clk);
+}
+static unsigned int clk_hw_get_num_parents(const struct clk_hw *hw)
+{
+ return __clk_get_num_parents(hw->clk);
+}
+static struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
+ unsigned int index)
+{
+ return __clk_get_hw(clk_get_parent_by_index(hw->clk, index));
+}
+#endif /* !CLKDBG_CCF_API_4_4 */
+#if CLKDBG_HACK_CLK
+#include <linux/clk-private.h>
+static bool clk_hw_is_on(struct clk_hw *hw)
+{
+ const struct clk_ops *ops = hw->clk->ops;
+ if (ops->is_enabled)
+ return clk_hw_is_enabled(hw);
+ else if (ops->is_prepared)
+ return clk_hw_is_prepared(hw);
+ return clk_hw_is_enabled(hw) || clk_hw_is_prepared(hw);
+}
+#elif CLKDBG_HACK_CLK_CORE
+struct clk_core {
+ const char *name;
+ const struct clk_ops *ops;
+ struct clk_hw *hw;
+};
+static bool clk_hw_is_on(struct clk_hw *hw)
+{
+ const struct clk_ops *ops = hw->core->ops;
+ if (ops->is_enabled)
+ return clk_hw_is_enabled(hw);
+ else if (ops->is_prepared)
+ return clk_hw_is_prepared(hw);
+ return clk_hw_is_enabled(hw) || clk_hw_is_prepared(hw);
+}
+#else
+static bool clk_hw_is_on(struct clk_hw *hw)
+{
+ return __clk_get_enable_count(hw->clk) || clk_hw_is_prepared(hw);
+}
+#endif /* !CLKDBG_HACK_CLK && !CLKDBG_HACK_CLK_CORE */
+static const struct clkdbg_ops *clkdbg_ops;
+void set_clkdbg_ops(const struct clkdbg_ops *ops)
+{
+ clkdbg_ops = ops;
+}
+static const struct fmeter_clk *get_all_fmeter_clks(void)
+{
+ if (clkdbg_ops == NULL || clkdbg_ops->get_all_fmeter_clks == NULL)
+ return NULL;
+ return clkdbg_ops->get_all_fmeter_clks();
+}
+static void *prepare_fmeter(void)
+{
+ if (clkdbg_ops == NULL || clkdbg_ops->prepare_fmeter == NULL)
+ return NULL;
+ return clkdbg_ops->prepare_fmeter();
+}
+static void unprepare_fmeter(void *data)
+{
+ if (clkdbg_ops == NULL || clkdbg_ops->unprepare_fmeter == NULL)
+ return;
+ clkdbg_ops->unprepare_fmeter(data);
+}
+static u32 fmeter_freq(const struct fmeter_clk *fclk)
+{
+ if (clkdbg_ops == NULL || clkdbg_ops->fmeter_freq == NULL)
+ return 0;
+ return clkdbg_ops->fmeter_freq(fclk);
+}
+static const struct regname *get_all_regnames(void)
+{
+ if (clkdbg_ops == NULL || clkdbg_ops->get_all_regnames == NULL)
+ return NULL;
+ return clkdbg_ops->get_all_regnames();
+}
+static const char * const *get_all_clk_names(void)
+{
+ if (clkdbg_ops == NULL || clkdbg_ops->get_all_clk_names == NULL)
+ return NULL;
+ return clkdbg_ops->get_all_clk_names();
+}
+static const char * const *get_pwr_names(void)
+{
+ static const char * const default_pwr_names[] = {
+ [0] = "(MD)",
+ [1] = "(CONN)",
+ [2] = "(DDRPHY)",
+ [3] = "(DISP)",
+ [4] = "(MFG)",
+ [5] = "(ISP)",
+ [6] = "(INFRA)",
+ [7] = "(VDEC)",
+ [8] = "(CPU, CA7_CPUTOP)",
+ [9] = "(FC3, CA7_CPU0, CPUTOP)",
+ [10] = "(FC2, CA7_CPU1, CPU3)",
+ [11] = "(FC1, CA7_CPU2, CPU2)",
+ [12] = "(FC0, CA7_CPU3, CPU1)",
+ [13] = "(MCUSYS, CA7_DBG, CPU0)",
+ [14] = "(MCUSYS, VEN, BDP)",
+ [15] = "(CA15_CPUTOP, ETH, MCUSYS)",
+ [16] = "(CA15_CPU0, HIF)",
+ [17] = "(CA15_CPU1, CA15-CX0, INFRA_MISC)",
+ [18] = "(CA15_CPU2, CA15-CX1)",
+ [19] = "(CA15_CPU3, CA15-CPU0)",
+ [20] = "(VEN2, MJC, CA15-CPU1)",
+ [21] = "(VEN, CA15-CPUTOP)",
+ [22] = "(MFG_2D)",
+ [23] = "(MFG_ASYNC, DBG)",
+ [24] = "(AUDIO, MFG_2D)",
+ [25] = "(USB, VCORE_PDN, MFG_ASYNC)",
+ [26] = "(ARMPLL_DIV, CPUTOP_SRM_SLPB)",
+ [27] = "(MD2, CPUTOP_SRM_PDN)",
+ [28] = "(CPU3_SRM_PDN)",
+ [29] = "(CPU2_SRM_PDN)",
+ [30] = "(CPU1_SRM_PDN)",
+ [31] = "(CPU0_SRM_PDN)",
+ };
+ if (clkdbg_ops == NULL || clkdbg_ops->get_pwr_names == NULL)
+ return default_pwr_names;
+ return clkdbg_ops->get_pwr_names();
+}
+static void setup_provider_clk(struct provider_clk *pvdck)
+{
+ if (clkdbg_ops == NULL || clkdbg_ops->setup_provider_clk == NULL)
+ return;
+ clkdbg_ops->setup_provider_clk(pvdck);
+}
+static bool is_valid_reg(void __iomem *addr)
+{
+#ifdef CONFIG_64BIT
+ return ((u64)addr & 0xf0000000) != 0UL ||
+ (((u64)addr >> 32U) & 0xf0000000) != 0UL;
+#else
+ return ((u32)addr & 0xf0000000) != 0U;
+#endif
+}
+enum clkdbg_opt {
+ CLKDBG_EN_SUSPEND_SAVE_1,
+ CLKDBG_EN_SUSPEND_SAVE_2,
+ CLKDBG_EN_SUSPEND_SAVE_3,
+ CLKDBG_EN_LOG_SAVE_POINTS,
+};
+static u32 clkdbg_flags;
+static void set_clkdbg_flag(enum clkdbg_opt opt)
+{
+ clkdbg_flags |= BIT(opt);
+}
+static void clr_clkdbg_flag(enum clkdbg_opt opt)
+{
+ clkdbg_flags &= ~BIT(opt);
+}
+static bool has_clkdbg_flag(enum clkdbg_opt opt)
+{
+ return (clkdbg_flags & BIT(opt)) != 0U;
+}
+typedef void (*fn_fclk_freq_proc)(const struct fmeter_clk *fclk,
+ u32 freq, void *data);
+static void proc_all_fclk_freq(fn_fclk_freq_proc proc, void *data)
+{
+ void *fmeter_data;
+ const struct fmeter_clk *fclk;
+ fclk = get_all_fmeter_clks();
+ if (fclk == NULL || proc == NULL)
+ return;
+ fmeter_data = prepare_fmeter();
+ for (; fclk->type != FT_NULL; fclk++) {
+ u32 freq;
+ freq = fmeter_freq(fclk);
+ proc(fclk, freq, data);
+ }
+ unprepare_fmeter(fmeter_data);
+}
+static void print_fclk_freq(const struct fmeter_clk *fclk, u32 freq, void *data)
+{
+ pr_info("%2d: %-29s: %u\n", fclk->id, fclk->name, freq);
+}
+void print_fmeter_all(void)
+{
+ proc_all_fclk_freq(print_fclk_freq, NULL);
+}
+static void seq_print_fclk_freq(const struct fmeter_clk *fclk,
+ u32 freq, void *data)
+{
+ struct seq_file *s = data;
+ seq_printf(s, "%2d: %-29s: %u\n", fclk->id, fclk->name, freq);
+}
+static int seq_print_fmeter_all(struct seq_file *s, void *v)
+{
+ proc_all_fclk_freq(seq_print_fclk_freq, s);
+ return 0;
+}
+typedef void (*fn_regname_proc)(const struct regname *rn, void *data);
+static void proc_all_regname(fn_regname_proc proc, void *data)
+{
+ const struct regname *rn = get_all_regnames();
+ if (rn == NULL)
+ return;
+ for (; rn->base != NULL; rn++)
+ proc(rn, data);
+}
+static void print_reg(const struct regname *rn, void *data)
+{
+ if (!is_valid_reg(ADDR(rn)))
+ return;
+ pr_info("%-21s: [0x%08x][0x%p] = 0x%08x\n",
+ rn->name, PHYSADDR(rn), ADDR(rn), clk_readl(ADDR(rn)));
+}
+void print_regs(void)
+{
+ proc_all_regname(print_reg, NULL);
+}
+static void seq_print_reg(const struct regname *rn, void *data)
+{
+ struct seq_file *s = data;
+ const char *pg = rn->base->pg;
+ struct clk *clk;
+ struct clk_hw *c_hw;
+ bool is_pwr_on = true;
+ if (!is_valid_reg(ADDR(rn)))
+ return;
+ if (pg) {
+ clk = __clk_lookup(pg);
+ if (!clk)
+ return;
+ c_hw = __clk_get_hw(clk);
+ if (c_hw)
+ is_pwr_on = clk_hw_is_prepared(c_hw);
+ }
+ if (is_pwr_on)
+ seq_printf(s, "%-21s: [0x%08x][0x%p] = 0x%08x\n",
+ rn->name, PHYSADDR(rn), ADDR(rn), clk_readl(ADDR(rn)));
+ else
+ seq_printf(s, "%-21s: [0x%08x][0x%p] cannot read, pwr_off\n",
+ rn->name, PHYSADDR(rn), ADDR(rn));
+}
+static int seq_print_regs(struct seq_file *s, void *v)
+{
+ proc_all_regname(seq_print_reg, s);
+ return 0;
+}
+static void print_reg2(const struct regname *rn, void *data)
+{
+ if (!is_valid_reg(ADDR(rn)))
+ return;
+ pr_info("%-21s: [0x%08x][0x%p] = 0x%08x\n",
+ rn->name, PHYSADDR(rn), ADDR(rn), clk_readl(ADDR(rn)));
+ msleep(20);
+}
+static int clkdbg_dump_regs2(struct seq_file *s, void *v)
+{
+ proc_all_regname(print_reg2, s);
+ return 0;
+}
+static u32 read_spm_pwr_status(void)
+{
+ static void __iomem *scpsys_base, *pwr_sta, *pwr_sta_2nd;
+ if (clkdbg_ops == NULL || clkdbg_ops->get_spm_pwr_status == NULL) {
+ if (scpsys_base == NULL ||
+ pwr_sta == NULL || pwr_sta_2nd == NULL) {
+ scpsys_base = ioremap(0x10006000, PAGE_SIZE);
+ pwr_sta = scpsys_base + 0x16c;
+ pwr_sta_2nd = scpsys_base + 0x170;
+ }
+ return clk_readl(pwr_sta) & clk_readl(pwr_sta_2nd);
+ } else
+ return clkdbg_ops->get_spm_pwr_status();
+}
+static bool clk_hw_pwr_is_on(struct clk_hw *c_hw,
+ u32 spm_pwr_status, u32 pwr_mask)
+{
+ if ((spm_pwr_status & pwr_mask) != pwr_mask)
+ return false;
+ return clk_hw_is_on(c_hw);
+}
+static bool pvdck_pwr_is_on(struct provider_clk *pvdck, u32 spm_pwr_status)
+{
+ struct clk *c = pvdck->ck;
+ struct clk_hw *c_hw = __clk_get_hw(c);
+ return clk_hw_pwr_is_on(c_hw, spm_pwr_status, pvdck->pwr_mask);
+}
+static bool pvdck_is_on(struct provider_clk *pvdck)
+{
+ u32 val = 0;
+ if (clkdbg_ops == NULL || clkdbg_ops->is_pwr_on == NULL) {
+ if (pvdck->pwr_mask != 0U)
+ val = read_spm_pwr_status();
+ return pvdck_pwr_is_on(pvdck, val);
+ }
+ val = clkdbg_ops->is_pwr_on(pvdck);
+ return val;
+}
+static const char *ccf_state(struct clk_hw *hw)
+{
+ if (__clk_get_enable_count(hw->clk))
+ return "enabled";
+ if (clk_hw_is_prepared(hw))
+ return "prepared";
+ return "disabled";
+}
+static void dump_clk_state(const char *clkname, struct seq_file *s)
+{
+ struct clk *c = __clk_lookup(clkname);
+ struct clk *p = IS_ERR_OR_NULL(c) ? NULL : clk_get_parent(c);
+ struct clk_hw *c_hw = __clk_get_hw(c);
+ struct clk_hw *p_hw = __clk_get_hw(p);
+ if (IS_ERR_OR_NULL(c)) {
+ seq_printf(s, "[%17s: NULL]\n", clkname);
+ return;
+ }
+ seq_printf(s, "[%-17s: %8s, %3d, %3d, %10ld, %17s]\n",
+ clk_hw_get_name(c_hw),
+ ccf_state(c_hw),
+ clk_hw_is_prepared(c_hw),
+ __clk_get_enable_count(c),
+ clk_hw_get_rate(c_hw),
+ p != NULL ? clk_hw_get_name(p_hw) : "- ");
+}
+static int clkdbg_dump_state_all(struct seq_file *s, void *v)
+{
+ const char * const *ckn = get_all_clk_names();
+ if (ckn == NULL)
+ return 0;
+ for (; *ckn != NULL; ckn++)
+ dump_clk_state(*ckn, s);
+ return 0;
+}
+static const char *get_provider_name(struct device_node *node, u32 *cells)
+{
+ const char *name;
+ const char *p;
+ u32 cc = 1;
+ if (of_property_read_u32(node, "#clock-cells", &cc) != 0)
+ cc = 0;
+ if (cells != NULL)
+ *cells = cc;
+ if (cc == 0U) {
+ if (of_property_read_string(node,
+ "clock-output-names", &name) < 0)
+ name = node->name;
+ return name;
+ }
+ if (of_property_read_string(node, "compatible", &name) < 0)
+ name = node->name;
+ p = strchr(name, (int)'-');
+ if (p != NULL)
+ return p + 1;
+ else
+ return name;
+}
+struct provider_clk *get_all_provider_clks(void)
+{
+ static struct provider_clk provider_clks[1024];
+ struct device_node *node = NULL;
+ int n = 0;
+ if (provider_clks[0].ck != NULL)
+ return provider_clks;
+ do {
+ const char *node_name;
+ u32 cells;
+ node = of_find_node_with_property(node, "#clock-cells");
+ if (node == NULL)
+ break;
+ node_name = get_provider_name(node, &cells);
+ if (cells == 0U) {
+ struct clk *ck = __clk_lookup(node_name);
+ if (IS_ERR_OR_NULL(ck))
+ continue;
+ provider_clks[n].ck = ck;
+ setup_provider_clk(&provider_clks[n]);
+ ++n;
+ } else {
+ unsigned int i;
+ for (i = 0; i < 256; i++) {
+ struct of_phandle_args pa;
+ struct clk *ck;
+ pa.np = node;
+ pa.args[0] = i;
+ pa.args_count = 1;
+ ck = of_clk_get_from_provider(&pa);
+ if (PTR_ERR(ck) == -EINVAL)
+ break;
+ else if (IS_ERR_OR_NULL(ck))
+ continue;
+ provider_clks[n].ck = ck;
+ provider_clks[n].idx = i;
+ provider_clks[n].provider_name = node_name;
+ setup_provider_clk(&provider_clks[n]);
+ ++n;
+ }
+ }
+ } while (node != NULL);
+ return provider_clks;
+}
+static void dump_provider_clk(struct provider_clk *pvdck, struct seq_file *s)
+{
+ struct clk *c = pvdck->ck;
+ struct clk *p = IS_ERR_OR_NULL(c) ? NULL : clk_get_parent(c);
+ struct clk_hw *c_hw = __clk_get_hw(c);
+ struct clk_hw *p_hw = __clk_get_hw(p);
+ seq_printf(s, "[%10s: %-17s: %3s, %3d, %3d, %10ld, %17s]\n",
+ pvdck->provider_name != NULL ? pvdck->provider_name : "/ ",
+ clk_hw_get_name(c_hw),
+ pvdck_is_on(pvdck) ? "ON" : "off",
+ clk_hw_is_prepared(c_hw),
+ __clk_get_enable_count(c),
+ clk_hw_get_rate(c_hw),
+ p != NULL ? clk_hw_get_name(p_hw) : "- ");
+}
+static int clkdbg_dump_provider_clks(struct seq_file *s, void *v)
+{
+ struct provider_clk *pvdck = get_all_provider_clks();
+ for (; pvdck->ck != NULL; pvdck++)
+ dump_provider_clk(pvdck, s);
+ return 0;
+}
+static void dump_provider_mux(struct provider_clk *pvdck, struct seq_file *s)
+{
+ unsigned int i;
+ struct clk *c = pvdck->ck;
+ struct clk_hw *c_hw = __clk_get_hw(c);
+ unsigned int np = clk_hw_get_num_parents(c_hw);
+ if (np <= 1U)
+ return;
+ dump_provider_clk(pvdck, s);
+ for (i = 0; i < np; i++) {
+ struct clk_hw *p_hw = clk_hw_get_parent_by_index(c_hw, i);
+ if (IS_ERR_OR_NULL(p_hw))
+ continue;
+ seq_printf(s, "\t\t\t(%2d: %-17s: %8s, %10ld)\n",
+ i,
+ clk_hw_get_name(p_hw),
+ ccf_state(p_hw),
+ clk_hw_get_rate(p_hw));
+ }
+}
+static int clkdbg_dump_muxes(struct seq_file *s, void *v)
+{
+ struct provider_clk *pvdck = get_all_provider_clks();
+ for (; pvdck->ck != NULL; pvdck++)
+ dump_provider_mux(pvdck, s);
+ return 0;
+}
+static void show_pwr_status(u32 spm_pwr_status)
+{
+ unsigned int i;
+ const char * const *pwr_name = get_pwr_names();
+ pr_info("SPM_PWR_STATUS: 0x%08x\n\n", spm_pwr_status);
+ for (i = 0; i < 32; i++) {
+ const char *st = (spm_pwr_status & BIT(i)) != 0U ? "ON" : "off";
+ pr_info("[%2d]: %3s: %s\n", i, st, pwr_name[i]);
+ mdelay(20);
+ }
+}
+static int dump_pwr_status(u32 spm_pwr_status, struct seq_file *s)
+{
+ unsigned int i;
+ const char * const *pwr_name = get_pwr_names();
+ seq_printf(s, "SPM_PWR_STATUS: 0x%08x\n\n", spm_pwr_status);
+ for (i = 0; i < 32; i++) {
+ const char *st = (spm_pwr_status & BIT(i)) != 0U ? "ON" : "off";
+ seq_printf(s, "[%2d]: %3s: %s\n", i, st, pwr_name[i]);
+ }
+ return 0;
+}
+static int clkdbg_pwr_status(struct seq_file *s, void *v)
+{
+ return dump_pwr_status(read_spm_pwr_status(), s);
+}
+static char last_cmd[128] = "null";
+const char *get_last_cmd(void)
+{
+ return last_cmd;
+}
+static int clkop_int_ckname(int (*clkop)(struct clk *clk),
+ const char *clkop_name, const char *clk_name,
+ struct clk *ck, struct seq_file *s)
+{
+ struct clk *clk;
+ if (!IS_ERR_OR_NULL(ck)) {
+ clk = ck;
+ } else {
+ clk = __clk_lookup(clk_name);
+ if (IS_ERR_OR_NULL(clk)) {
+ seq_printf(s, "clk_lookup(%s): 0x%p\n", clk_name, clk);
+ return PTR_ERR(clk);
+ }
+ }
+ return clkop(clk);
+}
+static int clkdbg_clkop_int_ckname(int (*clkop)(struct clk *clk),
+ const char *clkop_name, struct seq_file *s, void *v)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *clk_name;
+ int r = 0;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ clk_name = strsep(&c, " ");
+ if (clk_name == NULL)
+ return 0;
+ if (strcmp(clk_name, "all") == 0) {
+ struct provider_clk *pvdck = get_all_provider_clks();
+ for (; pvdck->ck != NULL; pvdck++) {
+ r |= clkop_int_ckname(clkop, clkop_name, NULL,
+ pvdck->ck, s);
+ }
+ seq_printf(s, "%s(%s): %d\n", clkop_name, clk_name, r);
+ return r;
+ }
+ r = clkop_int_ckname(clkop, clkop_name, clk_name, NULL, s);
+ seq_printf(s, "%s(%s): %d\n", clkop_name, clk_name, r);
+ return r;
+}
+static void clkop_void_ckname(void (*clkop)(struct clk *clk),
+ const char *clkop_name, const char *clk_name,
+ struct clk *ck, struct seq_file *s)
+{
+ struct clk *clk;
+ if (!IS_ERR_OR_NULL(ck)) {
+ clk = ck;
+ } else {
+ clk = __clk_lookup(clk_name);
+ if (IS_ERR_OR_NULL(clk)) {
+ seq_printf(s, "clk_lookup(%s): 0x%p\n", clk_name, clk);
+ return;
+ }
+ }
+ clkop(clk);
+}
+static int clkdbg_clkop_void_ckname(void (*clkop)(struct clk *clk),
+ const char *clkop_name, struct seq_file *s, void *v)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *clk_name;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ clk_name = strsep(&c, " ");
+ if (clk_name == NULL)
+ return 0;
+ if (strcmp(clk_name, "all") == 0) {
+ struct provider_clk *pvdck = get_all_provider_clks();
+ for (; pvdck->ck != NULL; pvdck++) {
+ clkop_void_ckname(clkop, clkop_name, NULL,
+ pvdck->ck, s);
+ }
+ seq_printf(s, "%s(%s)\n", clkop_name, clk_name);
+ return 0;
+ }
+ clkop_void_ckname(clkop, clkop_name, clk_name, NULL, s);
+ seq_printf(s, "%s(%s)\n", clkop_name, clk_name);
+ return 0;
+}
+static int clkdbg_prepare(struct seq_file *s, void *v)
+{
+ return clkdbg_clkop_int_ckname(clk_prepare,
+ "clk_prepare", s, v);
+}
+static int clkdbg_unprepare(struct seq_file *s, void *v)
+{
+ return clkdbg_clkop_void_ckname(clk_unprepare,
+ "clk_unprepare", s, v);
+}
+static int clkdbg_enable(struct seq_file *s, void *v)
+{
+ return clkdbg_clkop_int_ckname(clk_enable,
+ "clk_enable", s, v);
+}
+static int clkdbg_disable(struct seq_file *s, void *v)
+{
+ return clkdbg_clkop_void_ckname(clk_disable,
+ "clk_disable", s, v);
+}
+static int clkdbg_prepare_enable(struct seq_file *s, void *v)
+{
+ return clkdbg_clkop_int_ckname(clk_prepare_enable,
+ "clk_prepare_enable", s, v);
+}
+static int clkdbg_disable_unprepare(struct seq_file *s, void *v)
+{
+ return clkdbg_clkop_void_ckname(clk_disable_unprepare,
+ "clk_disable_unprepare", s, v);
+}
+void prepare_enable_provider(const char *pvd)
+{
+ bool allpvd = (pvd == NULL || strcmp(pvd, "all") == 0);
+ struct provider_clk *pvdck = get_all_provider_clks();
+ for (; pvdck->ck != NULL; pvdck++) {
+ if (allpvd || (pvdck->provider_name != NULL &&
+ strcmp(pvd, pvdck->provider_name) == 0)) {
+ int r = clk_prepare_enable(pvdck->ck);
+ if (r != 0)
+ pr_info("clk_prepare_enable(): %d\n", r);
+ }
+ }
+}
+void disable_unprepare_provider(const char *pvd)
+{
+ bool allpvd = (pvd == NULL || strcmp(pvd, "all") == 0);
+ struct provider_clk *pvdck = get_all_provider_clks();
+ for (; pvdck->ck != NULL; pvdck++) {
+ if (allpvd || (pvdck->provider_name != NULL &&
+ strcmp(pvd, pvdck->provider_name) == 0))
+ clk_disable_unprepare(pvdck->ck);
+ }
+}
+static void clkpvdop(void (*pvdop)(const char *), const char *clkpvdop_name,
+ struct seq_file *s)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *pvd_name;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ pvd_name = strsep(&c, " ");
+ if (pvd_name == NULL)
+ return;
+ pvdop(pvd_name);
+ seq_printf(s, "%s(%s)\n", clkpvdop_name, pvd_name);
+}
+static int clkdbg_prepare_enable_provider(struct seq_file *s, void *v)
+{
+ clkpvdop(prepare_enable_provider, "prepare_enable_provider", s);
+ return 0;
+}
+static int clkdbg_disable_unprepare_provider(struct seq_file *s, void *v)
+{
+ clkpvdop(disable_unprepare_provider, "disable_unprepare_provider", s);
+ return 0;
+}
+static int clkdbg_set_parent(struct seq_file *s, void *v)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *clk_name;
+ char *parent_name;
+ struct clk *clk;
+ struct clk *parent;
+ int r;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ clk_name = strsep(&c, " ");
+ parent_name = strsep(&c, " ");
+ if (clk_name == NULL || parent_name == NULL)
+ return 0;
+ seq_printf(s, "clk_set_parent(%s, %s): ", clk_name, parent_name);
+ clk = __clk_lookup(clk_name);
+ if (IS_ERR_OR_NULL(clk)) {
+ seq_printf(s, "__clk_lookup(): 0x%p\n", clk);
+ return PTR_ERR(clk);
+ }
+ parent = __clk_lookup(parent_name);
+ if (IS_ERR_OR_NULL(parent)) {
+ seq_printf(s, "__clk_lookup(): 0x%p\n", parent);
+ return PTR_ERR(parent);
+ }
+ r = clk_prepare_enable(clk);
+ if (r != 0) {
+ seq_printf(s, "clk_prepare_enable(): %d\n", r);
+ return r;
+ }
+ r = clk_set_parent(clk, parent);
+ seq_printf(s, "%d\n", r);
+ clk_disable_unprepare(clk);
+ return r;
+}
+static int clkdbg_set_rate(struct seq_file *s, void *v)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *clk_name;
+ char *rate_str;
+ struct clk *clk;
+ unsigned long rate = 0;
+ int r;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ clk_name = strsep(&c, " ");
+ rate_str = strsep(&c, " ");
+ if (clk_name == NULL || rate_str == NULL)
+ return 0;
+ r = kstrtoul(rate_str, 0, &rate);
+ seq_printf(s, "clk_set_rate(%s, %lu): %d: ", clk_name, rate, r);
+ clk = __clk_lookup(clk_name);
+ if (IS_ERR_OR_NULL(clk)) {
+ seq_printf(s, "__clk_lookup(): 0x%p\n", clk);
+ return PTR_ERR(clk);
+ }
+ r = clk_set_rate(clk, rate);
+ seq_printf(s, "%d\n", r);
+ return r;
+}
+static void *reg_from_str(const char *str)
+{
+ static phys_addr_t phys;
+ static void __iomem *virt;
+ if (sizeof(void *) == sizeof(unsigned long)) {
+ unsigned long v = 0;
+ if (kstrtoul(str, 0, &v) == 0U) {
+ if ((0xf0000000 & v) < 0x20000000) {
+ if (virt != NULL && v > phys
+ && v < phys + PAGE_SIZE)
+ return virt + v - phys;
+ if (virt != NULL)
+ iounmap(virt);
+ phys = v & ~(PAGE_SIZE - 1U);
+ virt = ioremap(phys, PAGE_SIZE);
+ return virt + v - phys;
+ }
+ return (void *)((uintptr_t)v);
+ }
+ } else if (sizeof(void *) == sizeof(unsigned long long)) {
+ unsigned long long v;
+ if (kstrtoull(str, 0, &v) == 0) {
+ if ((0xfffffffff0000000ULL & v) < 0x20000000) {
+ if (virt && v > phys && v < phys + PAGE_SIZE)
+ return virt + v - phys;
+ if (virt != NULL)
+ iounmap(virt);
+ phys = v & ~(PAGE_SIZE - 1);
+ virt = ioremap(phys, PAGE_SIZE);
+ return virt + v - phys;
+ }
+ return (void *)((uintptr_t)v);
+ }
+ } else {
+ pr_warn("unexpected pointer size: sizeof(void *): %zu\n",
+ sizeof(void *));
+ }
+ pr_warn("%s(): parsing error: %s\n", __func__, str);
+ return NULL;
+}
+static int parse_reg_val_from_cmd(void __iomem **preg, unsigned long *pval)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *reg_str;
+ char *val_str;
+ int r = 0;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ reg_str = strsep(&c, " ");
+ val_str = strsep(&c, " ");
+ if (preg != NULL && reg_str != NULL) {
+ *preg = reg_from_str(reg_str);
+ if (*preg != NULL)
+ r++;
+ }
+ if (pval != NULL && val_str != NULL && kstrtoul(val_str, 0, pval) == 0)
+ r++;
+ return r;
+}
+static int clkdbg_reg_read(struct seq_file *s, void *v)
+{
+ void __iomem *reg;
+ unsigned long val = 0;
+ if (parse_reg_val_from_cmd(®, NULL) != 1)
+ return 0;
+ seq_printf(s, "readl(0x%p): ", reg);
+ val = clk_readl(reg);
+ seq_printf(s, "0x%08x\n", (u32)val);
+ return 0;
+}
+static int clkdbg_reg_write(struct seq_file *s, void *v)
+{
+ void __iomem *reg;
+ unsigned long val = 0;
+ if (parse_reg_val_from_cmd(®, &val) != 2)
+ return 0;
+ seq_printf(s, "writel(0x%p, 0x%08x): ", reg, (u32)val);
+ clk_writel(reg, val);
+ val = clk_readl(reg);
+ seq_printf(s, "0x%08x\n", (u32)val);
+ return 0;
+}
+static int clkdbg_reg_set(struct seq_file *s, void *v)
+{
+ void __iomem *reg;
+ unsigned long val = 0;
+ if (parse_reg_val_from_cmd(®, &val) != 2)
+ return 0;
+ seq_printf(s, "writel(0x%p, 0x%08x): ", reg, (u32)val);
+ clk_setl(reg, val);
+ val = clk_readl(reg);
+ seq_printf(s, "0x%08x\n", (u32)val);
+ return 0;
+}
+static int clkdbg_reg_clr(struct seq_file *s, void *v)
+{
+ void __iomem *reg;
+ unsigned long val = 0;
+ if (parse_reg_val_from_cmd(®, &val) != 2)
+ return 0;
+ seq_printf(s, "writel(0x%p, 0x%08x): ", reg, (u32)val);
+ clk_clrl(reg, val);
+ val = clk_readl(reg);
+ seq_printf(s, "0x%08x\n", (u32)val);
+ return 0;
+}
+static int parse_val_from_cmd(unsigned long *pval)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *val_str;
+ int r = 0;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ val_str = strsep(&c, " ");
+ if (pval != NULL && val_str != NULL && kstrtoul(val_str, 0, pval) == 0)
+ r++;
+ return r;
+}
+static int clkdbg_show_flags(struct seq_file *s, void *v)
+{
+ static const char * const clkdbg_opt_name[] = {
+ "CLKDBG_EN_SUSPEND_SAVE_1",
+ "CLKDBG_EN_SUSPEND_SAVE_2",
+ "CLKDBG_EN_SUSPEND_SAVE_3",
+ "CLKDBG_EN_LOG_SAVE_POINTS",
+ };
+ size_t i;
+ seq_printf(s, "clkdbg_flags: 0x%08x\n", clkdbg_flags);
+ for (i = 0; i < ARRAY_SIZE(clkdbg_opt_name); i++) {
+ const char *onff =
+ has_clkdbg_flag((enum clkdbg_opt)i) ? "ON" : "off";
+ seq_printf(s, "[%2zd]: %3s: %s\n", i, onff, clkdbg_opt_name[i]);
+ }
+ return 0;
+}
+static int clkdbg_set_flag(struct seq_file *s, void *v)
+{
+ unsigned long val = 0;
+ if (parse_val_from_cmd(&val) != 1)
+ return 0;
+ set_clkdbg_flag((enum clkdbg_opt)val);
+ seq_printf(s, "clkdbg_flags: 0x%08x\n", clkdbg_flags);
+ return 0;
+}
+static int clkdbg_clr_flag(struct seq_file *s, void *v)
+{
+ unsigned long val = 0;
+ if (parse_val_from_cmd(&val) != 1)
+ return 0;
+ clr_clkdbg_flag((enum clkdbg_opt)val);
+ seq_printf(s, "clkdbg_flags: 0x%08x\n", clkdbg_flags);
+ return 0;
+}
+#if CLKDBG_PM_DOMAIN
+/*
+ * pm_domain support
+ */
+static struct generic_pm_domain **get_all_genpd(void)
+{
+ static struct generic_pm_domain *pds[31];
+ static int num_pds;
+ const size_t maxpd = ARRAY_SIZE(pds);
+ struct device_node *node;
+#if CLKDBG_PM_DOMAIN_API_4_9
+ struct platform_device *pdev;
+ int r;
+#endif
+ if (num_pds != 0)
+ goto out;
+ node = of_find_node_with_property(NULL, "#power-domain-cells");
+ if (node == NULL)
+ return NULL;
+#if CLKDBG_PM_DOMAIN_API_4_9
+ pdev = platform_device_alloc("traverse", 0);
+#endif
+ for (num_pds = 0; num_pds < maxpd; num_pds++) {
+ struct of_phandle_args pa;
+ pa.np = node;
+ pa.args[0] = num_pds;
+ pa.args_count = 1;
+#if CLKDBG_PM_DOMAIN_API_4_9
+ r = of_genpd_add_device(&pa, &pdev->dev);
+ if (r == -EINVAL)
+ continue;
+ else if (r != 0)
+ pr_warn("%s(): of_genpd_add_device(%d)\n", __func__, r);
+ pds[num_pds] = pd_to_genpd(pdev->dev.pm_domain);
+ //r = pm_genpd_remove_device(pds[num_pds], &pdev->dev);
+ r = pm_genpd_remove_device(&pdev->dev);
+ if (r != 0)
+ pr_warn("%s(): pm_genpd_remove_device(%d)\n",
+ __func__, r);
+#else
+ pds[num_pds] = of_genpd_get_from_provider(&pa);
+#endif
+ if (IS_ERR(pds[num_pds])) {
+ pds[num_pds] = NULL;
+ break;
+ }
+ }
+#if CLKDBG_PM_DOMAIN_API_4_9
+ platform_device_put(pdev);
+#endif
+out:
+ return pds;
+}
+static struct platform_device *pdev_from_name(const char *name)
+{
+ struct generic_pm_domain **pds = get_all_genpd();
+ for (; *pds != NULL; pds++) {
+ struct pm_domain_data *pdd;
+ struct generic_pm_domain *pd = *pds;
+ if (IS_ERR_OR_NULL(pd))
+ continue;
+ list_for_each_entry(pdd, &pd->dev_list, list_node) {
+ struct device *dev = pdd->dev;
+ struct platform_device *pdev = to_platform_device(dev);
+ if (strcmp(name, pdev->name) == 0)
+ return pdev;
+ }
+ }
+ return NULL;
+}
+static struct generic_pm_domain *genpd_from_name(const char *name)
+{
+ struct generic_pm_domain **pds = get_all_genpd();
+ for (; *pds != NULL; pds++) {
+ struct generic_pm_domain *pd = *pds;
+ if (IS_ERR_OR_NULL(pd))
+ continue;
+ if (strcmp(name, pd->name) == 0)
+ return pd;
+ }
+ return NULL;
+}
+struct genpd_dev_state {
+ struct device *dev;
+ bool active;
+ atomic_t usage_count;
+ unsigned int disable_depth;
+ enum rpm_status runtime_status;
+};
+struct genpd_state {
+ struct generic_pm_domain *pd;
+ enum gpd_status status;
+ struct genpd_dev_state *dev_state;
+ int num_dev_state;
+};
+static void save_all_genpd_state(struct genpd_state *genpd_states,
+ struct genpd_dev_state *genpd_dev_states)
+{
+ struct genpd_state *pdst = genpd_states;
+ struct genpd_dev_state *devst = genpd_dev_states;
+ struct generic_pm_domain **pds = get_all_genpd();
+ for (; *pds != NULL; pds++) {
+ struct pm_domain_data *pdd;
+ struct generic_pm_domain *pd = *pds;
+ if (IS_ERR_OR_NULL(pd))
+ continue;
+ pdst->pd = pd;
+ pdst->status = pd->status;
+ pdst->dev_state = devst;
+ pdst->num_dev_state = 0;
+ list_for_each_entry(pdd, &pd->dev_list, list_node) {
+ struct device *d = pdd->dev;
+ devst->dev = d;
+ devst->active = pm_runtime_active(d);
+ devst->usage_count = d->power.usage_count;
+ devst->disable_depth = d->power.disable_depth;
+ devst->runtime_status = d->power.runtime_status;
+ devst++;
+ pdst->num_dev_state++;
+ }
+ pdst++;
+ }
+ pdst->pd = NULL;
+ devst->dev = NULL;
+}
+static void show_genpd_state(struct genpd_state *pdst)
+{
+ static const char * const gpd_status_name[] = {
+ "ACTIVE",
+ "POWER_OFF",
+ };
+ static const char * const prm_status_name[] = {
+ "active",
+ "resuming",
+ "suspended",
+ "suspending",
+ };
+ pr_info("domain_on [pmd_name status]\n");
+ pr_info("\tdev_on (dev_name usage_count, disable, status)\n");
+ pr_info("------------------------------------------------------\n");
+ for (; pdst->pd != NULL; pdst++) {
+ int i;
+ struct generic_pm_domain *pd = pdst->pd;
+ if (IS_ERR_OR_NULL(pd)) {
+ pr_info("pd: 0x%p\n", pd);
+ continue;
+ }
+ pr_info("%c [%-9s %11s]\n",
+ (pdst->status == GPD_STATE_ACTIVE) ? '+' : '-',
+ pd->name, gpd_status_name[pdst->status]);
+ for (i = 0; i < pdst->num_dev_state; i++) {
+ struct genpd_dev_state *devst = &pdst->dev_state[i];
+ struct device *dev = devst->dev;
+ struct platform_device *pdev = to_platform_device(dev);
+ pr_info("\t%c (%-19s %3d, %d, %10s)\n",
+ devst->active ? '+' : '-',
+ pdev->name,
+ atomic_read(&dev->power.usage_count),
+ devst->disable_depth,
+ prm_status_name[devst->runtime_status]);
+ mdelay(20);
+ }
+ }
+}
+static void dump_genpd_state(struct genpd_state *pdst, struct seq_file *s)
+{
+ static const char * const gpd_status_name[] = {
+ "ACTIVE",
+ "POWER_OFF",
+ };
+ static const char * const prm_status_name[] = {
+ "active",
+ "resuming",
+ "suspended",
+ "suspending",
+ };
+ seq_puts(s, "domain_on [pmd_name status]\n");
+ seq_puts(s, "\tdev_on (dev_name usage_count, disable, status)\n");
+ seq_puts(s, "------------------------------------------------------\n");
+ for (; pdst->pd != NULL; pdst++) {
+ int i;
+ struct generic_pm_domain *pd = pdst->pd;
+ if (IS_ERR_OR_NULL(pd)) {
+ seq_printf(s, "pd: 0x%p\n", pd);
+ continue;
+ }
+ seq_printf(s, "%c [%-9s %11s]\n",
+ (pdst->status == GPD_STATE_ACTIVE) ? '+' : '-',
+ pd->name, gpd_status_name[pdst->status]);
+ for (i = 0; i < pdst->num_dev_state; i++) {
+ struct genpd_dev_state *devst = &pdst->dev_state[i];
+ struct device *dev = devst->dev;
+ struct platform_device *pdev = to_platform_device(dev);
+ seq_printf(s, "\t%c (%-19s %3d, %d, %10s)\n",
+ devst->active ? '+' : '-',
+ pdev->name,
+ atomic_read(&dev->power.usage_count),
+ devst->disable_depth,
+ prm_status_name[devst->runtime_status]);
+ }
+ }
+}
+static void seq_print_all_genpd(struct seq_file *s)
+{
+ static struct genpd_dev_state devst[100];
+ static struct genpd_state pdst[20];
+ save_all_genpd_state(pdst, devst);
+ dump_genpd_state(pdst, s);
+}
+static int clkdbg_dump_genpd(struct seq_file *s, void *v)
+{
+ seq_print_all_genpd(s);
+ return 0;
+}
+static int clkdbg_pm_runtime_enable(struct seq_file *s, void *v)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *dev_name;
+ struct platform_device *pdev;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ dev_name = strsep(&c, " ");
+ if (dev_name == NULL)
+ return 0;
+ seq_printf(s, "pm_runtime_enable(%s): ", dev_name);
+ pdev = pdev_from_name(dev_name);
+ if (pdev != NULL) {
+ pm_runtime_enable(&pdev->dev);
+ seq_puts(s, "\n");
+ } else {
+ seq_puts(s, "NULL\n");
+ }
+ return 0;
+}
+static int clkdbg_pm_runtime_disable(struct seq_file *s, void *v)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *dev_name;
+ struct platform_device *pdev;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ dev_name = strsep(&c, " ");
+ if (dev_name == NULL)
+ return 0;
+ seq_printf(s, "pm_runtime_disable(%s): ", dev_name);
+ pdev = pdev_from_name(dev_name);
+ if (pdev != NULL) {
+ pm_runtime_disable(&pdev->dev);
+ seq_puts(s, "\n");
+ } else {
+ seq_puts(s, "NULL\n");
+ }
+ return 0;
+}
+static int clkdbg_pm_runtime_get_sync(struct seq_file *s, void *v)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *dev_name;
+ struct platform_device *pdev;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ dev_name = strsep(&c, " ");
+ if (dev_name == NULL)
+ return 0;
+ seq_printf(s, "pm_runtime_get_sync(%s): ", dev_name);
+ pdev = pdev_from_name(dev_name);
+ if (pdev != NULL) {
+ int r = pm_runtime_get_sync(&pdev->dev);
+ seq_printf(s, "%d\n", r);
+ } else {
+ seq_puts(s, "NULL\n");
+ }
+ return 0;
+}
+static int clkdbg_pm_runtime_put_sync(struct seq_file *s, void *v)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *dev_name;
+ struct platform_device *pdev;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ dev_name = strsep(&c, " ");
+ if (dev_name == NULL)
+ return 0;
+ seq_printf(s, "pm_runtime_put_sync(%s): ", dev_name);
+ pdev = pdev_from_name(dev_name);
+ if (pdev != NULL) {
+ int r = pm_runtime_put_sync(&pdev->dev);
+ seq_printf(s, "%d\n", r);
+ } else {
+ seq_puts(s, "NULL\n");
+ }
+ return 0;
+}
+static int genpd_op(const char *gpd_op_name, struct seq_file *s)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *pd_name;
+ struct generic_pm_domain *genpd;
+ int gpd_op_id;
+ int (*gpd_op)(struct generic_pm_domain *);
+ int r = 0;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ pd_name = strsep(&c, " ");
+ if (pd_name == NULL)
+ return 0;
+ if (strcmp(gpd_op_name, "power_on") == 0)
+ gpd_op_id = 1;
+ else
+ gpd_op_id = 0;
+ if (strcmp(pd_name, "all") == 0) {
+ struct generic_pm_domain **pds = get_all_genpd();
+ for (; *pds != NULL; pds++) {
+ genpd = *pds;
+ if (IS_ERR_OR_NULL(genpd))
+ continue;
+ gpd_op = (gpd_op_id == 1) ?
+ genpd->power_on : genpd->power_off;
+ r |= gpd_op(genpd);
+ }
+ seq_printf(s, "%s(%s): %d\n", gpd_op_name, pd_name, r);
+ return 0;
+ }
+ genpd = genpd_from_name(pd_name);
+ if (genpd != NULL) {
+ gpd_op = (gpd_op_id == 1) ? genpd->power_on : genpd->power_off;
+ r = gpd_op(genpd);
+ seq_printf(s, "%s(%s): %d\n", gpd_op_name, pd_name, r);
+ } else {
+ seq_printf(s, "genpd_from_name(%s): NULL\n", pd_name);
+ }
+ return 0;
+}
+static int clkdbg_pwr_on(struct seq_file *s, void *v)
+{
+ return genpd_op("power_on", s);
+}
+static int clkdbg_pwr_off(struct seq_file *s, void *v)
+{
+ return genpd_op("power_off", s);
+}
+/*
+ * clkdbg reg_pdrv/runeg_pdrv support
+ */
+static int clkdbg_probe(struct platform_device *pdev)
+{
+ int r;
+ pm_runtime_enable(&pdev->dev);
+ r = pm_runtime_get_sync(&pdev->dev);
+ if (r != 0)
+ pr_warn("%s(): pm_runtime_get_sync(%d)\n", __func__, r);
+ return r;
+}
+static int clkdbg_remove(struct platform_device *pdev)
+{
+ int r;
+ r = pm_runtime_put_sync(&pdev->dev);
+ if (r != 0)
+ pr_warn("%s(): pm_runtime_put_sync(%d)\n", __func__, r);
+ pm_runtime_disable(&pdev->dev);
+ return r;
+}
+struct pdev_drv {
+ struct platform_driver pdrv;
+ struct platform_device *pdev;
+ struct generic_pm_domain *genpd;
+};
+#define PDEV_DRV(_name) { \
+ .pdrv = { \
+ .probe = clkdbg_probe, \
+ .remove = clkdbg_remove, \
+ .driver = { \
+ .name = _name, \
+ }, \
+ }, \
+}
+static struct pdev_drv pderv[] = {
+ PDEV_DRV("clkdbg-pd0"),
+ PDEV_DRV("clkdbg-pd1"),
+ PDEV_DRV("clkdbg-pd2"),
+ PDEV_DRV("clkdbg-pd3"),
+ PDEV_DRV("clkdbg-pd4"),
+ PDEV_DRV("clkdbg-pd5"),
+ PDEV_DRV("clkdbg-pd6"),
+ PDEV_DRV("clkdbg-pd7"),
+ PDEV_DRV("clkdbg-pd8"),
+ PDEV_DRV("clkdbg-pd9"),
+ PDEV_DRV("clkdbg-pd10"),
+ PDEV_DRV("clkdbg-pd11"),
+ PDEV_DRV("clkdbg-pd12"),
+ PDEV_DRV("clkdbg-pd13"),
+ PDEV_DRV("clkdbg-pd14"),
+ PDEV_DRV("clkdbg-pd15"),
+};
+static void reg_pdev_drv(const char *pdname, struct seq_file *s)
+{
+ size_t i;
+ struct generic_pm_domain **pds = get_all_genpd();
+ bool allpd = (pdname == NULL || strcmp(pdname, "all") == 0);
+ int r;
+ for (i = 0; i < ARRAY_SIZE(pderv) && *pds != NULL; i++, pds++) {
+ const char *name = pderv[i].pdrv.driver.name;
+ struct generic_pm_domain *pd = *pds;
+ if (IS_ERR_OR_NULL(pd) || pderv[i].genpd != NULL)
+ continue;
+ if (!allpd && strcmp(pdname, pd->name) != 0)
+ continue;
+ pderv[i].genpd = pd;
+ pderv[i].pdev = platform_device_alloc(name, 0);
+ r = platform_device_add(pderv[i].pdev);
+ if (r != 0 && s != NULL)
+ seq_printf(s, "%s(): platform_device_add(%d)\n",
+ __func__, r);
+ r = pm_genpd_add_device(pd, &pderv[i].pdev->dev);
+ if (r != 0 && s != NULL)
+ seq_printf(s, "%s(): pm_genpd_add_device(%d)\n",
+ __func__, r);
+ r = platform_driver_register(&pderv[i].pdrv);
+ if (r != 0 && s != NULL)
+ seq_printf(s, "%s(): platform_driver_register(%d)\n",
+ __func__, r);
+ if (s != NULL)
+ seq_printf(s, "%s --> %s\n", name, pd->name);
+ }
+}
+static void unreg_pdev_drv(const char *pdname, struct seq_file *s)
+{
+ ssize_t i;
+ bool allpd = (pdname == NULL || strcmp(pdname, "all") == 0);
+ int r;
+ for (i = ARRAY_SIZE(pderv) - 1L; i >= 0L; i--) {
+ const char *name = pderv[i].pdrv.driver.name;
+ struct generic_pm_domain *pd = pderv[i].genpd;
+ if (IS_ERR_OR_NULL(pd))
+ continue;
+ if (!allpd && strcmp(pdname, pd->name) != 0)
+ continue;
+ r = pm_genpd_remove_device(&pderv[i].pdev->dev);
+ //r = pm_genpd_remove_device(pd, &pderv[i].pdev->dev);
+ if (r != 0 && s != NULL)
+ seq_printf(s, "%s(): pm_genpd_remove_device(%d)\n",
+ __func__, r);
+ platform_driver_unregister(&pderv[i].pdrv);
+ platform_device_unregister(pderv[i].pdev);
+ pderv[i].genpd = NULL;
+ if (s != NULL)
+ seq_printf(s, "%s -x- %s\n", name, pd->name);
+ }
+}
+static int clkdbg_reg_pdrv(struct seq_file *s, void *v)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *pd_name;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ pd_name = strsep(&c, " ");
+ if (pd_name == NULL)
+ return 0;
+ reg_pdev_drv(pd_name, s);
+ return 0;
+}
+static int clkdbg_unreg_pdrv(struct seq_file *s, void *v)
+{
+ char cmd[sizeof(last_cmd)];
+ char *c = cmd;
+ char *ign;
+ char *pd_name;
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ ign = strsep(&c, " ");
+ pd_name = strsep(&c, " ");
+ if (pd_name == NULL)
+ return 0;
+ unreg_pdev_drv(pd_name, s);
+ return 0;
+}
+#endif /* CLKDBG_PM_DOMAIN */
+void reg_pdrv(const char *pdname)
+{
+#if CLKDBG_PM_DOMAIN
+ reg_pdev_drv(pdname, NULL);
+#endif
+}
+void unreg_pdrv(const char *pdname)
+{
+#if CLKDBG_PM_DOMAIN
+ unreg_pdev_drv(pdname, NULL);
+#endif
+}
+/*
+ * Suspend / resume handler
+ */
+#include <linux/suspend.h>
+#include <linux/syscore_ops.h>
+struct provider_clk_state {
+ struct provider_clk *pvdck;
+ bool prepared;
+ bool enabled;
+ unsigned int enable_count;
+ unsigned long rate;
+ struct clk *parent;
+};
+struct save_point {
+ u32 spm_pwr_status;
+ struct provider_clk_state clks_states[512];
+#if CLKDBG_PM_DOMAIN
+ struct genpd_state genpd_states[20];
+ struct genpd_dev_state genpd_dev_states[100];
+#endif
+};
+static struct save_point save_point_1;
+static struct save_point save_point_2;
+static struct save_point save_point_3;
+static void save_pwr_status(u32 *spm_pwr_status)
+{
+ *spm_pwr_status = read_spm_pwr_status();
+}
+static void save_all_clks_state(struct provider_clk_state *clks_states,
+ u32 spm_pwr_status)
+{
+ struct provider_clk *pvdck = get_all_provider_clks();
+ struct provider_clk_state *st = clks_states;
+ for (; pvdck->ck != NULL; pvdck++, st++) {
+ struct clk *c = pvdck->ck;
+ struct clk_hw *c_hw = __clk_get_hw(c);
+ st->pvdck = pvdck;
+ st->prepared = clk_hw_is_prepared(c_hw);
+ st->enabled = clk_hw_pwr_is_on(c_hw, spm_pwr_status,
+ pvdck->pwr_mask);
+ st->enable_count = __clk_get_enable_count(c);
+ st->rate = clk_hw_get_rate(c_hw);
+ st->parent = IS_ERR_OR_NULL(c) ? NULL : clk_get_parent(c);
+ }
+}
+static void show_provider_clk_state(struct provider_clk_state *st)
+{
+ struct provider_clk *pvdck = st->pvdck;
+ struct clk_hw *c_hw = __clk_get_hw(pvdck->ck);
+ pr_info("[%10s: %-17s: %3s, %3d, %3d, %10ld, %17s]\n",
+ pvdck->provider_name != NULL ? pvdck->provider_name : "/ ",
+ clk_hw_get_name(c_hw),
+ st->enabled ? "ON" : "off",
+ st->prepared,
+ st->enable_count,
+ st->rate,
+ st->parent != NULL ?
+ clk_hw_get_name(__clk_get_hw(st->parent)) : "- ");
+ mdelay(20);
+}
+static void dump_provider_clk_state(struct provider_clk_state *st,
+ struct seq_file *s)
+{
+ struct provider_clk *pvdck = st->pvdck;
+ struct clk_hw *c_hw = __clk_get_hw(pvdck->ck);
+ seq_printf(s, "[%10s: %-17s: %3s, %3d, %3d, %10ld, %17s]\n",
+ pvdck->provider_name != NULL ? pvdck->provider_name : "/ ",
+ clk_hw_get_name(c_hw),
+ st->enabled ? "ON" : "off",
+ st->prepared,
+ st->enable_count,
+ st->rate,
+ st->parent != NULL ?
+ clk_hw_get_name(__clk_get_hw(st->parent)) : "- ");
+}
+static void show_save_point(struct save_point *sp)
+{
+ struct provider_clk_state *st = sp->clks_states;
+ for (; st->pvdck != NULL; st++)
+ show_provider_clk_state(st);
+ pr_info("\n");
+ show_pwr_status(sp->spm_pwr_status);
+#if CLKDBG_PM_DOMAIN
+ pr_info("\n");
+ show_genpd_state(sp->genpd_states);
+#endif
+}
+static void store_save_point(struct save_point *sp)
+{
+ save_pwr_status(&sp->spm_pwr_status);
+ save_all_clks_state(sp->clks_states, sp->spm_pwr_status);
+#if CLKDBG_PM_DOMAIN
+ save_all_genpd_state(sp->genpd_states, sp->genpd_dev_states);
+#endif
+ if (has_clkdbg_flag(CLKDBG_EN_LOG_SAVE_POINTS))
+ show_save_point(sp);
+}
+static void dump_save_point(struct save_point *sp, struct seq_file *s)
+{
+ struct provider_clk_state *st = sp->clks_states;
+ for (; st->pvdck != NULL; st++)
+ dump_provider_clk_state(st, s);
+ seq_puts(s, "\n");
+ dump_pwr_status(sp->spm_pwr_status, s);
+#if CLKDBG_PM_DOMAIN
+ seq_puts(s, "\n");
+ dump_genpd_state(sp->genpd_states, s);
+#endif
+}
+static int clkdbg_dump_suspend_clks_1(struct seq_file *s, void *v)
+{
+ dump_save_point(&save_point_1, s);
+ return 0;
+}
+static int clkdbg_dump_suspend_clks_2(struct seq_file *s, void *v)
+{
+ dump_save_point(&save_point_2, s);
+ return 0;
+}
+static int clkdbg_dump_suspend_clks_3(struct seq_file *s, void *v)
+{
+ dump_save_point(&save_point_3, s);
+ return 0;
+}
+static int clkdbg_dump_suspend_clks(struct seq_file *s, void *v)
+{
+ if (has_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_3) &&
+ save_point_3.spm_pwr_status != 0U)
+ return clkdbg_dump_suspend_clks_3(s, v);
+ else if (has_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_2) &&
+ save_point_2.spm_pwr_status != 0U)
+ return clkdbg_dump_suspend_clks_2(s, v);
+ else if (has_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_1) &&
+ save_point_1.spm_pwr_status != 0U)
+ return clkdbg_dump_suspend_clks_1(s, v);
+ return 0;
+}
+static int clkdbg_pm_event_handler(struct notifier_block *nb,
+ unsigned long event, void *ptr)
+{
+ switch (event) {
+ case PM_HIBERNATION_PREPARE:
+ case PM_SUSPEND_PREPARE:
+ /* suspend */
+ if (has_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_1)) {
+ store_save_point(&save_point_1);
+ return NOTIFY_OK;
+ }
+ break;
+ case PM_POST_HIBERNATION:
+ case PM_POST_SUSPEND:
+ /* resume */
+ break;
+ }
+ return NOTIFY_DONE;
+}
+static struct notifier_block clkdbg_pm_notifier = {
+ .notifier_call = clkdbg_pm_event_handler,
+};
+static int clkdbg_syscore_suspend(void)
+{
+ if (has_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_2))
+ store_save_point(&save_point_2);
+ return 0;
+}
+static void clkdbg_syscore_resume(void)
+{
+}
+static struct syscore_ops clkdbg_syscore_ops = {
+ .suspend = clkdbg_syscore_suspend,
+ .resume = clkdbg_syscore_resume,
+};
+static int __init clkdbg_pm_init(void)
+{
+ int r;
+ register_syscore_ops(&clkdbg_syscore_ops);
+ r = register_pm_notifier(&clkdbg_pm_notifier);
+ if (r != 0)
+ pr_warn("%s(): register_pm_notifier(%d)\n", __func__, r);
+ return r;
+}
+subsys_initcall(clkdbg_pm_init);
+static int clkdbg_suspend_ops_valid(suspend_state_t state)
+{
+ return state == PM_SUSPEND_MEM ? 1 : 0;
+}
+static int clkdbg_suspend_ops_begin(suspend_state_t state)
+{
+ return 0;
+}
+static int clkdbg_suspend_ops_prepare(void)
+{
+ return 0;
+}
+static int clkdbg_suspend_ops_enter(suspend_state_t state)
+{
+ if (has_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_3))
+ store_save_point(&save_point_3);
+ return 0;
+}
+static void clkdbg_suspend_ops_finish(void)
+{
+}
+static void clkdbg_suspend_ops_end(void)
+{
+}
+static const struct platform_suspend_ops clkdbg_suspend_ops = {
+ .valid = clkdbg_suspend_ops_valid,
+ .begin = clkdbg_suspend_ops_begin,
+ .prepare = clkdbg_suspend_ops_prepare,
+ .enter = clkdbg_suspend_ops_enter,
+ .finish = clkdbg_suspend_ops_finish,
+ .end = clkdbg_suspend_ops_end,
+};
+static int clkdbg_suspend_set_ops(struct seq_file *s, void *v)
+{
+ suspend_set_ops(&clkdbg_suspend_ops);
+ return 0;
+}
+static const struct cmd_fn *custom_cmds;
+void set_custom_cmds(const struct cmd_fn *cmds)
+{
+ custom_cmds = cmds;
+}
+static int clkdbg_cmds(struct seq_file *s, void *v);
+static const struct cmd_fn common_cmds[] = {
+ CMDFN("dump_regs", seq_print_regs),
+ CMDFN("dump_regs2", clkdbg_dump_regs2),
+ CMDFN("dump_state", clkdbg_dump_state_all),
+ CMDFN("dump_clks", clkdbg_dump_provider_clks),
+ CMDFN("dump_muxes", clkdbg_dump_muxes),
+ CMDFN("fmeter", seq_print_fmeter_all),
+ CMDFN("pwr_status", clkdbg_pwr_status),
+ CMDFN("prepare", clkdbg_prepare),
+ CMDFN("unprepare", clkdbg_unprepare),
+ CMDFN("enable", clkdbg_enable),
+ CMDFN("disable", clkdbg_disable),
+ CMDFN("prepare_enable", clkdbg_prepare_enable),
+ CMDFN("disable_unprepare", clkdbg_disable_unprepare),
+ CMDFN("prepare_enable_provider", clkdbg_prepare_enable_provider),
+ CMDFN("disable_unprepare_provider", clkdbg_disable_unprepare_provider),
+ CMDFN("set_parent", clkdbg_set_parent),
+ CMDFN("set_rate", clkdbg_set_rate),
+ CMDFN("reg_read", clkdbg_reg_read),
+ CMDFN("reg_write", clkdbg_reg_write),
+ CMDFN("reg_set", clkdbg_reg_set),
+ CMDFN("reg_clr", clkdbg_reg_clr),
+ CMDFN("show_flags", clkdbg_show_flags),
+ CMDFN("set_flag", clkdbg_set_flag),
+ CMDFN("clr_flag", clkdbg_clr_flag),
+#if CLKDBG_PM_DOMAIN
+ CMDFN("dump_genpd", clkdbg_dump_genpd),
+ CMDFN("pm_runtime_enable", clkdbg_pm_runtime_enable),
+ CMDFN("pm_runtime_disable", clkdbg_pm_runtime_disable),
+ CMDFN("pm_runtime_get_sync", clkdbg_pm_runtime_get_sync),
+ CMDFN("pm_runtime_put_sync", clkdbg_pm_runtime_put_sync),
+ CMDFN("pwr_on", clkdbg_pwr_on),
+ CMDFN("pwr_off", clkdbg_pwr_off),
+ CMDFN("reg_pdrv", clkdbg_reg_pdrv),
+ CMDFN("unreg_pdrv", clkdbg_unreg_pdrv),
+#endif /* CLKDBG_PM_DOMAIN */
+ CMDFN("suspend_set_ops", clkdbg_suspend_set_ops),
+ CMDFN("dump_suspend_clks", clkdbg_dump_suspend_clks),
+ CMDFN("dump_suspend_clks_1", clkdbg_dump_suspend_clks_1),
+ CMDFN("dump_suspend_clks_2", clkdbg_dump_suspend_clks_2),
+ CMDFN("dump_suspend_clks_3", clkdbg_dump_suspend_clks_3),
+ CMDFN("cmds", clkdbg_cmds),
+ {}
+};
+static int clkdbg_cmds(struct seq_file *s, void *v)
+{
+ const struct cmd_fn *cf;
+ for (cf = common_cmds; cf->cmd != NULL; cf++)
+ seq_printf(s, "%s\n", cf->cmd);
+ for (cf = custom_cmds; cf != NULL && cf->cmd != NULL; cf++)
+ seq_printf(s, "%s\n", cf->cmd);
+ seq_puts(s, "\n");
+ return 0;
+}
+static int clkdbg_show(struct seq_file *s, void *v)
+{
+ const struct cmd_fn *cf;
+ char cmd[sizeof(last_cmd)];
+ strncpy(cmd, last_cmd, sizeof(cmd));
+ cmd[sizeof(cmd) - 1UL] = '\0';
+ for (cf = custom_cmds; cf != NULL && cf->cmd != NULL; cf++) {
+ char *c = cmd;
+ char *token = strsep(&c, " ");
+ if (strcmp(cf->cmd, token) == 0)
+ return cf->fn(s, v);
+ }
+ for (cf = common_cmds; cf->cmd != NULL; cf++) {
+ char *c = cmd;
+ char *token = strsep(&c, " ");
+ if (strcmp(cf->cmd, token) == 0)
+ return cf->fn(s, v);
+ }
+ return 0;
+}
+static int clkdbg_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, clkdbg_show, NULL);
+}
+static ssize_t clkdbg_write(
+ struct file *file,
+ const char __user *buffer,
+ size_t count,
+ loff_t *data)
+{
+ size_t len = 0;
+ char *nl;
+ len = (count < (sizeof(last_cmd) - 1UL)) ?
+ count : (sizeof(last_cmd) - 1UL);
+ if (copy_from_user(last_cmd, buffer, len) != 0UL)
+ return 0;
+ last_cmd[len] = '\0';
+ nl = strchr(last_cmd, '\n');
+ if (nl != NULL)
+ *nl = '\0';
+ return (ssize_t)len;
+}
+static const struct file_operations clkdbg_fops = {
+ .owner = THIS_MODULE,
+ .open = clkdbg_open,
+ .read = seq_read,
+ .write = clkdbg_write,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+/*
+ * init functions
+ */
+static int __init clkdbg_debug_init(void)
+{
+ struct proc_dir_entry *entry;
+ entry = proc_create("clkdbg", 0644, NULL, &clkdbg_fops);
+ if (entry == 0)
+ return -ENOMEM;
+ set_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_3);
+ return 0;
+}
+module_init(clkdbg_debug_init);
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg.h b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg.h
new file mode 100644
index 0000000..01e5872
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/clkdbg.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+struct seq_file;
+#define clk_readl(addr) readl(addr)
+#define clk_writel(addr, val) \
+ do { writel(val, addr); wmb(); } while (0) /* sync write */
+#define clk_setl(addr, val) clk_writel(addr, clk_readl(addr) | (val))
+#define clk_clrl(addr, val) clk_writel(addr, clk_readl(addr) & ~(val))
+enum FMETER_TYPE {
+ FT_NULL,
+ ABIST,
+ CKGEN,
+ ABIST_2,
+};
+struct fmeter_clk {
+ enum FMETER_TYPE type;
+ u32 id;
+ const char *name;
+ u32 ofs;
+ u32 pdn;
+};
+struct regbase {
+ u32 phys;
+ void __iomem *virt;
+ const char *name;
+ const char *pg;
+};
+struct regname {
+ struct regbase *base;
+ u32 ofs;
+ const char *name;
+};
+#define ADDR(rn) (rn->base->virt + rn->ofs)
+#define PHYSADDR(rn) (rn->base->phys + rn->ofs)
+struct cmd_fn {
+ const char *cmd;
+ int (*fn)(struct seq_file *s, void *v);
+};
+#define CMDFN(_cmd, _fn) { \
+ .cmd = _cmd, \
+ .fn = _fn, \
+}
+struct provider_clk {
+ const char *provider_name;
+ u32 idx;
+ struct clk *ck;
+ u32 pwr_mask;
+};
+struct clkdbg_ops {
+ const struct fmeter_clk *(*get_all_fmeter_clks)(void);
+ void *(*prepare_fmeter)(void);
+ void (*unprepare_fmeter)(void *data);
+ u32 (*fmeter_freq)(const struct fmeter_clk *fclk);
+ const struct regname *(*get_all_regnames)(void);
+ const char * const *(*get_all_clk_names)(void);
+ const char * const *(*get_pwr_names)(void);
+ void (*setup_provider_clk)(struct provider_clk *pvdck);
+ u32 (*get_spm_pwr_status)(void);
+ bool (*is_pwr_on)(struct provider_clk *pvdck);
+};
+void set_clkdbg_ops(const struct clkdbg_ops *ops);
+void set_custom_cmds(const struct cmd_fn *cmds);
+struct provider_clk *get_all_provider_clks(void);
+const char *get_last_cmd(void);
+void reg_pdrv(const char *pdname);
+void unreg_pdrv(const char *pdname);
+void prepare_enable_provider(const char *pvd);
+void disable_unprepare_provider(const char *pvd);
+void print_regs(void);
+void print_fmeter_all(void);
\ No newline at end of file
diff --git a/src/kernel/linux/v4.19/drivers/clk/mediatek/reset.c b/src/kernel/linux/v4.19/drivers/clk/mediatek/reset.c
new file mode 100644
index 0000000..d3551d5
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/clk/mediatek/reset.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+
+#include "clk-mtk.h"
+
+struct mtk_reset {
+ struct regmap *regmap;
+ int regofs;
+ struct reset_controller_dev rcdev;
+};
+
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+
+ return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
+ BIT(id % 32), ~0);
+}
+
+static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+
+ return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
+ BIT(id % 32), 0);
+}
+
+static int mtk_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ int ret;
+
+ ret = mtk_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ return mtk_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops mtk_reset_ops = {
+ .assert = mtk_reset_assert,
+ .deassert = mtk_reset_deassert,
+ .reset = mtk_reset,
+};
+
+void mtk_register_reset_controller(struct device_node *np,
+ unsigned int num_regs, int regofs)
+{
+ struct mtk_reset *data;
+ int ret;
+ struct regmap *regmap;
+
+ regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(regmap)) {
+ pr_err("Cannot find regmap for %pOF: %ld\n", np,
+ PTR_ERR(regmap));
+ return;
+ }
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return;
+
+ data->regmap = regmap;
+ data->regofs = regofs;
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.nr_resets = num_regs * 32;
+ data->rcdev.ops = &mtk_reset_ops;
+ data->rcdev.of_node = np;
+
+ ret = reset_controller_register(&data->rcdev);
+ if (ret) {
+ pr_err("could not register reset controller: %d\n", ret);
+ kfree(data);
+ return;
+ }
+}