[Feature] add GA346 baseline version
Change-Id: Ic62933698569507dcf98240cdf5d9931ae34348f
diff --git a/src/kernel/linux/v4.19/drivers/spmi/Kconfig b/src/kernel/linux/v4.19/drivers/spmi/Kconfig
new file mode 100644
index 0000000..e10314e
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/spmi/Kconfig
@@ -0,0 +1,36 @@
+#
+# SPMI driver configuration
+#
+menuconfig SPMI
+ tristate "SPMI support"
+ help
+ SPMI (System Power Management Interface) is a two-wire
+ serial interface between baseband and application processors
+ and Power Management Integrated Circuits (PMIC).
+
+if SPMI
+
+config SPMI_MSM_PMIC_ARB
+ tristate "Qualcomm MSM SPMI Controller (PMIC Arbiter)"
+ select IRQ_DOMAIN
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on HAS_IOMEM
+ default ARCH_QCOM
+ help
+ If you say yes to this option, support will be included for the
+ built-in SPMI PMIC Arbiter interface on Qualcomm MSM family
+ processors.
+
+ This is required for communicating with Qualcomm PMICs and
+ other devices that have the SPMI interface.
+
+config MTK_PMIF
+ tristate "Mediatek SPMI Controller (PMIC Arbiter)"
+ help
+ If you say yes to this option, support will be included for the
+ built-in SPMI PMIC Arbiter interface on Mediatek family
+ processors.
+
+ This is required for communicating with Mediatek PMICs and
+ other devices that have the SPMI interface.
+endif
diff --git a/src/kernel/linux/v4.19/drivers/spmi/Makefile b/src/kernel/linux/v4.19/drivers/spmi/Makefile
new file mode 100644
index 0000000..da9892e
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/spmi/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for kernel SPMI framework.
+#
+ccflags-y += -I$(srctree)/drivers/misc/mediatek/include/
+obj-$(CONFIG_SPMI) += spmi.o
+
+obj-$(CONFIG_SPMI_MSM_PMIC_ARB) += spmi-pmic-arb.o
+obj-$(CONFIG_MTK_PMIF) += mtk-pmif.o mtk-dbg.o
diff --git a/src/kernel/linux/v4.19/drivers/spmi/mtk-dbg.c b/src/kernel/linux/v4.19/drivers/spmi/mtk-dbg.c
new file mode 100644
index 0000000..44201bd
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/spmi/mtk-dbg.c
@@ -0,0 +1,1676 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Argus Lin <argus.lin@mediatek.com>
+ */
+#define DEBUG
+
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/sched/clock.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
+#include <linux/debugfs.h>
+#include "spmi_sw.h"
+
+enum pmif_dbg_regs {
+ PMIF_INIT_DONE,
+ PMIF_INF_BUSY_STA,
+ PMIF_OTHER_BUSY_STA_0,
+ PMIF_OTHER_BUSY_STA_1,
+ PMIF_IRQ_EVENT_EN_0,
+ PMIF_IRQ_FLAG_0,
+ PMIF_IRQ_CLR_0,
+ PMIF_IRQ_EVENT_EN_1,
+ PMIF_IRQ_FLAG_1,
+ PMIF_IRQ_CLR_1,
+ PMIF_IRQ_EVENT_EN_2,
+ PMIF_IRQ_FLAG_2,
+ PMIF_IRQ_CLR_2,
+ PMIF_IRQ_EVENT_EN_3,
+ PMIF_IRQ_FLAG_3,
+ PMIF_IRQ_CLR_3,
+ PMIF_IRQ_EVENT_EN_4,
+ PMIF_IRQ_FLAG_4,
+ PMIF_IRQ_CLR_4,
+ PMIF_WDT_EVENT_EN_0,
+ PMIF_WDT_FLAG_0,
+ PMIF_WDT_EVENT_EN_1,
+ PMIF_WDT_FLAG_1,
+ PMIF_MONITOR_CTRL,
+ PMIF_MONITOR_TARGET_CHAN_0,
+ PMIF_MONITOR_TARGET_CHAN_1,
+ PMIF_MONITOR_TARGET_CHAN_2,
+ PMIF_MONITOR_TARGET_CHAN_3,
+ PMIF_MONITOR_TARGET_CHAN_4,
+ PMIF_MONITOR_TARGET_CHAN_5,
+ PMIF_MONITOR_TARGET_CHAN_6,
+ PMIF_MONITOR_TARGET_CHAN_7,
+ PMIF_MONITOR_TARGET_WRITE,
+ PMIF_MONITOR_TARGET_SLVID_0,
+ PMIF_MONITOR_TARGET_SLVID_1,
+ PMIF_MONITOR_TARGET_ADDR_0,
+ PMIF_MONITOR_TARGET_ADDR_1,
+ PMIF_MONITOR_TARGET_ADDR_2,
+ PMIF_MONITOR_TARGET_ADDR_3,
+ PMIF_MONITOR_TARGET_ADDR_4,
+ PMIF_MONITOR_TARGET_ADDR_5,
+ PMIF_MONITOR_TARGET_ADDR_6,
+ PMIF_MONITOR_TARGET_ADDR_7,
+ PMIF_MONITOR_TARGET_WDATA_0,
+ PMIF_MONITOR_TARGET_WDATA_1,
+ PMIF_MONITOR_TARGET_WDATA_2,
+ PMIF_MONITOR_TARGET_WDATA_3,
+ PMIF_MONITOR_TARGET_WDATA_4,
+ PMIF_MONITOR_TARGET_WDATA_5,
+ PMIF_MONITOR_TARGET_WDATA_6,
+ PMIF_MONITOR_TARGET_WDATA_7,
+ PMIF_MONITOR_STA,
+ PMIF_MONITOR_RECORD_0_0,
+ PMIF_MONITOR_RECORD_0_1,
+ PMIF_MONITOR_RECORD_0_2,
+ PMIF_MONITOR_RECORD_0_3,
+ PMIF_MONITOR_RECORD_0_4,
+ PMIF_MONITOR_RECORD_1_0,
+ PMIF_MONITOR_RECORD_1_1,
+ PMIF_MONITOR_RECORD_1_2,
+ PMIF_MONITOR_RECORD_1_3,
+ PMIF_MONITOR_RECORD_1_4,
+ PMIF_MONITOR_RECORD_2_0,
+ PMIF_MONITOR_RECORD_2_1,
+ PMIF_MONITOR_RECORD_2_2,
+ PMIF_MONITOR_RECORD_2_3,
+ PMIF_MONITOR_RECORD_2_4,
+ PMIF_MONITOR_RECORD_3_0,
+ PMIF_MONITOR_RECORD_3_1,
+ PMIF_MONITOR_RECORD_3_2,
+ PMIF_MONITOR_RECORD_3_3,
+ PMIF_MONITOR_RECORD_3_4,
+ PMIF_MONITOR_RECORD_4_0,
+ PMIF_MONITOR_RECORD_4_1,
+ PMIF_MONITOR_RECORD_4_2,
+ PMIF_MONITOR_RECORD_4_3,
+ PMIF_MONITOR_RECORD_4_4,
+ PMIF_MONITOR_RECORD_5_0,
+ PMIF_MONITOR_RECORD_5_1,
+ PMIF_MONITOR_RECORD_5_2,
+ PMIF_MONITOR_RECORD_5_3,
+ PMIF_MONITOR_RECORD_5_4,
+ PMIF_MONITOR_RECORD_6_0,
+ PMIF_MONITOR_RECORD_6_1,
+ PMIF_MONITOR_RECORD_6_2,
+ PMIF_MONITOR_RECORD_6_3,
+ PMIF_MONITOR_RECORD_6_4,
+ PMIF_MONITOR_RECORD_7_0,
+ PMIF_MONITOR_RECORD_7_1,
+ PMIF_MONITOR_RECORD_7_2,
+ PMIF_MONITOR_RECORD_7_3,
+ PMIF_MONITOR_RECORD_7_4,
+ PMIF_MONITOR_RECORD_8_0,
+ PMIF_MONITOR_RECORD_8_1,
+ PMIF_MONITOR_RECORD_8_2,
+ PMIF_MONITOR_RECORD_8_3,
+ PMIF_MONITOR_RECORD_8_4,
+ PMIF_MONITOR_RECORD_9_0,
+ PMIF_MONITOR_RECORD_9_1,
+ PMIF_MONITOR_RECORD_9_2,
+ PMIF_MONITOR_RECORD_9_3,
+ PMIF_MONITOR_RECORD_9_4,
+ PMIF_MONITOR_RECORD_10_0,
+ PMIF_MONITOR_RECORD_10_1,
+ PMIF_MONITOR_RECORD_10_2,
+ PMIF_MONITOR_RECORD_10_3,
+ PMIF_MONITOR_RECORD_10_4,
+ PMIF_MONITOR_RECORD_11_0,
+ PMIF_MONITOR_RECORD_11_1,
+ PMIF_MONITOR_RECORD_11_2,
+ PMIF_MONITOR_RECORD_11_3,
+ PMIF_MONITOR_RECORD_11_4,
+ PMIF_MONITOR_RECORD_12_0,
+ PMIF_MONITOR_RECORD_12_1,
+ PMIF_MONITOR_RECORD_12_2,
+ PMIF_MONITOR_RECORD_12_3,
+ PMIF_MONITOR_RECORD_12_4,
+ PMIF_MONITOR_RECORD_13_0,
+ PMIF_MONITOR_RECORD_13_1,
+ PMIF_MONITOR_RECORD_13_2,
+ PMIF_MONITOR_RECORD_13_3,
+ PMIF_MONITOR_RECORD_13_4,
+ PMIF_MONITOR_RECORD_14_0,
+ PMIF_MONITOR_RECORD_14_1,
+ PMIF_MONITOR_RECORD_14_2,
+ PMIF_MONITOR_RECORD_14_3,
+ PMIF_MONITOR_RECORD_14_4,
+ PMIF_MONITOR_RECORD_15_0,
+ PMIF_MONITOR_RECORD_15_1,
+ PMIF_MONITOR_RECORD_15_2,
+ PMIF_MONITOR_RECORD_15_3,
+ PMIF_MONITOR_RECORD_15_4,
+ PMIF_MONITOR_RECORD_16_0,
+ PMIF_MONITOR_RECORD_16_1,
+ PMIF_MONITOR_RECORD_16_2,
+ PMIF_MONITOR_RECORD_16_3,
+ PMIF_MONITOR_RECORD_16_4,
+ PMIF_MONITOR_RECORD_17_0,
+ PMIF_MONITOR_RECORD_17_1,
+ PMIF_MONITOR_RECORD_17_2,
+ PMIF_MONITOR_RECORD_17_3,
+ PMIF_MONITOR_RECORD_17_4,
+ PMIF_MONITOR_RECORD_18_0,
+ PMIF_MONITOR_RECORD_18_1,
+ PMIF_MONITOR_RECORD_18_2,
+ PMIF_MONITOR_RECORD_18_3,
+ PMIF_MONITOR_RECORD_18_4,
+ PMIF_MONITOR_RECORD_19_0,
+ PMIF_MONITOR_RECORD_19_1,
+ PMIF_MONITOR_RECORD_19_2,
+ PMIF_MONITOR_RECORD_19_3,
+ PMIF_MONITOR_RECORD_19_4,
+ PMIF_MONITOR_RECORD_20_0,
+ PMIF_MONITOR_RECORD_20_1,
+ PMIF_MONITOR_RECORD_20_2,
+ PMIF_MONITOR_RECORD_20_3,
+ PMIF_MONITOR_RECORD_20_4,
+ PMIF_MONITOR_RECORD_21_0,
+ PMIF_MONITOR_RECORD_21_1,
+ PMIF_MONITOR_RECORD_21_2,
+ PMIF_MONITOR_RECORD_21_3,
+ PMIF_MONITOR_RECORD_21_4,
+ PMIF_MONITOR_RECORD_22_0,
+ PMIF_MONITOR_RECORD_22_1,
+ PMIF_MONITOR_RECORD_22_2,
+ PMIF_MONITOR_RECORD_22_3,
+ PMIF_MONITOR_RECORD_22_4,
+ PMIF_MONITOR_RECORD_23_0,
+ PMIF_MONITOR_RECORD_23_1,
+ PMIF_MONITOR_RECORD_23_2,
+ PMIF_MONITOR_RECORD_23_3,
+ PMIF_MONITOR_RECORD_23_4,
+ PMIF_MONITOR_RECORD_24_0,
+ PMIF_MONITOR_RECORD_24_1,
+ PMIF_MONITOR_RECORD_24_2,
+ PMIF_MONITOR_RECORD_24_3,
+ PMIF_MONITOR_RECORD_24_4,
+ PMIF_MONITOR_RECORD_25_0,
+ PMIF_MONITOR_RECORD_25_1,
+ PMIF_MONITOR_RECORD_25_2,
+ PMIF_MONITOR_RECORD_25_3,
+ PMIF_MONITOR_RECORD_25_4,
+ PMIF_MONITOR_RECORD_26_0,
+ PMIF_MONITOR_RECORD_26_1,
+ PMIF_MONITOR_RECORD_26_2,
+ PMIF_MONITOR_RECORD_26_3,
+ PMIF_MONITOR_RECORD_26_4,
+ PMIF_MONITOR_RECORD_27_0,
+ PMIF_MONITOR_RECORD_27_1,
+ PMIF_MONITOR_RECORD_27_2,
+ PMIF_MONITOR_RECORD_27_3,
+ PMIF_MONITOR_RECORD_27_4,
+ PMIF_MONITOR_RECORD_28_0,
+ PMIF_MONITOR_RECORD_28_1,
+ PMIF_MONITOR_RECORD_28_2,
+ PMIF_MONITOR_RECORD_28_3,
+ PMIF_MONITOR_RECORD_28_4,
+ PMIF_MONITOR_RECORD_29_0,
+ PMIF_MONITOR_RECORD_29_1,
+ PMIF_MONITOR_RECORD_29_2,
+ PMIF_MONITOR_RECORD_29_3,
+ PMIF_MONITOR_RECORD_29_4,
+ PMIF_MONITOR_RECORD_30_0,
+ PMIF_MONITOR_RECORD_30_1,
+ PMIF_MONITOR_RECORD_30_2,
+ PMIF_MONITOR_RECORD_30_3,
+ PMIF_MONITOR_RECORD_30_4,
+ PMIF_MONITOR_RECORD_31_0,
+ PMIF_MONITOR_RECORD_31_1,
+ PMIF_MONITOR_RECORD_31_2,
+ PMIF_MONITOR_RECORD_31_3,
+ PMIF_MONITOR_RECORD_31_4,
+ PMIF_DEBUG_CTRL,
+ PMIF_RESERVED_0,
+ PMIF_SWINF_0_ACC,
+ PMIF_SWINF_0_WDATA_31_0,
+ PMIF_SWINF_0_WDATA_63_32,
+ PMIF_SWINF_0_RDATA_31_0,
+ PMIF_SWINF_0_RDATA_63_32,
+ PMIF_SWINF_0_VLD_CLR,
+ PMIF_SWINF_0_STA,
+ PMIF_SWINF_1_ACC,
+ PMIF_SWINF_1_WDATA_31_0,
+ PMIF_SWINF_1_WDATA_63_32,
+ PMIF_SWINF_1_RDATA_31_0,
+ PMIF_SWINF_1_RDATA_63_32,
+ PMIF_SWINF_1_VLD_CLR,
+ PMIF_SWINF_1_STA,
+ PMIF_SWINF_2_ACC,
+ PMIF_SWINF_2_WDATA_31_0,
+ PMIF_SWINF_2_WDATA_63_32,
+ PMIF_SWINF_2_RDATA_31_0,
+ PMIF_SWINF_2_RDATA_63_32,
+ PMIF_SWINF_2_VLD_CLR,
+ PMIF_SWINF_2_STA,
+ PMIF_SWINF_3_ACC,
+ PMIF_SWINF_3_WDATA_31_0,
+ PMIF_SWINF_3_WDATA_63_32,
+ PMIF_SWINF_3_RDATA_31_0,
+ PMIF_SWINF_3_RDATA_63_32,
+ PMIF_SWINF_3_VLD_CLR,
+ PMIF_SWINF_3_STA,
+
+ PMIC_ACC_VIO_INFO_0,
+ PMIC_ACC_VIO_INFO_1,
+ PMIC_ACC_VIO_INFO_2,
+ PMIC_ACC_VIO_INFO_3,
+ PMIC_ACC_VIO_INFO_4,
+ PMIC_ACC_VIO_INFO_5,
+ PMIC_ACC_SCP_VIO_INFO_0,
+ PMIC_ACC_SCP_VIO_INFO_1,
+ PMIC_ACC_SCP_VIO_INFO_2,
+ PMIC_ACC_SCP_VIO_INFO_3,
+ PMIC_ACC_SCP_VIO_INFO_4,
+ PMIC_ACC_SCP_VIO_INFO_5,
+ PMIF_ACC_VIO_INFO_0,
+ PMIF_ACC_VIO_INFO_1,
+ PMIF_ACC_VIO_INFO_2,
+ /* MT6853/MT6880 new register */
+ PMIC_ALL_ACC_VIO_INFO_0,
+ PMIC_ALL_ACC_VIO_INFO_1,
+};
+
+static const u32 mt6880_pmif_dbg_regs[] = {
+ [PMIF_INIT_DONE] = 0x0000,
+ [PMIF_INF_BUSY_STA] = 0x0018,
+ [PMIF_OTHER_BUSY_STA_0] = 0x001C,
+ [PMIF_OTHER_BUSY_STA_1] = 0x0020,
+ [PMIF_IRQ_EVENT_EN_0] = 0x0420,
+ [PMIF_IRQ_FLAG_0] = 0x0428,
+ [PMIF_IRQ_CLR_0] = 0x042C,
+ [PMIF_IRQ_EVENT_EN_1] = 0x0430,
+ [PMIF_IRQ_FLAG_1] = 0x0438,
+ [PMIF_IRQ_CLR_1] = 0x043C,
+ [PMIF_IRQ_EVENT_EN_2] = 0x0440,
+ [PMIF_IRQ_FLAG_2] = 0x0448,
+ [PMIF_IRQ_CLR_2] = 0x044C,
+ [PMIF_IRQ_EVENT_EN_3] = 0x0450,
+ [PMIF_IRQ_FLAG_3] = 0x0458,
+ [PMIF_IRQ_CLR_3] = 0x045C,
+ [PMIF_IRQ_EVENT_EN_4] = 0x0460,
+ [PMIF_IRQ_FLAG_4] = 0x0468,
+ [PMIF_IRQ_CLR_4] = 0x046C,
+ [PMIF_WDT_EVENT_EN_0] = 0x0474,
+ [PMIF_WDT_FLAG_0] = 0x0478,
+ [PMIF_WDT_EVENT_EN_1] = 0x047C,
+ [PMIF_WDT_FLAG_1] = 0x0480,
+ [PMIF_MONITOR_CTRL] = 0x0484,
+ [PMIF_MONITOR_TARGET_CHAN_0] = 0x0488,
+ [PMIF_MONITOR_TARGET_CHAN_1] = 0x048C,
+ [PMIF_MONITOR_TARGET_CHAN_2] = 0x0490,
+ [PMIF_MONITOR_TARGET_CHAN_3] = 0x0494,
+ [PMIF_MONITOR_TARGET_CHAN_4] = 0x0498,
+ [PMIF_MONITOR_TARGET_CHAN_5] = 0x049C,
+ [PMIF_MONITOR_TARGET_CHAN_6] = 0x04A0,
+ [PMIF_MONITOR_TARGET_CHAN_7] = 0x04A4,
+ [PMIF_MONITOR_TARGET_WRITE] = 0x04A8,
+ [PMIF_MONITOR_TARGET_SLVID_0] = 0x04AC,
+ [PMIF_MONITOR_TARGET_SLVID_1] = 0x04B0,
+ [PMIF_MONITOR_TARGET_ADDR_0] = 0x04B4,
+ [PMIF_MONITOR_TARGET_ADDR_1] = 0x04B8,
+ [PMIF_MONITOR_TARGET_ADDR_2] = 0x04BC,
+ [PMIF_MONITOR_TARGET_ADDR_3] = 0x04C0,
+ [PMIF_MONITOR_TARGET_ADDR_4] = 0x04C4,
+ [PMIF_MONITOR_TARGET_ADDR_5] = 0x04C8,
+ [PMIF_MONITOR_TARGET_ADDR_6] = 0x04CC,
+ [PMIF_MONITOR_TARGET_ADDR_7] = 0x04D0,
+ [PMIF_MONITOR_TARGET_WDATA_0] = 0x04D4,
+ [PMIF_MONITOR_TARGET_WDATA_1] = 0x04D8,
+ [PMIF_MONITOR_TARGET_WDATA_2] = 0x04DC,
+ [PMIF_MONITOR_TARGET_WDATA_3] = 0x04E0,
+ [PMIF_MONITOR_TARGET_WDATA_4] = 0x04E4,
+ [PMIF_MONITOR_TARGET_WDATA_5] = 0x04E8,
+ [PMIF_MONITOR_TARGET_WDATA_6] = 0x04EC,
+ [PMIF_MONITOR_TARGET_WDATA_7] = 0x04F0,
+ [PMIF_MONITOR_STA] = 0x04F4,
+ [PMIF_MONITOR_RECORD_0_0] = 0x04F8,
+ [PMIF_MONITOR_RECORD_0_1] = 0x04FC,
+ [PMIF_MONITOR_RECORD_0_2] = 0x0500,
+ [PMIF_MONITOR_RECORD_0_3] = 0x0504,
+ [PMIF_MONITOR_RECORD_0_4] = 0x0508,
+ [PMIF_MONITOR_RECORD_1_0] = 0x050C,
+ [PMIF_MONITOR_RECORD_1_1] = 0x0510,
+ [PMIF_MONITOR_RECORD_1_2] = 0x0514,
+ [PMIF_MONITOR_RECORD_1_3] = 0x0518,
+ [PMIF_MONITOR_RECORD_1_4] = 0x051C,
+ [PMIF_MONITOR_RECORD_2_0] = 0x0520,
+ [PMIF_MONITOR_RECORD_2_1] = 0x0524,
+ [PMIF_MONITOR_RECORD_2_2] = 0x0528,
+ [PMIF_MONITOR_RECORD_2_3] = 0x052C,
+ [PMIF_MONITOR_RECORD_2_4] = 0x0530,
+ [PMIF_MONITOR_RECORD_3_0] = 0x0534,
+ [PMIF_MONITOR_RECORD_3_1] = 0x0538,
+ [PMIF_MONITOR_RECORD_3_2] = 0x053C,
+ [PMIF_MONITOR_RECORD_3_3] = 0x0540,
+ [PMIF_MONITOR_RECORD_3_4] = 0x0544,
+ [PMIF_MONITOR_RECORD_4_0] = 0x0548,
+ [PMIF_MONITOR_RECORD_4_1] = 0x054C,
+ [PMIF_MONITOR_RECORD_4_2] = 0x0550,
+ [PMIF_MONITOR_RECORD_4_3] = 0x0554,
+ [PMIF_MONITOR_RECORD_4_4] = 0x0558,
+ [PMIF_MONITOR_RECORD_5_0] = 0x055C,
+ [PMIF_MONITOR_RECORD_5_1] = 0x0560,
+ [PMIF_MONITOR_RECORD_5_2] = 0x0564,
+ [PMIF_MONITOR_RECORD_5_3] = 0x0568,
+ [PMIF_MONITOR_RECORD_5_4] = 0x056C,
+ [PMIF_MONITOR_RECORD_6_0] = 0x0570,
+ [PMIF_MONITOR_RECORD_6_1] = 0x0574,
+ [PMIF_MONITOR_RECORD_6_2] = 0x0578,
+ [PMIF_MONITOR_RECORD_6_3] = 0x057C,
+ [PMIF_MONITOR_RECORD_6_4] = 0x0580,
+ [PMIF_MONITOR_RECORD_7_0] = 0x0584,
+ [PMIF_MONITOR_RECORD_7_1] = 0x0588,
+ [PMIF_MONITOR_RECORD_7_2] = 0x058C,
+ [PMIF_MONITOR_RECORD_7_3] = 0x0590,
+ [PMIF_MONITOR_RECORD_7_4] = 0x0594,
+ [PMIF_MONITOR_RECORD_8_0] = 0x0598,
+ [PMIF_MONITOR_RECORD_8_1] = 0x059C,
+ [PMIF_MONITOR_RECORD_8_2] = 0x05A0,
+ [PMIF_MONITOR_RECORD_8_3] = 0x05A4,
+ [PMIF_MONITOR_RECORD_8_4] = 0x05A8,
+ [PMIF_MONITOR_RECORD_9_0] = 0x05AC,
+ [PMIF_MONITOR_RECORD_9_1] = 0x05B0,
+ [PMIF_MONITOR_RECORD_9_2] = 0x05B4,
+ [PMIF_MONITOR_RECORD_9_3] = 0x05B8,
+ [PMIF_MONITOR_RECORD_9_4] = 0x05BC,
+ [PMIF_MONITOR_RECORD_10_0] = 0x05C0,
+ [PMIF_MONITOR_RECORD_10_1] = 0x05C4,
+ [PMIF_MONITOR_RECORD_10_2] = 0x05C8,
+ [PMIF_MONITOR_RECORD_10_3] = 0x05CC,
+ [PMIF_MONITOR_RECORD_10_4] = 0x05D0,
+ [PMIF_MONITOR_RECORD_11_0] = 0x05D4,
+ [PMIF_MONITOR_RECORD_11_1] = 0x05D8,
+ [PMIF_MONITOR_RECORD_11_2] = 0x05DC,
+ [PMIF_MONITOR_RECORD_11_3] = 0x05E0,
+ [PMIF_MONITOR_RECORD_11_4] = 0x05E4,
+ [PMIF_MONITOR_RECORD_12_0] = 0x05E8,
+ [PMIF_MONITOR_RECORD_12_1] = 0x05EC,
+ [PMIF_MONITOR_RECORD_12_2] = 0x05F0,
+ [PMIF_MONITOR_RECORD_12_3] = 0x05F4,
+ [PMIF_MONITOR_RECORD_12_4] = 0x05F8,
+ [PMIF_MONITOR_RECORD_13_0] = 0x05FC,
+ [PMIF_MONITOR_RECORD_13_1] = 0x0600,
+ [PMIF_MONITOR_RECORD_13_2] = 0x0604,
+ [PMIF_MONITOR_RECORD_13_3] = 0x0608,
+ [PMIF_MONITOR_RECORD_13_4] = 0x060C,
+ [PMIF_MONITOR_RECORD_14_0] = 0x0610,
+ [PMIF_MONITOR_RECORD_14_1] = 0x0614,
+ [PMIF_MONITOR_RECORD_14_2] = 0x0618,
+ [PMIF_MONITOR_RECORD_14_3] = 0x061C,
+ [PMIF_MONITOR_RECORD_14_4] = 0x0620,
+ [PMIF_MONITOR_RECORD_15_0] = 0x0624,
+ [PMIF_MONITOR_RECORD_15_1] = 0x0628,
+ [PMIF_MONITOR_RECORD_15_2] = 0x062C,
+ [PMIF_MONITOR_RECORD_15_3] = 0x0630,
+ [PMIF_MONITOR_RECORD_15_4] = 0x0634,
+ [PMIF_MONITOR_RECORD_16_0] = 0x0638,
+ [PMIF_MONITOR_RECORD_16_1] = 0x063C,
+ [PMIF_MONITOR_RECORD_16_2] = 0x0640,
+ [PMIF_MONITOR_RECORD_16_3] = 0x0644,
+ [PMIF_MONITOR_RECORD_16_4] = 0x0648,
+ [PMIF_MONITOR_RECORD_17_0] = 0x064C,
+ [PMIF_MONITOR_RECORD_17_1] = 0x0650,
+ [PMIF_MONITOR_RECORD_17_2] = 0x0654,
+ [PMIF_MONITOR_RECORD_17_3] = 0x0658,
+ [PMIF_MONITOR_RECORD_17_4] = 0x065C,
+ [PMIF_MONITOR_RECORD_18_0] = 0x0660,
+ [PMIF_MONITOR_RECORD_18_1] = 0x0664,
+ [PMIF_MONITOR_RECORD_18_2] = 0x0668,
+ [PMIF_MONITOR_RECORD_18_3] = 0x066C,
+ [PMIF_MONITOR_RECORD_18_4] = 0x0670,
+ [PMIF_MONITOR_RECORD_19_0] = 0x0674,
+ [PMIF_MONITOR_RECORD_19_1] = 0x0678,
+ [PMIF_MONITOR_RECORD_19_2] = 0x067C,
+ [PMIF_MONITOR_RECORD_19_3] = 0x0680,
+ [PMIF_MONITOR_RECORD_19_4] = 0x0684,
+ [PMIF_MONITOR_RECORD_20_0] = 0x0688,
+ [PMIF_MONITOR_RECORD_20_1] = 0x068C,
+ [PMIF_MONITOR_RECORD_20_2] = 0x0690,
+ [PMIF_MONITOR_RECORD_20_3] = 0x0694,
+ [PMIF_MONITOR_RECORD_20_4] = 0x0698,
+ [PMIF_MONITOR_RECORD_21_0] = 0x069C,
+ [PMIF_MONITOR_RECORD_21_1] = 0x06A0,
+ [PMIF_MONITOR_RECORD_21_2] = 0x06A4,
+ [PMIF_MONITOR_RECORD_21_3] = 0x06A8,
+ [PMIF_MONITOR_RECORD_21_4] = 0x06AC,
+ [PMIF_MONITOR_RECORD_22_0] = 0x06B0,
+ [PMIF_MONITOR_RECORD_22_1] = 0x06B4,
+ [PMIF_MONITOR_RECORD_22_2] = 0x06B8,
+ [PMIF_MONITOR_RECORD_22_3] = 0x06BC,
+ [PMIF_MONITOR_RECORD_22_4] = 0x06C0,
+ [PMIF_MONITOR_RECORD_23_0] = 0x06C4,
+ [PMIF_MONITOR_RECORD_23_1] = 0x06C8,
+ [PMIF_MONITOR_RECORD_23_2] = 0x06CC,
+ [PMIF_MONITOR_RECORD_23_3] = 0x06D0,
+ [PMIF_MONITOR_RECORD_23_4] = 0x06D4,
+ [PMIF_MONITOR_RECORD_24_0] = 0x06D8,
+ [PMIF_MONITOR_RECORD_24_1] = 0x06DC,
+ [PMIF_MONITOR_RECORD_24_2] = 0x06E0,
+ [PMIF_MONITOR_RECORD_24_3] = 0x06E4,
+ [PMIF_MONITOR_RECORD_24_4] = 0x06E8,
+ [PMIF_MONITOR_RECORD_25_0] = 0x06EC,
+ [PMIF_MONITOR_RECORD_25_1] = 0x06F0,
+ [PMIF_MONITOR_RECORD_25_2] = 0x06F4,
+ [PMIF_MONITOR_RECORD_25_3] = 0x06F8,
+ [PMIF_MONITOR_RECORD_25_4] = 0x06FC,
+ [PMIF_MONITOR_RECORD_26_0] = 0x0700,
+ [PMIF_MONITOR_RECORD_26_1] = 0x0704,
+ [PMIF_MONITOR_RECORD_26_2] = 0x0708,
+ [PMIF_MONITOR_RECORD_26_3] = 0x070C,
+ [PMIF_MONITOR_RECORD_26_4] = 0x0710,
+ [PMIF_MONITOR_RECORD_27_0] = 0x0714,
+ [PMIF_MONITOR_RECORD_27_1] = 0x0718,
+ [PMIF_MONITOR_RECORD_27_2] = 0x071C,
+ [PMIF_MONITOR_RECORD_27_3] = 0x0720,
+ [PMIF_MONITOR_RECORD_27_4] = 0x0724,
+ [PMIF_MONITOR_RECORD_28_0] = 0x0728,
+ [PMIF_MONITOR_RECORD_28_1] = 0x072C,
+ [PMIF_MONITOR_RECORD_28_2] = 0x0730,
+ [PMIF_MONITOR_RECORD_28_3] = 0x0734,
+ [PMIF_MONITOR_RECORD_28_4] = 0x0738,
+ [PMIF_MONITOR_RECORD_29_0] = 0x073C,
+ [PMIF_MONITOR_RECORD_29_1] = 0x0740,
+ [PMIF_MONITOR_RECORD_29_2] = 0x0744,
+ [PMIF_MONITOR_RECORD_29_3] = 0x0748,
+ [PMIF_MONITOR_RECORD_29_4] = 0x074C,
+ [PMIF_MONITOR_RECORD_30_0] = 0x0750,
+ [PMIF_MONITOR_RECORD_30_1] = 0x0754,
+ [PMIF_MONITOR_RECORD_30_2] = 0x0758,
+ [PMIF_MONITOR_RECORD_30_3] = 0x075C,
+ [PMIF_MONITOR_RECORD_30_4] = 0x0760,
+ [PMIF_MONITOR_RECORD_31_0] = 0x0764,
+ [PMIF_MONITOR_RECORD_31_1] = 0x0768,
+ [PMIF_MONITOR_RECORD_31_2] = 0x076C,
+ [PMIF_MONITOR_RECORD_31_3] = 0x0770,
+ [PMIF_MONITOR_RECORD_31_4] = 0x0774,
+ [PMIF_DEBUG_CTRL] = 0x0778,
+ [PMIF_RESERVED_0] = 0x0780,
+ [PMIF_SWINF_0_ACC] = 0x0800,
+ [PMIF_SWINF_0_WDATA_31_0] = 0x0804,
+ [PMIF_SWINF_0_RDATA_31_0] = 0x0814,
+ [PMIF_SWINF_0_VLD_CLR] = 0x0824,
+ [PMIF_SWINF_0_STA] = 0x0828,
+ [PMIF_SWINF_1_ACC] = 0x0840,
+ [PMIF_SWINF_1_WDATA_31_0] = 0x0844,
+ [PMIF_SWINF_1_RDATA_31_0] = 0x0854,
+ [PMIF_SWINF_1_VLD_CLR] = 0x0864,
+ [PMIF_SWINF_1_STA] = 0x0868,
+ [PMIF_SWINF_2_ACC] = 0x0880,
+ [PMIF_SWINF_2_WDATA_31_0] = 0x0884,
+ [PMIF_SWINF_2_RDATA_31_0] = 0x0894,
+ [PMIF_SWINF_2_VLD_CLR] = 0x08A4,
+ [PMIF_SWINF_2_STA] = 0x08A8,
+ [PMIF_SWINF_3_ACC] = 0x08C0,
+ [PMIF_SWINF_3_WDATA_31_0] = 0x08C4,
+ [PMIF_SWINF_3_RDATA_31_0] = 0x08D4,
+ [PMIF_SWINF_3_VLD_CLR] = 0x08E4,
+ [PMIF_SWINF_3_STA] = 0x08E8,
+ [PMIC_ACC_VIO_INFO_0] = 0x0950,
+ [PMIC_ACC_VIO_INFO_1] = 0x0954,
+ [PMIC_ACC_VIO_INFO_2] = 0x0958,
+ [PMIC_ACC_VIO_INFO_3] = 0x095C,
+ [PMIC_ACC_VIO_INFO_4] = 0x0960,
+ [PMIC_ACC_VIO_INFO_5] = 0x0964,
+ [PMIC_ACC_SCP_VIO_INFO_0] = 0x0968,
+ [PMIC_ACC_SCP_VIO_INFO_1] = 0x096C,
+ [PMIC_ACC_SCP_VIO_INFO_2] = 0x0970,
+ [PMIC_ACC_SCP_VIO_INFO_3] = 0x0974,
+ [PMIC_ACC_SCP_VIO_INFO_4] = 0x0978,
+ [PMIC_ACC_SCP_VIO_INFO_5] = 0x097C,
+ [PMIF_ACC_VIO_INFO_0] = 0x0980,
+ [PMIF_ACC_VIO_INFO_1] = 0x0984,
+ [PMIF_ACC_VIO_INFO_2] = 0x0988,
+ [PMIC_ALL_ACC_VIO_INFO_0] = 0x098C,
+ [PMIC_ALL_ACC_VIO_INFO_1] = 0x0990,
+};
+
+static const u32 mt6873_pmif_dbg_regs[] = {
+ [PMIF_INIT_DONE] = 0x0000,
+ [PMIF_INF_BUSY_STA] = 0x0018,
+ [PMIF_OTHER_BUSY_STA_0] = 0x001C,
+ [PMIF_OTHER_BUSY_STA_1] = 0x0020,
+ [PMIF_IRQ_EVENT_EN_0] = 0x0418,
+ [PMIF_IRQ_FLAG_0] = 0x0420,
+ [PMIF_IRQ_CLR_0] = 0x0424,
+ [PMIF_IRQ_EVENT_EN_1] = 0x0428,
+ [PMIF_IRQ_FLAG_1] = 0x0430,
+ [PMIF_IRQ_CLR_1] = 0x0434,
+ [PMIF_IRQ_EVENT_EN_2] = 0x0438,
+ [PMIF_IRQ_FLAG_2] = 0x0440,
+ [PMIF_IRQ_CLR_2] = 0x0444,
+ [PMIF_IRQ_EVENT_EN_3] = 0x0448,
+ [PMIF_IRQ_FLAG_3] = 0x0450,
+ [PMIF_IRQ_CLR_3] = 0x0454,
+ [PMIF_IRQ_EVENT_EN_4] = 0x0458,
+ [PMIF_IRQ_FLAG_4] = 0x0460,
+ [PMIF_IRQ_CLR_4] = 0x0464,
+ [PMIF_WDT_EVENT_EN_0] = 0x046C,
+ [PMIF_WDT_FLAG_0] = 0x0470,
+ [PMIF_WDT_EVENT_EN_1] = 0x0474,
+ [PMIF_WDT_FLAG_1] = 0x0478,
+ [PMIF_MONITOR_CTRL] = 0x047C,
+ [PMIF_MONITOR_TARGET_CHAN_0] = 0x0480,
+ [PMIF_MONITOR_TARGET_CHAN_1] = 0x0484,
+ [PMIF_MONITOR_TARGET_CHAN_2] = 0x0488,
+ [PMIF_MONITOR_TARGET_CHAN_3] = 0x048C,
+ [PMIF_MONITOR_TARGET_CHAN_4] = 0x0490,
+ [PMIF_MONITOR_TARGET_CHAN_5] = 0x0494,
+ [PMIF_MONITOR_TARGET_CHAN_6] = 0x0498,
+ [PMIF_MONITOR_TARGET_CHAN_7] = 0x049C,
+ [PMIF_MONITOR_TARGET_WRITE] = 0x04A0,
+ [PMIF_MONITOR_TARGET_SLVID_0] = 0x04A4,
+ [PMIF_MONITOR_TARGET_SLVID_1] = 0x04A8,
+ [PMIF_MONITOR_TARGET_ADDR_0] = 0x04AC,
+ [PMIF_MONITOR_TARGET_ADDR_1] = 0x04B0,
+ [PMIF_MONITOR_TARGET_ADDR_2] = 0x04B4,
+ [PMIF_MONITOR_TARGET_ADDR_3] = 0x04B8,
+ [PMIF_MONITOR_TARGET_ADDR_4] = 0x04BC,
+ [PMIF_MONITOR_TARGET_ADDR_5] = 0x04C0,
+ [PMIF_MONITOR_TARGET_ADDR_6] = 0x04C4,
+ [PMIF_MONITOR_TARGET_ADDR_7] = 0x04C8,
+ [PMIF_MONITOR_TARGET_WDATA_0] = 0x04CC,
+ [PMIF_MONITOR_TARGET_WDATA_1] = 0x04D0,
+ [PMIF_MONITOR_TARGET_WDATA_2] = 0x04D4,
+ [PMIF_MONITOR_TARGET_WDATA_3] = 0x04D8,
+ [PMIF_MONITOR_TARGET_WDATA_4] = 0x04DC,
+ [PMIF_MONITOR_TARGET_WDATA_5] = 0x04E0,
+ [PMIF_MONITOR_TARGET_WDATA_6] = 0x04E4,
+ [PMIF_MONITOR_TARGET_WDATA_7] = 0x04E8,
+ [PMIF_MONITOR_STA] = 0x04EC,
+ [PMIF_MONITOR_RECORD_0_0] = 0x04F0,
+ [PMIF_MONITOR_RECORD_0_1] = 0x04F4,
+ [PMIF_MONITOR_RECORD_0_2] = 0x04F8,
+ [PMIF_MONITOR_RECORD_0_3] = 0x04FC,
+ [PMIF_MONITOR_RECORD_0_4] = 0x0500,
+ [PMIF_MONITOR_RECORD_1_0] = 0x0504,
+ [PMIF_MONITOR_RECORD_1_1] = 0x0508,
+ [PMIF_MONITOR_RECORD_1_2] = 0x050C,
+ [PMIF_MONITOR_RECORD_1_3] = 0x0510,
+ [PMIF_MONITOR_RECORD_1_4] = 0x0514,
+ [PMIF_MONITOR_RECORD_2_0] = 0x0518,
+ [PMIF_MONITOR_RECORD_2_1] = 0x051C,
+ [PMIF_MONITOR_RECORD_2_2] = 0x0520,
+ [PMIF_MONITOR_RECORD_2_3] = 0x0524,
+ [PMIF_MONITOR_RECORD_2_4] = 0x0528,
+ [PMIF_MONITOR_RECORD_3_0] = 0x052C,
+ [PMIF_MONITOR_RECORD_3_1] = 0x0530,
+ [PMIF_MONITOR_RECORD_3_2] = 0x0534,
+ [PMIF_MONITOR_RECORD_3_3] = 0x0538,
+ [PMIF_MONITOR_RECORD_3_4] = 0x053C,
+ [PMIF_MONITOR_RECORD_4_0] = 0x0540,
+ [PMIF_MONITOR_RECORD_4_1] = 0x0544,
+ [PMIF_MONITOR_RECORD_4_2] = 0x0548,
+ [PMIF_MONITOR_RECORD_4_3] = 0x054C,
+ [PMIF_MONITOR_RECORD_4_4] = 0x0550,
+ [PMIF_MONITOR_RECORD_5_0] = 0x0554,
+ [PMIF_MONITOR_RECORD_5_1] = 0x0558,
+ [PMIF_MONITOR_RECORD_5_2] = 0x055C,
+ [PMIF_MONITOR_RECORD_5_3] = 0x0560,
+ [PMIF_MONITOR_RECORD_5_4] = 0x0564,
+ [PMIF_MONITOR_RECORD_6_0] = 0x0568,
+ [PMIF_MONITOR_RECORD_6_1] = 0x056C,
+ [PMIF_MONITOR_RECORD_6_2] = 0x0570,
+ [PMIF_MONITOR_RECORD_6_3] = 0x0574,
+ [PMIF_MONITOR_RECORD_6_4] = 0x0578,
+ [PMIF_MONITOR_RECORD_7_0] = 0x057C,
+ [PMIF_MONITOR_RECORD_7_1] = 0x0580,
+ [PMIF_MONITOR_RECORD_7_2] = 0x0584,
+ [PMIF_MONITOR_RECORD_7_3] = 0x0588,
+ [PMIF_MONITOR_RECORD_7_4] = 0x058C,
+ [PMIF_MONITOR_RECORD_8_0] = 0x0590,
+ [PMIF_MONITOR_RECORD_8_1] = 0x0594,
+ [PMIF_MONITOR_RECORD_8_2] = 0x0598,
+ [PMIF_MONITOR_RECORD_8_3] = 0x059C,
+ [PMIF_MONITOR_RECORD_8_4] = 0x05A0,
+ [PMIF_MONITOR_RECORD_9_0] = 0x05A4,
+ [PMIF_MONITOR_RECORD_9_1] = 0x05A8,
+ [PMIF_MONITOR_RECORD_9_2] = 0x05AC,
+ [PMIF_MONITOR_RECORD_9_3] = 0x05B0,
+ [PMIF_MONITOR_RECORD_9_4] = 0x05B4,
+ [PMIF_MONITOR_RECORD_10_0] = 0x05B8,
+ [PMIF_MONITOR_RECORD_10_1] = 0x05BC,
+ [PMIF_MONITOR_RECORD_10_2] = 0x05C0,
+ [PMIF_MONITOR_RECORD_10_3] = 0x05C4,
+ [PMIF_MONITOR_RECORD_10_4] = 0x05C8,
+ [PMIF_MONITOR_RECORD_11_0] = 0x05CC,
+ [PMIF_MONITOR_RECORD_11_1] = 0x05D0,
+ [PMIF_MONITOR_RECORD_11_2] = 0x05D4,
+ [PMIF_MONITOR_RECORD_11_3] = 0x05D8,
+ [PMIF_MONITOR_RECORD_11_4] = 0x05DC,
+ [PMIF_MONITOR_RECORD_12_0] = 0x05E0,
+ [PMIF_MONITOR_RECORD_12_1] = 0x05E4,
+ [PMIF_MONITOR_RECORD_12_2] = 0x05E8,
+ [PMIF_MONITOR_RECORD_12_3] = 0x05EC,
+ [PMIF_MONITOR_RECORD_12_4] = 0x05F0,
+ [PMIF_MONITOR_RECORD_13_0] = 0x05F4,
+ [PMIF_MONITOR_RECORD_13_1] = 0x05F8,
+ [PMIF_MONITOR_RECORD_13_2] = 0x05FC,
+ [PMIF_MONITOR_RECORD_13_3] = 0x0600,
+ [PMIF_MONITOR_RECORD_13_4] = 0x0604,
+ [PMIF_MONITOR_RECORD_14_0] = 0x0608,
+ [PMIF_MONITOR_RECORD_14_1] = 0x060C,
+ [PMIF_MONITOR_RECORD_14_2] = 0x0610,
+ [PMIF_MONITOR_RECORD_14_3] = 0x0614,
+ [PMIF_MONITOR_RECORD_14_4] = 0x0618,
+ [PMIF_MONITOR_RECORD_15_0] = 0x061C,
+ [PMIF_MONITOR_RECORD_15_1] = 0x0620,
+ [PMIF_MONITOR_RECORD_15_2] = 0x0624,
+ [PMIF_MONITOR_RECORD_15_3] = 0x0628,
+ [PMIF_MONITOR_RECORD_15_4] = 0x062C,
+ [PMIF_MONITOR_RECORD_16_0] = 0x0630,
+ [PMIF_MONITOR_RECORD_16_1] = 0x0634,
+ [PMIF_MONITOR_RECORD_16_2] = 0x0638,
+ [PMIF_MONITOR_RECORD_16_3] = 0x063C,
+ [PMIF_MONITOR_RECORD_16_4] = 0x0640,
+ [PMIF_MONITOR_RECORD_17_0] = 0x0644,
+ [PMIF_MONITOR_RECORD_17_1] = 0x0648,
+ [PMIF_MONITOR_RECORD_17_2] = 0x064C,
+ [PMIF_MONITOR_RECORD_17_3] = 0x0650,
+ [PMIF_MONITOR_RECORD_17_4] = 0x0654,
+ [PMIF_MONITOR_RECORD_18_0] = 0x0658,
+ [PMIF_MONITOR_RECORD_18_1] = 0x065C,
+ [PMIF_MONITOR_RECORD_18_2] = 0x0660,
+ [PMIF_MONITOR_RECORD_18_3] = 0x0664,
+ [PMIF_MONITOR_RECORD_18_4] = 0x0668,
+ [PMIF_MONITOR_RECORD_19_0] = 0x066C,
+ [PMIF_MONITOR_RECORD_19_1] = 0x0670,
+ [PMIF_MONITOR_RECORD_19_2] = 0x0674,
+ [PMIF_MONITOR_RECORD_19_3] = 0x0678,
+ [PMIF_MONITOR_RECORD_19_4] = 0x067C,
+ [PMIF_MONITOR_RECORD_20_0] = 0x0680,
+ [PMIF_MONITOR_RECORD_20_1] = 0x0684,
+ [PMIF_MONITOR_RECORD_20_2] = 0x0688,
+ [PMIF_MONITOR_RECORD_20_3] = 0x068C,
+ [PMIF_MONITOR_RECORD_20_4] = 0x0690,
+ [PMIF_MONITOR_RECORD_21_0] = 0x0694,
+ [PMIF_MONITOR_RECORD_21_1] = 0x0698,
+ [PMIF_MONITOR_RECORD_21_2] = 0x069C,
+ [PMIF_MONITOR_RECORD_21_3] = 0x06A0,
+ [PMIF_MONITOR_RECORD_21_4] = 0x06A4,
+ [PMIF_MONITOR_RECORD_22_0] = 0x06A8,
+ [PMIF_MONITOR_RECORD_22_1] = 0x06AC,
+ [PMIF_MONITOR_RECORD_22_2] = 0x06B0,
+ [PMIF_MONITOR_RECORD_22_3] = 0x06B4,
+ [PMIF_MONITOR_RECORD_22_4] = 0x06B8,
+ [PMIF_MONITOR_RECORD_23_0] = 0x06BC,
+ [PMIF_MONITOR_RECORD_23_1] = 0x06C0,
+ [PMIF_MONITOR_RECORD_23_2] = 0x06C4,
+ [PMIF_MONITOR_RECORD_23_3] = 0x06C8,
+ [PMIF_MONITOR_RECORD_23_4] = 0x06CC,
+ [PMIF_MONITOR_RECORD_24_0] = 0x06D0,
+ [PMIF_MONITOR_RECORD_24_1] = 0x06D4,
+ [PMIF_MONITOR_RECORD_24_2] = 0x06D8,
+ [PMIF_MONITOR_RECORD_24_3] = 0x06DC,
+ [PMIF_MONITOR_RECORD_24_4] = 0x06E0,
+ [PMIF_MONITOR_RECORD_25_0] = 0x06E4,
+ [PMIF_MONITOR_RECORD_25_1] = 0x06E8,
+ [PMIF_MONITOR_RECORD_25_2] = 0x06EC,
+ [PMIF_MONITOR_RECORD_25_3] = 0x06F0,
+ [PMIF_MONITOR_RECORD_25_4] = 0x06F4,
+ [PMIF_MONITOR_RECORD_26_0] = 0x06F8,
+ [PMIF_MONITOR_RECORD_26_1] = 0x06FC,
+ [PMIF_MONITOR_RECORD_26_2] = 0x0700,
+ [PMIF_MONITOR_RECORD_26_3] = 0x0704,
+ [PMIF_MONITOR_RECORD_26_4] = 0x0708,
+ [PMIF_MONITOR_RECORD_27_0] = 0x070C,
+ [PMIF_MONITOR_RECORD_27_1] = 0x0710,
+ [PMIF_MONITOR_RECORD_27_2] = 0x0714,
+ [PMIF_MONITOR_RECORD_27_3] = 0x0718,
+ [PMIF_MONITOR_RECORD_27_4] = 0x071C,
+ [PMIF_MONITOR_RECORD_28_0] = 0x0720,
+ [PMIF_MONITOR_RECORD_28_1] = 0x0724,
+ [PMIF_MONITOR_RECORD_28_2] = 0x0728,
+ [PMIF_MONITOR_RECORD_28_3] = 0x072C,
+ [PMIF_MONITOR_RECORD_28_4] = 0x0730,
+ [PMIF_MONITOR_RECORD_29_0] = 0x0734,
+ [PMIF_MONITOR_RECORD_29_1] = 0x0738,
+ [PMIF_MONITOR_RECORD_29_2] = 0x073C,
+ [PMIF_MONITOR_RECORD_29_3] = 0x0740,
+ [PMIF_MONITOR_RECORD_29_4] = 0x0744,
+ [PMIF_MONITOR_RECORD_30_0] = 0x0748,
+ [PMIF_MONITOR_RECORD_30_1] = 0x074C,
+ [PMIF_MONITOR_RECORD_30_2] = 0x0750,
+ [PMIF_MONITOR_RECORD_30_3] = 0x0754,
+ [PMIF_MONITOR_RECORD_30_4] = 0x0758,
+ [PMIF_MONITOR_RECORD_31_0] = 0x075C,
+ [PMIF_MONITOR_RECORD_31_1] = 0x0760,
+ [PMIF_MONITOR_RECORD_31_2] = 0x0764,
+ [PMIF_MONITOR_RECORD_31_3] = 0x0768,
+ [PMIF_MONITOR_RECORD_31_4] = 0x076C,
+ [PMIF_DEBUG_CTRL] = 0x0770,
+ [PMIF_RESERVED_0] = 0x0778,
+ [PMIF_SWINF_0_ACC] = 0x0C00,
+ [PMIF_SWINF_0_WDATA_31_0] = 0x0C04,
+ [PMIF_SWINF_0_WDATA_63_32] = 0x0C08,
+ [PMIF_SWINF_0_RDATA_31_0] = 0x0C14,
+ [PMIF_SWINF_0_RDATA_63_32] = 0x0C18,
+ [PMIF_SWINF_0_VLD_CLR] = 0x0C24,
+ [PMIF_SWINF_0_STA] = 0x0C28,
+ [PMIF_SWINF_1_ACC] = 0x0C40,
+ [PMIF_SWINF_1_WDATA_31_0] = 0x0C44,
+ [PMIF_SWINF_1_WDATA_63_32] = 0x0C48,
+ [PMIF_SWINF_1_RDATA_31_0] = 0x0C54,
+ [PMIF_SWINF_1_RDATA_63_32] = 0x0C58,
+ [PMIF_SWINF_1_VLD_CLR] = 0x0C64,
+ [PMIF_SWINF_1_STA] = 0x0C68,
+ [PMIF_SWINF_2_ACC] = 0x0C80,
+ [PMIF_SWINF_2_WDATA_31_0] = 0x0C84,
+ [PMIF_SWINF_2_WDATA_63_32] = 0x0C88,
+ [PMIF_SWINF_2_RDATA_31_0] = 0x0C94,
+ [PMIF_SWINF_2_RDATA_63_32] = 0x0C98,
+ [PMIF_SWINF_2_VLD_CLR] = 0x0CA4,
+ [PMIF_SWINF_2_STA] = 0x0CA8,
+ [PMIF_SWINF_3_ACC] = 0x0CC0,
+ [PMIF_SWINF_3_WDATA_31_0] = 0x0CC4,
+ [PMIF_SWINF_3_WDATA_63_32] = 0x0CC8,
+ [PMIF_SWINF_3_RDATA_31_0] = 0x0CD4,
+ [PMIF_SWINF_3_RDATA_63_32] = 0x0CD8,
+ [PMIF_SWINF_3_VLD_CLR] = 0x0CE4,
+ [PMIF_SWINF_3_STA] = 0x0CE8,
+ [PMIC_ACC_VIO_INFO_0] = 0x0F50,
+ [PMIC_ACC_VIO_INFO_1] = 0x0F54,
+ [PMIC_ACC_VIO_INFO_2] = 0x0F58,
+ [PMIC_ACC_VIO_INFO_3] = 0x0F5C,
+ [PMIC_ACC_VIO_INFO_4] = 0x0F60,
+ [PMIC_ACC_VIO_INFO_5] = 0x0F64,
+ [PMIC_ACC_SCP_VIO_INFO_0] = 0x0F68,
+ [PMIC_ACC_SCP_VIO_INFO_1] = 0x0F6C,
+ [PMIC_ACC_SCP_VIO_INFO_2] = 0x0F70,
+ [PMIC_ACC_SCP_VIO_INFO_3] = 0x0F74,
+ [PMIC_ACC_SCP_VIO_INFO_4] = 0x0F78,
+ [PMIC_ACC_SCP_VIO_INFO_5] = 0x0F7C,
+ [PMIF_ACC_VIO_INFO_0] = 0x0F80,
+ [PMIF_ACC_VIO_INFO_1] = 0x0F84,
+ [PMIF_ACC_VIO_INFO_2] = 0x0F88,
+};
+
+static const u32 mt6885_pmif_dbg_regs[] = {
+ [PMIF_INIT_DONE] = 0x0000,
+ [PMIF_INF_BUSY_STA] = 0x0018,
+ [PMIF_OTHER_BUSY_STA_0] = 0x001C,
+ [PMIF_OTHER_BUSY_STA_1] = 0x0020,
+ [PMIF_IRQ_EVENT_EN_0] = 0x0418,
+ [PMIF_IRQ_FLAG_0] = 0x0420,
+ [PMIF_IRQ_CLR_0] = 0x0424,
+ [PMIF_IRQ_EVENT_EN_1] = 0x0428,
+ [PMIF_IRQ_FLAG_1] = 0x0430,
+ [PMIF_IRQ_CLR_1] = 0x0434,
+ [PMIF_IRQ_EVENT_EN_2] = 0x0438,
+ [PMIF_IRQ_FLAG_2] = 0x0440,
+ [PMIF_IRQ_CLR_2] = 0x0444,
+ [PMIF_IRQ_EVENT_EN_3] = 0x0448,
+ [PMIF_IRQ_FLAG_3] = 0x0450,
+ [PMIF_IRQ_CLR_3] = 0x0454,
+ [PMIF_IRQ_EVENT_EN_4] = 0x0458,
+ [PMIF_IRQ_FLAG_4] = 0x0460,
+ [PMIF_IRQ_CLR_4] = 0x0464,
+ [PMIF_WDT_EVENT_EN_0] = 0x046C,
+ [PMIF_WDT_FLAG_0] = 0x0470,
+ [PMIF_WDT_EVENT_EN_1] = 0x0474,
+ [PMIF_WDT_FLAG_1] = 0x0478,
+ [PMIF_MONITOR_CTRL] = 0x047C,
+ [PMIF_MONITOR_TARGET_CHAN_0] = 0x0480,
+ [PMIF_MONITOR_TARGET_CHAN_1] = 0x0484,
+ [PMIF_MONITOR_TARGET_CHAN_2] = 0x0488,
+ [PMIF_MONITOR_TARGET_CHAN_3] = 0x048C,
+ [PMIF_MONITOR_TARGET_CHAN_4] = 0x0490,
+ [PMIF_MONITOR_TARGET_CHAN_5] = 0x0494,
+ [PMIF_MONITOR_TARGET_CHAN_6] = 0x0498,
+ [PMIF_MONITOR_TARGET_CHAN_7] = 0x049C,
+ [PMIF_MONITOR_TARGET_WRITE] = 0x04A0,
+ [PMIF_MONITOR_TARGET_ADDR_0] = 0x04A4,
+ [PMIF_MONITOR_TARGET_ADDR_1] = 0x04A8,
+ [PMIF_MONITOR_TARGET_ADDR_2] = 0x04AC,
+ [PMIF_MONITOR_TARGET_ADDR_3] = 0x04B0,
+ [PMIF_MONITOR_TARGET_ADDR_4] = 0x04B4,
+ [PMIF_MONITOR_TARGET_ADDR_5] = 0x04B8,
+ [PMIF_MONITOR_TARGET_ADDR_6] = 0x04BC,
+ [PMIF_MONITOR_TARGET_ADDR_7] = 0x04C0,
+ [PMIF_MONITOR_TARGET_WDATA_0] = 0x04C4,
+ [PMIF_MONITOR_TARGET_WDATA_1] = 0x04C8,
+ [PMIF_MONITOR_TARGET_WDATA_2] = 0x04CC,
+ [PMIF_MONITOR_TARGET_WDATA_3] = 0x04D0,
+ [PMIF_MONITOR_TARGET_WDATA_4] = 0x04D4,
+ [PMIF_MONITOR_TARGET_WDATA_5] = 0x04D8,
+ [PMIF_MONITOR_TARGET_WDATA_6] = 0x04DC,
+ [PMIF_MONITOR_TARGET_WDATA_7] = 0x04E0,
+ [PMIF_MONITOR_STA] = 0x04E4,
+ [PMIF_MONITOR_RECORD_0_0] = 0x04E8,
+ [PMIF_MONITOR_RECORD_0_1] = 0x04EC,
+ [PMIF_MONITOR_RECORD_0_2] = 0x04F0,
+ [PMIF_MONITOR_RECORD_0_3] = 0x04F4,
+ [PMIF_MONITOR_RECORD_0_4] = 0x04F8,
+ [PMIF_MONITOR_RECORD_1_0] = 0x04FC,
+ [PMIF_MONITOR_RECORD_1_1] = 0x0500,
+ [PMIF_MONITOR_RECORD_1_2] = 0x0504,
+ [PMIF_MONITOR_RECORD_1_3] = 0x0508,
+ [PMIF_MONITOR_RECORD_1_4] = 0x050C,
+ [PMIF_MONITOR_RECORD_2_0] = 0x0510,
+ [PMIF_MONITOR_RECORD_2_1] = 0x0514,
+ [PMIF_MONITOR_RECORD_2_2] = 0x0518,
+ [PMIF_MONITOR_RECORD_2_3] = 0x051C,
+ [PMIF_MONITOR_RECORD_2_4] = 0x0520,
+ [PMIF_MONITOR_RECORD_3_0] = 0x0524,
+ [PMIF_MONITOR_RECORD_3_1] = 0x0528,
+ [PMIF_MONITOR_RECORD_3_2] = 0x052C,
+ [PMIF_MONITOR_RECORD_3_3] = 0x0530,
+ [PMIF_MONITOR_RECORD_3_4] = 0x0534,
+ [PMIF_MONITOR_RECORD_4_0] = 0x0538,
+ [PMIF_MONITOR_RECORD_4_1] = 0x053C,
+ [PMIF_MONITOR_RECORD_4_2] = 0x0540,
+ [PMIF_MONITOR_RECORD_4_3] = 0x0544,
+ [PMIF_MONITOR_RECORD_4_4] = 0x0548,
+ [PMIF_MONITOR_RECORD_5_0] = 0x054C,
+ [PMIF_MONITOR_RECORD_5_1] = 0x0550,
+ [PMIF_MONITOR_RECORD_5_2] = 0x0554,
+ [PMIF_MONITOR_RECORD_5_3] = 0x0558,
+ [PMIF_MONITOR_RECORD_5_4] = 0x055C,
+ [PMIF_MONITOR_RECORD_6_0] = 0x0560,
+ [PMIF_MONITOR_RECORD_6_1] = 0x0564,
+ [PMIF_MONITOR_RECORD_6_2] = 0x0568,
+ [PMIF_MONITOR_RECORD_6_3] = 0x056C,
+ [PMIF_MONITOR_RECORD_6_4] = 0x0570,
+ [PMIF_MONITOR_RECORD_7_0] = 0x0574,
+ [PMIF_MONITOR_RECORD_7_1] = 0x0578,
+ [PMIF_MONITOR_RECORD_7_2] = 0x057C,
+ [PMIF_MONITOR_RECORD_7_3] = 0x0580,
+ [PMIF_MONITOR_RECORD_7_4] = 0x0584,
+ [PMIF_MONITOR_RECORD_8_0] = 0x0588,
+ [PMIF_MONITOR_RECORD_8_1] = 0x058C,
+ [PMIF_MONITOR_RECORD_8_2] = 0x0590,
+ [PMIF_MONITOR_RECORD_8_3] = 0x0594,
+ [PMIF_MONITOR_RECORD_8_4] = 0x0598,
+ [PMIF_MONITOR_RECORD_9_0] = 0x059C,
+ [PMIF_MONITOR_RECORD_9_1] = 0x05A0,
+ [PMIF_MONITOR_RECORD_9_2] = 0x05A4,
+ [PMIF_MONITOR_RECORD_9_3] = 0x05A8,
+ [PMIF_MONITOR_RECORD_9_4] = 0x05AC,
+ [PMIF_MONITOR_RECORD_10_0] = 0x05B0,
+ [PMIF_MONITOR_RECORD_10_1] = 0x05B4,
+ [PMIF_MONITOR_RECORD_10_2] = 0x05B8,
+ [PMIF_MONITOR_RECORD_10_3] = 0x05BC,
+ [PMIF_MONITOR_RECORD_10_4] = 0x05C0,
+ [PMIF_MONITOR_RECORD_11_0] = 0x05C4,
+ [PMIF_MONITOR_RECORD_11_1] = 0x05C8,
+ [PMIF_MONITOR_RECORD_11_2] = 0x05CC,
+ [PMIF_MONITOR_RECORD_11_3] = 0x05D0,
+ [PMIF_MONITOR_RECORD_11_4] = 0x05D4,
+ [PMIF_MONITOR_RECORD_12_0] = 0x05D8,
+ [PMIF_MONITOR_RECORD_12_1] = 0x05DC,
+ [PMIF_MONITOR_RECORD_12_2] = 0x05E0,
+ [PMIF_MONITOR_RECORD_12_3] = 0x05E4,
+ [PMIF_MONITOR_RECORD_12_4] = 0x05E8,
+ [PMIF_MONITOR_RECORD_13_0] = 0x05EC,
+ [PMIF_MONITOR_RECORD_13_1] = 0x05F0,
+ [PMIF_MONITOR_RECORD_13_2] = 0x05F4,
+ [PMIF_MONITOR_RECORD_13_3] = 0x05F8,
+ [PMIF_MONITOR_RECORD_13_4] = 0x05FC,
+ [PMIF_MONITOR_RECORD_14_0] = 0x0600,
+ [PMIF_MONITOR_RECORD_14_1] = 0x0604,
+ [PMIF_MONITOR_RECORD_14_2] = 0x0608,
+ [PMIF_MONITOR_RECORD_14_3] = 0x060C,
+ [PMIF_MONITOR_RECORD_14_4] = 0x0610,
+ [PMIF_MONITOR_RECORD_15_0] = 0x0614,
+ [PMIF_MONITOR_RECORD_15_1] = 0x0618,
+ [PMIF_MONITOR_RECORD_15_2] = 0x061C,
+ [PMIF_MONITOR_RECORD_15_3] = 0x0620,
+ [PMIF_MONITOR_RECORD_15_4] = 0x0624,
+ [PMIF_MONITOR_RECORD_16_0] = 0x0628,
+ [PMIF_MONITOR_RECORD_16_1] = 0x062C,
+ [PMIF_MONITOR_RECORD_16_2] = 0x0630,
+ [PMIF_MONITOR_RECORD_16_3] = 0x0634,
+ [PMIF_MONITOR_RECORD_16_4] = 0x0638,
+ [PMIF_MONITOR_RECORD_17_0] = 0x063C,
+ [PMIF_MONITOR_RECORD_17_1] = 0x0640,
+ [PMIF_MONITOR_RECORD_17_2] = 0x0644,
+ [PMIF_MONITOR_RECORD_17_3] = 0x0648,
+ [PMIF_MONITOR_RECORD_17_4] = 0x064C,
+ [PMIF_MONITOR_RECORD_18_0] = 0x0650,
+ [PMIF_MONITOR_RECORD_18_1] = 0x0654,
+ [PMIF_MONITOR_RECORD_18_2] = 0x0658,
+ [PMIF_MONITOR_RECORD_18_3] = 0x065C,
+ [PMIF_MONITOR_RECORD_18_4] = 0x0660,
+ [PMIF_MONITOR_RECORD_19_0] = 0x0664,
+ [PMIF_MONITOR_RECORD_19_1] = 0x0668,
+ [PMIF_MONITOR_RECORD_19_2] = 0x066C,
+ [PMIF_MONITOR_RECORD_19_3] = 0x0670,
+ [PMIF_MONITOR_RECORD_19_4] = 0x0674,
+ [PMIF_MONITOR_RECORD_20_0] = 0x0678,
+ [PMIF_MONITOR_RECORD_20_1] = 0x067C,
+ [PMIF_MONITOR_RECORD_20_2] = 0x0680,
+ [PMIF_MONITOR_RECORD_20_3] = 0x0684,
+ [PMIF_MONITOR_RECORD_20_4] = 0x0688,
+ [PMIF_MONITOR_RECORD_21_0] = 0x068C,
+ [PMIF_MONITOR_RECORD_21_1] = 0x0690,
+ [PMIF_MONITOR_RECORD_21_2] = 0x0694,
+ [PMIF_MONITOR_RECORD_21_3] = 0x0698,
+ [PMIF_MONITOR_RECORD_21_4] = 0x069C,
+ [PMIF_MONITOR_RECORD_22_0] = 0x06A0,
+ [PMIF_MONITOR_RECORD_22_1] = 0x06A4,
+ [PMIF_MONITOR_RECORD_22_2] = 0x06A8,
+ [PMIF_MONITOR_RECORD_22_3] = 0x06AC,
+ [PMIF_MONITOR_RECORD_22_4] = 0x06B0,
+ [PMIF_MONITOR_RECORD_23_0] = 0x06B4,
+ [PMIF_MONITOR_RECORD_23_1] = 0x06B8,
+ [PMIF_MONITOR_RECORD_23_2] = 0x06BC,
+ [PMIF_MONITOR_RECORD_23_3] = 0x06C0,
+ [PMIF_MONITOR_RECORD_23_4] = 0x06C4,
+ [PMIF_MONITOR_RECORD_24_0] = 0x06C8,
+ [PMIF_MONITOR_RECORD_24_1] = 0x06CC,
+ [PMIF_MONITOR_RECORD_24_2] = 0x06D0,
+ [PMIF_MONITOR_RECORD_24_3] = 0x06D4,
+ [PMIF_MONITOR_RECORD_24_4] = 0x06D8,
+ [PMIF_MONITOR_RECORD_25_0] = 0x06DC,
+ [PMIF_MONITOR_RECORD_25_1] = 0x06E0,
+ [PMIF_MONITOR_RECORD_25_2] = 0x06E4,
+ [PMIF_MONITOR_RECORD_25_3] = 0x06E8,
+ [PMIF_MONITOR_RECORD_25_4] = 0x06EC,
+ [PMIF_MONITOR_RECORD_26_0] = 0x06F0,
+ [PMIF_MONITOR_RECORD_26_1] = 0x06F4,
+ [PMIF_MONITOR_RECORD_26_2] = 0x06F8,
+ [PMIF_MONITOR_RECORD_26_3] = 0x06FC,
+ [PMIF_MONITOR_RECORD_26_4] = 0x0700,
+ [PMIF_MONITOR_RECORD_27_0] = 0x0704,
+ [PMIF_MONITOR_RECORD_27_1] = 0x0708,
+ [PMIF_MONITOR_RECORD_27_2] = 0x070C,
+ [PMIF_MONITOR_RECORD_27_3] = 0x0710,
+ [PMIF_MONITOR_RECORD_27_4] = 0x0714,
+ [PMIF_MONITOR_RECORD_28_0] = 0x0718,
+ [PMIF_MONITOR_RECORD_28_1] = 0x071C,
+ [PMIF_MONITOR_RECORD_28_2] = 0x0720,
+ [PMIF_MONITOR_RECORD_28_3] = 0x0724,
+ [PMIF_MONITOR_RECORD_28_4] = 0x0728,
+ [PMIF_MONITOR_RECORD_29_0] = 0x072C,
+ [PMIF_MONITOR_RECORD_29_1] = 0x0730,
+ [PMIF_MONITOR_RECORD_29_2] = 0x0734,
+ [PMIF_MONITOR_RECORD_29_3] = 0x0738,
+ [PMIF_MONITOR_RECORD_29_4] = 0x073C,
+ [PMIF_MONITOR_RECORD_30_0] = 0x0740,
+ [PMIF_MONITOR_RECORD_30_1] = 0x0744,
+ [PMIF_MONITOR_RECORD_30_2] = 0x0748,
+ [PMIF_MONITOR_RECORD_30_3] = 0x074C,
+ [PMIF_MONITOR_RECORD_30_4] = 0x0750,
+ [PMIF_MONITOR_RECORD_31_0] = 0x0754,
+ [PMIF_MONITOR_RECORD_31_1] = 0x0758,
+ [PMIF_MONITOR_RECORD_31_2] = 0x075C,
+ [PMIF_MONITOR_RECORD_31_3] = 0x0760,
+ [PMIF_MONITOR_RECORD_31_4] = 0x0764,
+ [PMIF_DEBUG_CTRL] = 0x0768,
+ [PMIF_RESERVED_0] = 0x0770,
+ [PMIF_SWINF_0_ACC] = 0x0C00,
+ [PMIF_SWINF_0_WDATA_31_0] = 0x0C04,
+ [PMIF_SWINF_0_WDATA_63_32] = 0x0C08,
+ [PMIF_SWINF_0_RDATA_31_0] = 0x0C14,
+ [PMIF_SWINF_0_RDATA_63_32] = 0x0C18,
+ [PMIF_SWINF_0_VLD_CLR] = 0x0C24,
+ [PMIF_SWINF_0_STA] = 0x0C28,
+ [PMIF_SWINF_1_ACC] = 0x0C40,
+ [PMIF_SWINF_1_WDATA_31_0] = 0x0C44,
+ [PMIF_SWINF_1_WDATA_63_32] = 0x0C48,
+ [PMIF_SWINF_1_RDATA_31_0] = 0x0C54,
+ [PMIF_SWINF_1_RDATA_63_32] = 0x0C58,
+ [PMIF_SWINF_1_VLD_CLR] = 0x0C64,
+ [PMIF_SWINF_1_STA] = 0x0C68,
+ [PMIF_SWINF_2_ACC] = 0x0C80,
+ [PMIF_SWINF_2_WDATA_31_0] = 0x0C84,
+ [PMIF_SWINF_2_WDATA_63_32] = 0x0C88,
+ [PMIF_SWINF_2_RDATA_31_0] = 0x0C94,
+ [PMIF_SWINF_2_RDATA_63_32] = 0x0C98,
+ [PMIF_SWINF_2_VLD_CLR] = 0x0CA4,
+ [PMIF_SWINF_2_STA] = 0x0CA8,
+ [PMIF_SWINF_3_ACC] = 0x0CC0,
+ [PMIF_SWINF_3_WDATA_31_0] = 0x0CC4,
+ [PMIF_SWINF_3_WDATA_63_32] = 0x0CC8,
+ [PMIF_SWINF_3_RDATA_31_0] = 0x0CD4,
+ [PMIF_SWINF_3_RDATA_63_32] = 0x0CD8,
+ [PMIF_SWINF_3_VLD_CLR] = 0x0CE4,
+ [PMIF_SWINF_3_STA] = 0x0CE8,
+ [PMIC_ACC_VIO_INFO_0] = 0x0F50,
+ [PMIC_ACC_VIO_INFO_1] = 0x0F54,
+ [PMIC_ACC_VIO_INFO_2] = 0x0F58,
+ [PMIC_ACC_VIO_INFO_3] = 0x0F5C,
+ [PMIC_ACC_VIO_INFO_4] = 0x0F60,
+ [PMIC_ACC_VIO_INFO_5] = 0x0F64,
+ [PMIC_ACC_SCP_VIO_INFO_0] = 0x0F68,
+ [PMIC_ACC_SCP_VIO_INFO_1] = 0x0F6C,
+ [PMIC_ACC_SCP_VIO_INFO_2] = 0x0F70,
+ [PMIC_ACC_SCP_VIO_INFO_3] = 0x0F74,
+ [PMIC_ACC_SCP_VIO_INFO_4] = 0x0F78,
+ [PMIC_ACC_SCP_VIO_INFO_5] = 0x0F7C,
+ [PMIF_ACC_VIO_INFO_0] = 0x0F80,
+ [PMIF_ACC_VIO_INFO_1] = 0x0F84,
+ [PMIF_ACC_VIO_INFO_2] = 0x0F88,
+};
+
+static char d_log_buf[1280];
+static struct spmi_controller *dbg_ctrl;
+static char *wp;
+
+/* spmi & pmif debug mechanism */
+void spmi_dump_wdt_reg(void)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl);
+ unsigned int offset, tmp_dat;
+ unsigned int start, end, log_size = 0;
+
+ start = arb->dbgregs[PMIF_WDT_EVENT_EN_0];
+ end = arb->dbgregs[PMIF_WDT_FLAG_1];
+
+ for (offset = start; offset <= end; offset += 4) {
+ tmp_dat = readl(arb->base + offset);
+ log_size += sprintf(wp + log_size, "(0x%x)=0x%x ",
+ offset, tmp_dat);
+ }
+ log_size += sprintf(wp + log_size, "\n");
+ pr_info("[PMIF] %s", wp);
+}
+
+void spmi_dump_pmif_acc_vio_reg(void)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl);
+ unsigned int offset, tmp_dat;
+ unsigned int start, end, log_size = 0;
+
+ start = arb->dbgregs[PMIF_ACC_VIO_INFO_0];
+ if (arb->dbgver == 2)
+ end = arb->dbgregs[PMIC_ALL_ACC_VIO_INFO_1];
+ else
+ end = arb->dbgregs[PMIF_ACC_VIO_INFO_2];
+
+ for (offset = start; offset <= end; offset += 4) {
+ tmp_dat = readl(arb->base + offset);
+ log_size += sprintf(wp + log_size, "(0x%x)=0x%x ",
+ offset, tmp_dat);
+ }
+ log_size += sprintf(wp + log_size, "\n");
+ pr_info("[PMIF] %s", wp);
+}
+
+void spmi_dump_pmic_acc_vio_reg(void)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl);
+ unsigned int offset, tmp_dat;
+ unsigned int start, end, log_size = 0;
+
+ start = arb->dbgregs[PMIC_ACC_VIO_INFO_0];
+ end = arb->dbgregs[PMIC_ACC_VIO_INFO_5];
+
+ for (offset = start; offset <= end; offset += 4) {
+ tmp_dat = readl(arb->base + offset);
+ log_size += sprintf(wp + log_size, "(0x%x)=0x%x ",
+ offset, tmp_dat);
+ }
+ log_size += sprintf(wp + log_size, "\n");
+ pr_info("[PMIF] %s", wp);
+}
+
+static char *get_pmif_busy_reg_dump(void)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl);
+ unsigned int offset, tmp_dat;
+ unsigned int start, end, log_size = 0;
+
+ start = arb->dbgregs[PMIF_INF_BUSY_STA];
+ end = arb->dbgregs[PMIF_OTHER_BUSY_STA_1];
+
+ for (offset = start; offset <= end; offset += 4) {
+ tmp_dat = readl(arb->base + offset);
+ log_size += sprintf(wp + log_size, "(0x%x)=0x%x ",
+ offset, tmp_dat);
+ }
+ log_size += sprintf(wp + log_size, "\n");
+ return wp;
+}
+
+static char *get_pmif_swinf_reg_dump(void)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl);
+ unsigned int swinf = 0, step, offset, tmp_dat, log_size = 0;
+ unsigned int cmd, is_write, slvid, bytecnt, addr;
+ unsigned int wd_31_0, rd_31_0;
+ unsigned int err, sbusy, done, qfillcnt, qfreecnt, qempty, qfull;
+ unsigned int req, fsm, en;
+
+ step = arb->dbgregs[PMIF_SWINF_1_ACC] - arb->dbgregs[PMIF_SWINF_0_ACC];
+ for (swinf = 0; swinf < 4; swinf++) {
+ offset = arb->dbgregs[PMIF_SWINF_0_ACC] + swinf * step;
+ tmp_dat = readl(arb->base + offset);
+ cmd = (tmp_dat & (0x3 << 30)) >> 30;
+ is_write = (tmp_dat & (0x1 << 29)) >> 29;
+ slvid = (tmp_dat & (0xf << 24)) >> 24;
+ bytecnt = (tmp_dat & (0xf << 16)) >> 16;
+ addr = (tmp_dat & (0xffff << 0)) >> 0;
+
+ offset = arb->dbgregs[PMIF_SWINF_0_WDATA_31_0] + swinf * step;
+ wd_31_0 = readl(arb->base + offset);
+
+ offset = arb->dbgregs[PMIF_SWINF_0_RDATA_31_0] + swinf * step;
+ rd_31_0 = readl(arb->base + offset);
+
+ offset = arb->dbgregs[PMIF_SWINF_0_STA] + swinf * step;
+ tmp_dat = readl(arb->base + offset);
+ err = (tmp_dat & (0x1 << 18)) >> 18;
+ sbusy = (tmp_dat & (0x1 << 17)) >> 17;
+ done = (tmp_dat & (0x1 << 15)) >> 15;
+ qfillcnt = (tmp_dat & (0xf << 11)) >> 11;
+ qfreecnt = (tmp_dat & (0xf << 7)) >> 7;
+ qempty = (tmp_dat & (0x1 << 6)) >> 6;
+ qfull = (tmp_dat & (0x1 << 5)) >> 5;
+ req = (tmp_dat & (0x1 << 4)) >> 4;
+ fsm = (tmp_dat & (0x7 << 1)) >> 1;
+ en = (tmp_dat & (0x1 << 0)) >> 0;
+
+ log_size += sprintf(
+ wp + log_size,
+ "[swinf:%d, cmd:0x%x, is_write:%d, slvid:%d ",
+ swinf, cmd, is_write, slvid);
+ if (is_write) {
+ log_size += sprintf(
+ wp + log_size,
+ "bytecnt:%d (write addr 0x%x=0x%x)]\n",
+ bytecnt, addr, wd_31_0);
+ } else {
+ log_size += sprintf(
+ wp + log_size,
+ "bytecnt:%d (read addr 0x%x=0x%x)]\n",
+ bytecnt, addr, rd_31_0);
+ }
+ log_size += sprintf(
+ wp + log_size,
+ "[err:%d, sbusy:%d, done:%d, qfillcnt:%d ",
+ err, sbusy, done, qfillcnt);
+ log_size += sprintf(
+ wp + log_size,
+ "qfreecnt:%d, qempty:%d, qfull:%d, req:%d ",
+ qfreecnt, qempty, qfull, req);
+ log_size += sprintf(wp + log_size, "fsm:%d, en:%d]\n", fsm, en);
+ }
+ log_size += sprintf(wp + log_size, "\n");
+ return wp;
+}
+
+static char *get_spmimst_all_reg_dump(void)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl);
+ unsigned int tmp_dat, log_size = 0;
+ int i;
+
+ log_size += sprintf(wp, "\n[SPMI] ");
+ for (i = 0; i < SPMI_NUM_REGS; i++) {
+ tmp_dat = readl(arb->spmimst_base + arb->spmimst_regs[i]);
+ log_size += sprintf(wp + log_size, "(0x%x)=0x%x ",
+ arb->spmimst_regs[i], tmp_dat);
+ if ((i + 1) % 8 == 0)
+ log_size += sprintf(wp + log_size, "\n[SPMI] ");
+ }
+ log_size += sprintf(wp + log_size, "\n");
+ return wp;
+}
+
+void spmi_dump_pmif_busy_reg(void)
+{
+ pr_info("[PMIF] %s", get_pmif_busy_reg_dump());
+}
+
+static void spmi_dump_pmif_busy_reg_d(struct seq_file *m)
+{
+ seq_puts(m, get_pmif_busy_reg_dump());
+}
+
+void spmi_dump_pmif_swinf_reg(void)
+{
+ pr_info("[PMIF]\n%s", get_pmif_swinf_reg_dump());
+}
+
+static void spmi_dump_pmif_swinf_reg_d(struct seq_file *m)
+{
+ seq_puts(m, get_pmif_swinf_reg_dump());
+}
+
+void spmi_dump_pmif_all_reg(void)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl);
+ unsigned int offset, tmp_dat, log_size = 0;
+ unsigned int start, end;
+ int i = 0;
+
+ start = arb->dbgregs[PMIF_INIT_DONE];
+ end = arb->dbgregs[PMIF_RESERVED_0];
+
+ for (offset = start; offset <= end; offset += 4) {
+ tmp_dat = readl(arb->base + offset);
+ log_size += sprintf(wp + log_size, "(0x%x)=0x%x ",
+ offset, tmp_dat);
+ i++;
+ if (i % 64 == 0) {
+ pr_info("\n[PMIF] %s", wp);
+ log_size = 0;
+ } else if (i % 8 == 0)
+ log_size += sprintf(wp + log_size, "\n[PMIF] ");
+ }
+ pr_info("\n[PMIF] %s", wp);
+}
+
+static void spmi_dump_pmif_all_reg_d(struct seq_file *m)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl);
+ unsigned int offset, tmp_dat;
+ unsigned int start, end;
+
+ start = arb->dbgregs[PMIF_INIT_DONE];
+ end = arb->dbgregs[PMIF_RESERVED_0];
+
+ for (offset = start; offset <= end; offset += 4) {
+ tmp_dat = readl(arb->base + offset);
+ seq_printf(m, "(0x%x)=0x%x ", offset, tmp_dat);
+ }
+ seq_puts(m, "\n");
+}
+
+void spmi_dump_pmif_record_reg(void)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl);
+ unsigned int i = 0, step, offset, tmp_dat;
+ unsigned int chan, cmd, is_write, slvid, bytecnt, addr;
+ unsigned int wd_31_0, log_size = 0;
+ char wd_str[15] = "";
+
+ /* stop logging */
+ writel(0, arb->base + arb->dbgregs[PMIF_MONITOR_CTRL]);
+ step = arb->dbgregs[PMIF_MONITOR_RECORD_1_0] -
+ arb->dbgregs[PMIF_MONITOR_RECORD_0_0];
+
+ for (i = 0; i < 32; i++) {
+ offset = arb->dbgregs[PMIF_MONITOR_RECORD_0_0] + i * step;
+ tmp_dat = readl(arb->base + offset);
+ chan = (tmp_dat & (0x1f << 27)) >> 27;
+ cmd = (tmp_dat & (0x3 << 25)) >> 25;
+ is_write = (tmp_dat & (0x1 << 24)) >> 24;
+ slvid = (tmp_dat & (0xf << 20)) >> 20;
+ bytecnt = (tmp_dat & (0xf << 16)) >> 16;
+ addr = (tmp_dat & (0xffff << 0)) >> 0;
+
+ offset = arb->dbgregs[PMIF_MONITOR_RECORD_0_1] + i * step;
+ wd_31_0 = readl(arb->base + offset);
+ if (is_write)
+ snprintf(wd_str, 12, "=0x%x", wd_31_0);
+ else
+ wd_str[0] = '\0';
+
+ log_size += sprintf(wp + log_size,
+ "[PMIF] (%d)[chan:%d, cmd:0x%x, rw:0x%x, slvid:%d, ",
+ i, chan, cmd, is_write, slvid);
+ log_size += sprintf(wp + log_size,
+ "bytecnt:%d, (addr 0x%x%s)]\n",
+ bytecnt, addr, wd_str);
+ if ((i + 1) % 8 == 0) {
+ pr_info("\n%s", wp);
+ log_size = 0;
+ }
+ }
+ /* logging mode no need to clear record, re-enable logging */
+ writel(0x5, arb->base + arb->dbgregs[PMIF_MONITOR_CTRL]);
+}
+
+static void spmi_dump_pmif_record_reg_d(struct seq_file *m)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl);
+ unsigned int i = 0, step, offset, tmp_dat;
+ unsigned int chan, cmd, is_write, slvid, bytecnt, addr;
+ unsigned int wd_31_0;
+ char wd_str[15] = "";
+
+ /* stop logging */
+ writel(0, arb->base + arb->dbgregs[PMIF_MONITOR_CTRL]);
+ step = arb->dbgregs[PMIF_MONITOR_RECORD_1_0] -
+ arb->dbgregs[PMIF_MONITOR_RECORD_0_0];
+ step = arb->dbgregs[PMIF_MONITOR_RECORD_1_0] -
+ arb->dbgregs[PMIF_MONITOR_RECORD_0_0];
+
+ for (i = 0; i < 32; i++) {
+ offset = arb->dbgregs[PMIF_MONITOR_RECORD_0_0] + i * step;
+ tmp_dat = readl(arb->base + offset);
+ chan = (tmp_dat & (0x1f << 27)) >> 27;
+ cmd = (tmp_dat & (0x3 << 25)) >> 25;
+ is_write = (tmp_dat & (0x1 << 24)) >> 24;
+ slvid = (tmp_dat & (0xf << 20)) >> 20;
+ bytecnt = (tmp_dat & (0xf << 16)) >> 16;
+ addr = (tmp_dat & (0xffff << 0)) >> 0;
+
+ offset = arb->dbgregs[PMIF_MONITOR_RECORD_0_1] + i * step;
+ wd_31_0 = readl(arb->base + offset);
+ if (is_write)
+ snprintf(wd_str, 12, "=0x%x", wd_31_0);
+ else
+ wd_str[0] = '\0';
+
+ seq_printf(m, "(%d)[chan:%d, cmd:0x%x, rw:0x%x, slvid:%d, ",
+ i, chan, cmd, is_write, slvid);
+ seq_printf(m, "bytecnt:%d, (addr 0x%x%s)]\n",
+ bytecnt, addr, wd_str);
+ }
+ /* logging mode no need to clear record, re-enable logging */
+ writel(0x5, arb->base + arb->dbgregs[PMIF_MONITOR_CTRL]);
+}
+
+void spmi_dump_spmimst_all_reg(void)
+{
+ pr_info("%s", get_spmimst_all_reg_dump());
+}
+
+static void spmi_dump_spmimst_all_reg_d(struct seq_file *m)
+{
+ seq_puts(m, get_spmimst_all_reg_dump());
+}
+
+/*
+ * PMIF dump busy register log
+ */
+static int proc_dump_pmif_busy_reg_show(struct seq_file *m, void *v)
+{
+ seq_puts(m, "********** PMIF dump busy register**********\n");
+ spmi_dump_pmif_busy_reg();
+ spmi_dump_pmif_busy_reg_d(m);
+
+ return 0;
+}
+
+static int proc_dump_pmif_busy_reg_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, proc_dump_pmif_busy_reg_show, NULL);
+}
+
+static const struct file_operations dump_pmif_busy_reg_proc_fops = {
+ .open = proc_dump_pmif_busy_reg_open,
+ .read = seq_read,
+};
+
+/*
+ * PMIF dump swinf log
+ */
+
+static int proc_dump_pmif_swinf_show(struct seq_file *m, void *v)
+{
+ seq_puts(m, "********** PMIF dump swinf register**********\n");
+ spmi_dump_pmif_swinf_reg();
+ spmi_dump_pmif_swinf_reg_d(m);
+
+ return 0;
+}
+
+static int proc_dump_pmif_swinf_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, proc_dump_pmif_swinf_show, NULL);
+}
+
+static const struct file_operations dump_pmif_swinf_proc_fops = {
+ .open = proc_dump_pmif_swinf_open,
+ .read = seq_read,
+};
+
+/*
+ * PMIF dump all register log
+ */
+static int proc_dump_pmif_all_reg_show(struct seq_file *m, void *v)
+{
+ seq_puts(m, "********** PMIF dump all register**********\n");
+ spmi_dump_pmif_all_reg();
+ spmi_dump_pmif_all_reg_d(m);
+
+ return 0;
+}
+
+static int proc_dump_pmif_all_reg_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, proc_dump_pmif_all_reg_show, NULL);
+}
+
+static const struct file_operations dump_pmif_all_reg_proc_fops = {
+ .open = proc_dump_pmif_all_reg_open,
+ .read = seq_read,
+};
+
+/*
+ * PMIF dump record register log
+ */
+static int proc_dump_pmif_record_reg_show(struct seq_file *m, void *v)
+{
+ seq_puts(m, "********** PMIF dump record register**********\n");
+ seq_puts(m, "*swinf:4=MD,swinf:5:GZ,swinf:6:AP,swinf:7:RSV\n");
+ spmi_dump_pmif_record_reg();
+ spmi_dump_pmif_record_reg_d(m);
+
+ return 0;
+}
+
+static int proc_dump_pmif_record_reg_open(struct inode *inode,
+ struct file *file)
+{
+ return single_open(file, proc_dump_pmif_record_reg_show, NULL);
+}
+
+static const struct file_operations dump_pmif_record_reg_proc_fops = {
+ .open = proc_dump_pmif_record_reg_open,
+ .read = seq_read,
+};
+
+/*
+ * SPMIMST dump all register log
+ */
+static int proc_dump_spmimst_all_reg_show(struct seq_file *m, void *v)
+{
+ seq_puts(m, "********** SPMIMST dump all register**********\n");
+ spmi_dump_spmimst_all_reg();
+ spmi_dump_spmimst_all_reg_d(m);
+
+ return 0;
+}
+
+static int proc_dump_spmimst_all_reg_open(struct inode *inode,
+ struct file *file)
+{
+ return single_open(file, proc_dump_spmimst_all_reg_show, NULL);
+}
+
+static const struct file_operations dump_spmimst_all_reg_proc_fops = {
+ .open = proc_dump_spmimst_all_reg_open,
+ .read = seq_read,
+};
+
+static u32 gpmif_of;
+static u32 gpmif_val;
+static ssize_t pmif_access_show(struct device_driver *ddri, char *buf)
+{
+ if (buf == NULL) {
+ pr_notice("[%s] *buf is NULL!\n", __func__);
+ return -EINVAL;
+ }
+ sprintf(buf, "[%s] [0x%x]=0x%x\n", __func__, gpmif_of, gpmif_val);
+
+ return strlen(buf);
+}
+static ssize_t pmif_access_store(struct device_driver *ddri,
+ const char *buf, size_t count)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl);
+ int ret = 0;
+ u32 offset = 0;
+ u32 value = 0;
+
+ pr_info("[%s]\n", __func__);
+ if (buf != NULL && count != 0) {
+ pr_info("[%s] size is %d, buf is %s\n",
+ __func__, (int)count, buf);
+
+ if (strlen(buf) < 3) {
+ pr_notice("%s() Invalid input!!\n", __func__);
+ return -EINVAL;
+ }
+
+ ret = sscanf(buf, "0x%x 0x%x", &offset, &value);
+ if (ret < 0)
+ return ret;
+
+ if (value) {
+ if (offset > arb->dbgregs[PMIF_SWINF_3_STA]) {
+ pr_notice("%s() Illegal offset[0x%x]!!\n",
+ __func__, offset);
+ } else {
+ pr_info("%s() set offset[0x%x]=0x%x\n",
+ __func__, offset, value);
+ writel(value, arb->base + offset);
+ }
+ }
+
+ gpmif_of = offset;
+ gpmif_val = readl(arb->base + offset);
+ }
+ return count;
+}
+static u32 gspmi_of;
+static u32 gspmi_val;
+static ssize_t spmi_access_show(struct device_driver *ddri, char *buf)
+{
+ if (buf == NULL) {
+ pr_notice("[%s] *buf is NULL!\n", __func__);
+ return -EINVAL;
+ }
+ sprintf(buf, "[%s] [0x%x]=0x%x\n", __func__, gspmi_of, gspmi_val);
+
+ return strlen(buf);
+}
+static ssize_t spmi_access_store(struct device_driver *ddri,
+ const char *buf, size_t count)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl);
+ int ret = 0;
+ u32 offset = 0;
+ u32 value = 0;
+
+ pr_info("[%s]\n", __func__);
+ if (buf != NULL && count != 0) {
+ pr_info("[%s] size is %d, buf is %s\n",
+ __func__, (int)count, buf);
+
+ if (strlen(buf) < 3) {
+ pr_notice("%s() Invalid input!!\n", __func__);
+ return -EINVAL;
+ }
+
+ ret = sscanf(buf, "0x%x 0x%x", &offset, &value);
+ if (ret < 0)
+ return ret;
+
+ if (value) {
+ if (offset > arb->spmimst_regs[SPMI_MST_DBG]) {
+ pr_notice("%s() Illegal offset[0x%x]!!\n",
+ __func__, offset);
+ } else {
+ pr_info("%s() set offset[0x%x]=0x%x\n",
+ __func__, offset, value);
+ writel(value, arb->spmimst_base + offset);
+ }
+ }
+
+ gspmi_of = offset;
+ gspmi_val = readl(arb->spmimst_base + offset);
+ }
+ return count;
+}
+static DRIVER_ATTR_RW(pmif_access);
+static DRIVER_ATTR_RW(spmi_access);
+
+static struct driver_attribute *spmi_pmif_attr_list[] = {
+ &driver_attr_pmif_access,
+ &driver_attr_spmi_access,
+};
+
+int spmi_pmif_create_attr(struct device_driver *driver)
+{
+ int idx, err;
+ int num = ARRAY_SIZE(spmi_pmif_attr_list);
+ struct dentry *mtk_spmi_dir;
+
+ mtk_spmi_dir = debugfs_create_dir("mtk_spmi", NULL);
+ if (!mtk_spmi_dir) {
+ pr_notice("fail to mkdir /sys/kernel/debug/mtk_spmi\n");
+ return -ENOMEM;
+ }
+
+ /*--/sys/kernel/debug/mtk_spmi--*/
+ debugfs_create_file("dump_pmif_busy_reg", 0644,
+ mtk_spmi_dir, NULL,
+ &dump_pmif_busy_reg_proc_fops);
+ debugfs_create_file("dump_pmif_swinf", 0644,
+ mtk_spmi_dir, NULL,
+ &dump_pmif_swinf_proc_fops);
+ debugfs_create_file("dump_pmif_all_reg", 0644,
+ mtk_spmi_dir, NULL,
+ &dump_pmif_all_reg_proc_fops);
+ debugfs_create_file("dump_pmif_record_reg", 0644,
+ mtk_spmi_dir, NULL,
+ &dump_pmif_record_reg_proc_fops);
+ debugfs_create_file("dump_spmimst_all_reg", 0644,
+ mtk_spmi_dir, NULL,
+ &dump_spmimst_all_reg_proc_fops);
+
+ if (driver == NULL)
+ return -EINVAL;
+
+ /*--/sys/devices/platform/10027000.spmi/driver--*/
+ for (idx = 0; idx < num; idx++) {
+ err = driver_create_file(driver, spmi_pmif_attr_list[idx]);
+ if (err) {
+ pr_notice("%s() driver_create_file %s err:%d\n",
+ __func__, spmi_pmif_attr_list[idx]->attr.name, err);
+ break;
+ }
+ }
+ return err;
+}
+
+int spmi_pmif_dbg_init(struct spmi_controller *ctrl)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+
+ dbg_ctrl = ctrl;
+ wp = d_log_buf;
+ if (of_device_is_compatible(ctrl->dev.parent->of_node,
+ "mediatek,mt6885-pmif")) {
+ arb->dbgregs = mt6885_pmif_dbg_regs;
+ arb->dbgver = 1;
+ } else if (of_device_is_compatible(ctrl->dev.parent->of_node,
+ "mediatek,mt6873-pmif")) {
+ arb->dbgregs = mt6873_pmif_dbg_regs;
+ arb->dbgver = 1;
+ } else if (of_device_is_compatible(ctrl->dev.parent->of_node,
+ "mediatek,mt6880-pmif-m")) {
+ arb->dbgregs = mt6880_pmif_dbg_regs;
+ arb->dbgver = 2;
+ } else if (of_device_is_compatible(ctrl->dev.parent->of_node,
+ "mediatek,mt6880-pmif-p")) {
+ arb->dbgregs = mt6880_pmif_dbg_regs;
+ arb->dbgver = 2;
+ }
+
+ return 0;
+}
diff --git a/src/kernel/linux/v4.19/drivers/spmi/mtk-pmif.c b/src/kernel/linux/v4.19/drivers/spmi/mtk-pmif.c
new file mode 100644
index 0000000..b254a88
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/spmi/mtk-pmif.c
@@ -0,0 +1,2007 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Argus Lin <argus.lin@mediatek.com>
+ */
+/* #define DEBUG */
+
+#include <dt-bindings/spmi/spmi.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_wakeup.h>
+#include <linux/pmif.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/sched/clock.h>
+#include <linux/slab.h>
+#include <linux/spmi.h>
+#include <mt-plat/aee.h>
+
+#include "spmi_sw.h"
+
+/*
+ * marco
+ */
+#define PMIF_TIMEOUT 1
+#define PMIF_BRINGUP 0
+
+/* macro for PMIF SWINF FSM */
+#define PMIF_SWINF_FSM_IDLE 0x00
+#define PMIF_SWINF_FSM_REQ 0x02
+#define PMIF_SWINF_FSM_WFDLE 0x04
+#define PMIF_SWINF_FSM_WFVLDCLR 0x06
+#define PMIF_SWINF_INIT_DONE 0x01
+#define PMIF_SWINF_SYS_IDLE 0x00
+#define PMIF_SWINF_SYS_BUSY 0x01
+
+#define PMIF_GET_SWINF_FSM(x) ((x>>1) & 0x00000007)
+
+#define PMIF_CMD_REG_0 0
+#define PMIF_CMD_REG 1
+#define PMIF_CMD_EXT_REG 2
+#define PMIF_CMD_EXT_REG_LONG 3
+/* 0: SPI, 1: SPMI */
+#define PMIF_PMIFID_SPI 0
+#define PMIF_PMIFID_SPMI0 0
+#define PMIF_PMIFID_SPMI1 1
+#define PMIF_PMIFID_SPMI2 2
+#define PMIF_PMIFID_SPMI3 3
+
+enum pmif_regs {
+ PMIF_INIT_DONE,
+ PMIF_INF_EN,
+ PMIF_ARB_EN,
+ PMIF_CMDISSUE_EN,
+ PMIF_TIMER_CTRL,
+ PMIF_SPI_MODE_CTRL,
+ PMIF_IRQ_EVENT_EN_0,
+ PMIF_IRQ_FLAG_0,
+ PMIF_IRQ_CLR_0,
+ PMIF_IRQ_EVENT_EN_1,
+ PMIF_IRQ_FLAG_1,
+ PMIF_IRQ_CLR_1,
+ PMIF_IRQ_EVENT_EN_2,
+ PMIF_IRQ_FLAG_2,
+ PMIF_IRQ_CLR_2,
+ PMIF_IRQ_EVENT_EN_3,
+ PMIF_IRQ_FLAG_3,
+ PMIF_IRQ_CLR_3,
+ PMIF_IRQ_EVENT_EN_4,
+ PMIF_IRQ_FLAG_4,
+ PMIF_IRQ_CLR_4,
+ PMIF_WDT_EVENT_EN_0,
+ PMIF_WDT_FLAG_0,
+ PMIF_WDT_EVENT_EN_1,
+ PMIF_WDT_FLAG_1,
+ PMIF_SWINF_0_STA,
+ PMIF_SWINF_0_WDATA_31_0,
+ PMIF_SWINF_0_RDATA_31_0,
+ PMIF_SWINF_0_ACC,
+ PMIF_SWINF_0_VLD_CLR,
+ PMIF_SWINF_1_STA,
+ PMIF_SWINF_1_WDATA_31_0,
+ PMIF_SWINF_1_RDATA_31_0,
+ PMIF_SWINF_1_ACC,
+ PMIF_SWINF_1_VLD_CLR,
+ PMIF_SWINF_2_STA,
+ PMIF_SWINF_2_WDATA_31_0,
+ PMIF_SWINF_2_RDATA_31_0,
+ PMIF_SWINF_2_ACC,
+ PMIF_SWINF_2_VLD_CLR,
+ PMIF_SWINF_3_STA,
+ PMIF_SWINF_3_WDATA_31_0,
+ PMIF_SWINF_3_RDATA_31_0,
+ PMIF_SWINF_3_ACC,
+ PMIF_SWINF_3_VLD_CLR,
+};
+
+static const u32 mt6xxx_regs[] = {
+ [PMIF_INIT_DONE] = 0x0000,
+ [PMIF_INF_EN] = 0x0024,
+ [PMIF_ARB_EN] = 0x0150,
+ [PMIF_CMDISSUE_EN] = 0x03B4,
+ [PMIF_TIMER_CTRL] = 0x03E0,
+ [PMIF_SPI_MODE_CTRL] = 0x0400,
+ [PMIF_IRQ_EVENT_EN_0] = 0x0418,
+ [PMIF_IRQ_FLAG_0] = 0x0420,
+ [PMIF_IRQ_CLR_0] = 0x0424,
+ [PMIF_IRQ_EVENT_EN_1] = 0x0428,
+ [PMIF_IRQ_FLAG_1] = 0x0430,
+ [PMIF_IRQ_CLR_1] = 0x0434,
+ [PMIF_IRQ_EVENT_EN_2] = 0x0438,
+ [PMIF_IRQ_FLAG_2] = 0x0440,
+ [PMIF_IRQ_CLR_2] = 0x0444,
+ [PMIF_IRQ_EVENT_EN_3] = 0x0448,
+ [PMIF_IRQ_FLAG_3] = 0x0450,
+ [PMIF_IRQ_CLR_3] = 0x0454,
+ [PMIF_IRQ_EVENT_EN_4] = 0x0458,
+ [PMIF_IRQ_FLAG_4] = 0x0460,
+ [PMIF_IRQ_CLR_4] = 0x0464,
+ [PMIF_WDT_EVENT_EN_0] = 0x046C,
+ [PMIF_WDT_FLAG_0] = 0x0470,
+ [PMIF_WDT_EVENT_EN_1] = 0x0474,
+ [PMIF_WDT_FLAG_1] = 0x0478,
+ [PMIF_SWINF_0_ACC] = 0x0C00,
+ [PMIF_SWINF_0_WDATA_31_0] = 0x0C04,
+ [PMIF_SWINF_0_RDATA_31_0] = 0x0C14,
+ [PMIF_SWINF_0_VLD_CLR] = 0x0C24,
+ [PMIF_SWINF_0_STA] = 0x0C28,
+ [PMIF_SWINF_1_ACC] = 0x0C40,
+ [PMIF_SWINF_1_WDATA_31_0] = 0x0C44,
+ [PMIF_SWINF_1_RDATA_31_0] = 0x0C54,
+ [PMIF_SWINF_1_VLD_CLR] = 0x0C64,
+ [PMIF_SWINF_1_STA] = 0x0C68,
+ [PMIF_SWINF_2_ACC] = 0x0C80,
+ [PMIF_SWINF_2_WDATA_31_0] = 0x0C84,
+ [PMIF_SWINF_2_RDATA_31_0] = 0x0C94,
+ [PMIF_SWINF_2_VLD_CLR] = 0x0CA4,
+ [PMIF_SWINF_2_STA] = 0x0CA8,
+ [PMIF_SWINF_3_ACC] = 0x0CC0,
+ [PMIF_SWINF_3_WDATA_31_0] = 0x0CC4,
+ [PMIF_SWINF_3_RDATA_31_0] = 0x0CD4,
+ [PMIF_SWINF_3_VLD_CLR] = 0x0CE4,
+ [PMIF_SWINF_3_STA] = 0x0CE8,
+};
+
+static const u32 mt6880_regs[] = {
+ [PMIF_INIT_DONE] = 0x0000,
+ [PMIF_INF_EN] = 0x0024,
+ [PMIF_ARB_EN] = 0x0150,
+ [PMIF_CMDISSUE_EN] = 0x03B8,
+ [PMIF_TIMER_CTRL] = 0x03E4,
+ [PMIF_SPI_MODE_CTRL] = 0x0408,
+ [PMIF_IRQ_EVENT_EN_0] = 0x0420,
+ [PMIF_IRQ_FLAG_0] = 0x0428,
+ [PMIF_IRQ_CLR_0] = 0x042C,
+ [PMIF_IRQ_EVENT_EN_1] = 0x0430,
+ [PMIF_IRQ_FLAG_1] = 0x0438,
+ [PMIF_IRQ_CLR_1] = 0x043C,
+ [PMIF_IRQ_EVENT_EN_2] = 0x0440,
+ [PMIF_IRQ_FLAG_2] = 0x0448,
+ [PMIF_IRQ_CLR_2] = 0x044C,
+ [PMIF_IRQ_EVENT_EN_3] = 0x0450,
+ [PMIF_IRQ_FLAG_3] = 0x0458,
+ [PMIF_IRQ_CLR_3] = 0x045C,
+ [PMIF_IRQ_EVENT_EN_4] = 0x0460,
+ [PMIF_IRQ_FLAG_4] = 0x0468,
+ [PMIF_IRQ_CLR_4] = 0x046C,
+ [PMIF_WDT_EVENT_EN_0] = 0x0474,
+ [PMIF_WDT_FLAG_0] = 0x0478,
+ [PMIF_WDT_EVENT_EN_1] = 0x047C,
+ [PMIF_WDT_FLAG_1] = 0x0480,
+ [PMIF_SWINF_0_ACC] = 0x0800,
+ [PMIF_SWINF_0_WDATA_31_0] = 0x0804,
+ [PMIF_SWINF_0_RDATA_31_0] = 0x0814,
+ [PMIF_SWINF_0_VLD_CLR] = 0x0824,
+ [PMIF_SWINF_0_STA] = 0x0828,
+ [PMIF_SWINF_1_ACC] = 0x0840,
+ [PMIF_SWINF_1_WDATA_31_0] = 0x0844,
+ [PMIF_SWINF_1_RDATA_31_0] = 0x0854,
+ [PMIF_SWINF_1_VLD_CLR] = 0x0864,
+ [PMIF_SWINF_1_STA] = 0x0868,
+ [PMIF_SWINF_2_ACC] = 0x0880,
+ [PMIF_SWINF_2_WDATA_31_0] = 0x0884,
+ [PMIF_SWINF_2_RDATA_31_0] = 0x0894,
+ [PMIF_SWINF_2_VLD_CLR] = 0x08A4,
+ [PMIF_SWINF_2_STA] = 0x08A8,
+ [PMIF_SWINF_3_ACC] = 0x08C0,
+ [PMIF_SWINF_3_WDATA_31_0] = 0x08C4,
+ [PMIF_SWINF_3_RDATA_31_0] = 0x08D4,
+ [PMIF_SWINF_3_VLD_CLR] = 0x08E4,
+ [PMIF_SWINF_3_STA] = 0x08E8,
+};
+
+static const u32 mt6853_regs[] = {
+ [PMIF_INIT_DONE] = 0x0000,
+ [PMIF_INF_EN] = 0x0024,
+ [PMIF_ARB_EN] = 0x0150,
+ [PMIF_CMDISSUE_EN] = 0x03B8,
+ [PMIF_TIMER_CTRL] = 0x03E4,
+ [PMIF_SPI_MODE_CTRL] = 0x0408,
+ [PMIF_IRQ_EVENT_EN_0] = 0x0420,
+ [PMIF_IRQ_FLAG_0] = 0x0428,
+ [PMIF_IRQ_CLR_0] = 0x042C,
+ [PMIF_IRQ_EVENT_EN_1] = 0x0430,
+ [PMIF_IRQ_FLAG_1] = 0x0438,
+ [PMIF_IRQ_CLR_1] = 0x043C,
+ [PMIF_IRQ_EVENT_EN_2] = 0x0440,
+ [PMIF_IRQ_FLAG_2] = 0x0448,
+ [PMIF_IRQ_CLR_2] = 0x044C,
+ [PMIF_IRQ_EVENT_EN_3] = 0x0450,
+ [PMIF_IRQ_FLAG_3] = 0x0458,
+ [PMIF_IRQ_CLR_3] = 0x045C,
+ [PMIF_IRQ_EVENT_EN_4] = 0x0460,
+ [PMIF_IRQ_FLAG_4] = 0x0468,
+ [PMIF_IRQ_CLR_4] = 0x046C,
+ [PMIF_WDT_EVENT_EN_0] = 0x0474,
+ [PMIF_WDT_FLAG_0] = 0x0478,
+ [PMIF_WDT_EVENT_EN_1] = 0x047C,
+ [PMIF_WDT_FLAG_1] = 0x0480,
+ [PMIF_SWINF_0_ACC] = 0x0C00,
+ [PMIF_SWINF_0_WDATA_31_0] = 0x0C04,
+ [PMIF_SWINF_0_RDATA_31_0] = 0x0C14,
+ [PMIF_SWINF_0_VLD_CLR] = 0x0C24,
+ [PMIF_SWINF_0_STA] = 0x0C28,
+ [PMIF_SWINF_1_ACC] = 0x0C40,
+ [PMIF_SWINF_1_WDATA_31_0] = 0x0C44,
+ [PMIF_SWINF_1_RDATA_31_0] = 0x0C54,
+ [PMIF_SWINF_1_VLD_CLR] = 0x0C64,
+ [PMIF_SWINF_1_STA] = 0x0C68,
+ [PMIF_SWINF_2_ACC] = 0x0C80,
+ [PMIF_SWINF_2_WDATA_31_0] = 0x0C84,
+ [PMIF_SWINF_2_RDATA_31_0] = 0x0C94,
+ [PMIF_SWINF_2_VLD_CLR] = 0x0CA4,
+ [PMIF_SWINF_2_STA] = 0x0CA8,
+ [PMIF_SWINF_3_ACC] = 0x0CC0,
+ [PMIF_SWINF_3_WDATA_31_0] = 0x0CC4,
+ [PMIF_SWINF_3_RDATA_31_0] = 0x0CD4,
+ [PMIF_SWINF_3_VLD_CLR] = 0x0CE4,
+ [PMIF_SWINF_3_STA] = 0x0CE8,
+};
+
+static const u32 mt6xxx_spmi_regs[] = {
+ [SPMI_OP_ST_CTRL] = 0x0000,
+ [SPMI_GRP_ID_EN] = 0x0004,
+ [SPMI_OP_ST_STA] = 0x0008,
+ [SPMI_SAMPL_CTRL] = 0x000c,
+ [SPMI_REQ_EN] = 0x0010,
+ [SPMI_REC_CTRL] = 0x0040,
+ [SPMI_REC0] = 0x0044,
+ [SPMI_REC1] = 0x0048,
+ [SPMI_REC2] = 0x004c,
+ [SPMI_REC3] = 0x0050,
+ [SPMI_REC4] = 0x0054,
+ [SPMI_MST_DBG] = 0x00fc,
+};
+
+static const u32 mt6880_spmi_regs[] = {
+ [SPMI_OP_ST_CTRL] = 0x0000,
+ [SPMI_GRP_ID_EN] = 0x0004,
+ [SPMI_OP_ST_STA] = 0x0008,
+ [SPMI_SAMPL_CTRL] = 0x000C,
+ [SPMI_REQ_EN] = 0x0010,
+ [SPMI_RCS_CTRL] = 0x0014,
+ [SPMI_SLV_3_0_EINT] = 0x0020,
+ [SPMI_SLV_7_4_EINT] = 0x0024,
+ [SPMI_SLV_B_8_EINT] = 0x0028,
+ [SPMI_SLV_F_C_EINT] = 0x002C,
+ [SPMI_REC_CTRL] = 0x0040,
+ [SPMI_REC0] = 0x0044,
+ [SPMI_REC1] = 0x0048,
+ [SPMI_REC2] = 0x004C,
+ [SPMI_REC3] = 0x0050,
+ [SPMI_REC4] = 0x0054,
+ [SPMI_REC_CMD_DEC] = 0x005C,
+ [SPMI_DEC_DBG] = 0x00F8,
+ [SPMI_MST_DBG] = 0x00FC,
+};
+
+static const u32 mt6853_spmi_regs[] = {
+ [SPMI_OP_ST_CTRL] = 0x0000,
+ [SPMI_GRP_ID_EN] = 0x0004,
+ [SPMI_OP_ST_STA] = 0x0008,
+ [SPMI_SAMPL_CTRL] = 0x000C,
+ [SPMI_REQ_EN] = 0x0010,
+ [SPMI_RCS_CTRL] = 0x0014,
+ [SPMI_SLV_3_0_EINT] = 0x0020,
+ [SPMI_SLV_7_4_EINT] = 0x0024,
+ [SPMI_SLV_B_8_EINT] = 0x0028,
+ [SPMI_SLV_F_C_EINT] = 0x002C,
+ [SPMI_REC_CTRL] = 0x0040,
+ [SPMI_REC0] = 0x0044,
+ [SPMI_REC1] = 0x0048,
+ [SPMI_REC2] = 0x004C,
+ [SPMI_REC3] = 0x0050,
+ [SPMI_REC4] = 0x0054,
+ [SPMI_REC_CMD_DEC] = 0x005C,
+ [SPMI_DEC_DBG] = 0x00F8,
+ [SPMI_MST_DBG] = 0x00FC,
+};
+
+enum {
+ SPMI_OP_ST_BUSY = 1,
+ SPMI_OP_ST_ACK = 0,
+ SPMI_OP_ST_NACK = 1
+};
+
+enum {
+ SPMI_RCS_SR_BIT,
+ SPMI_RCS_A_BIT
+};
+
+enum {
+ SPMI_RCS_MST_W = 1,
+ SPMI_RCS_SLV_W = 3
+};
+
+enum infra_regs {
+ MODULE_SW_CG_0_SET,
+ MODULE_SW_CG_0_CLR,
+ MODULE_SW_CG_2_SET,
+ MODULE_SW_CG_2_CLR,
+ PMICW_CLOCK_CTRL,
+ INFRA_GLOBALCON_RST2_SET,
+ INFRA_GLOBALCON_RST2_CLR,
+};
+
+static const u32 mt6xxx_infra_regs[] = {
+ [MODULE_SW_CG_0_SET] = 0x0080,
+ [MODULE_SW_CG_0_CLR] = 0x0084,
+ [MODULE_SW_CG_2_SET] = 0x00a4,
+ [MODULE_SW_CG_2_CLR] = 0x00a8,
+ [PMICW_CLOCK_CTRL] = 0x0108,
+ [INFRA_GLOBALCON_RST2_SET] = 0x0140,
+ [INFRA_GLOBALCON_RST2_CLR] = 0x0144,
+};
+
+enum topckgen_regs {
+ CLK_CFG_UPDATE,
+ CLK_CFG_UPDATE1,
+ CLK_CFG_UPDATE2,
+ CLK_CFG_3_CLR,
+ CLK_CFG_6,
+ CLK_CFG_6_SET,
+ CLK_CFG_6_CLR,
+ CLK_CFG_8_CLR,
+ CLK_CFG_15,
+ CLK_CFG_15_CLR,
+ CLK_CFG_16,
+ CLK_CFG_16_CLR,
+};
+
+static const u32 mt6xxx_topckgen_regs[] = {
+ [CLK_CFG_UPDATE] = 0x0004,
+ [CLK_CFG_UPDATE1] = 0x0008,
+ [CLK_CFG_UPDATE2] = 0x000c,
+ [CLK_CFG_3_CLR] = 0x0048,
+ [CLK_CFG_6] = 0x0070,
+ [CLK_CFG_6_SET] = 0x0074,
+ [CLK_CFG_6_CLR] = 0x0078,
+ [CLK_CFG_8_CLR] = 0x0098,
+ [CLK_CFG_15] = 0x0100,
+ [CLK_CFG_15_CLR] = 0x0108,
+ [CLK_CFG_16] = 0x0110,
+ [CLK_CFG_16_CLR] = 0x0118,
+};
+
+enum toprgu_regs {
+ WDT_SWSYSRST2,
+};
+
+static const u32 mt6xxx_toprgu_regs[] = {
+ [WDT_SWSYSRST2] = 0x0090,
+};
+
+enum {
+ /* MT6885/MT6873 series */
+ IRQ_PMIC_CMD_ERR_PARITY_ERR = 17,
+ IRQ_PMIF_ACC_VIO = 20,
+ IRQ_PMIC_ACC_VIO = 21,
+ IRQ_LAT_LIMIT_REACHED = 6,
+ IRQ_HW_MONITOR = 7,
+ IRQ_WDT = 8,
+ /* MT6853/MT6880 series */
+ IRQ_PMIF_ACC_VIO_V2 = 19,
+ IRQ_PMIC_ACC_VIO_V2 = 20,
+ IRQ_HW_MONITOR_V2 = 10,
+ IRQ_WDT_V2 = 11,
+};
+
+struct pmif_irq_desc {
+ const char *name;
+ irq_handler_t irq_handler;
+ int irq;
+};
+
+#define PMIF_IRQDESC(name) { #name, pmif_##name##_irq_handler, -1}
+
+/*
+ * pmif internal API declaration
+ */
+int __attribute__((weak)) spmi_pmif_create_attr(struct device_driver *driver);
+int __attribute__((weak)) spmi_pmif_dbg_init(struct spmi_controller *ctrl);
+void __attribute__((weak)) spmi_dump_spmimst_record_reg(struct pmif *arb);
+static int pmif_timeout_ns(struct spmi_controller *ctrl,
+ unsigned long long start_time_ns, unsigned long long timeout_time_ns);
+static void pmif_enable_soft_reset(struct pmif *arb);
+static void pmif_enable_soft_reset_p_v1(struct pmif *arb);
+static void pmif_spmi_enable_clk_set(struct pmif *arb);
+static void pmif_spmi_enable_clk_set_v2(struct pmif *arb);
+static void pmif_spmi_force_normal_mode(struct pmif *arb);
+static void pmif_spmi_enable_swinf(struct pmif *arb,
+ unsigned int chan_no, unsigned int swinf_no);
+static void pmif_spmi_enable_cmdIssue(struct pmif *arb, bool en);
+static void pmif_spmi_enable(struct pmif *arb);
+static void pmif_spmi_enable_m_v1(struct pmif *arb);
+static void pmif_spmi_enable_p_v1(struct pmif *arb);
+static void pmif_spmi_enable_m_v2(struct pmif *arb);
+static void pmif_spmi_enable_p_v2(struct pmif *arb);
+static int is_pmif_spmi_init_done(struct pmif *arb);
+static int pmif_spmi_read_cmd(struct spmi_controller *ctrl,
+ u8 opc, u8 sid, u16 addr, u8 *buf, size_t len);
+static int pmif_spmi_write_cmd(struct spmi_controller *ctrl,
+ u8 opc, u8 sid, u16 addr, const u8 *buf,
+ size_t len);
+static int mtk_spmi_config_master(struct pmif *arb,
+ unsigned int mstid, bool en);
+static int mtk_spmi_config_master_v2(struct pmif *arb,
+ unsigned int mstid, bool en);
+static int mtk_spmi_config_master_m_v1(struct pmif *arb,
+ unsigned int mstid, bool en);
+static int mtk_spmi_config_master_p_v1(struct pmif *arb,
+ unsigned int mstid, bool en);
+static int mtk_spmi_config_master_m_v2(struct pmif *arb,
+ unsigned int mstid, bool en);
+static int mtk_spmi_config_master_p_v2(struct pmif *arb,
+ unsigned int mstid, bool en);
+static int mtk_spmi_cali_rd_clock_polarity(struct pmif *arb);
+static int mtk_spmi_cali_rd_clock_polarity_m_p_v1(struct pmif *arb);
+static int mtk_spmi_cali_rd_clock_polarity_m_p_v2(struct pmif *arb);
+static int mtk_spmi_ctrl_op_st(struct spmi_controller *ctrl, u8 opc, u8 sid);
+static int mtk_spmi_enable_group_id(struct pmif *arb, u8 grpid);
+
+static struct pmif mt6885_pmif_arb = {
+ .base = 0x0,
+ .regs = mt6xxx_regs,
+ .spmimst_base = 0x0,
+ .spmimst_regs = mt6xxx_spmi_regs,
+ .infra_base = 0x0,
+ .infra_regs = mt6xxx_infra_regs,
+ .topckgen_base = 0x0,
+ .topckgen_regs = mt6xxx_topckgen_regs,
+ .toprgu_base = 0x0,
+ .toprgu_regs = mt6xxx_toprgu_regs,
+ .swinf_ch_start = 0,
+ .ap_swinf_no = 0,
+ .write = 0x0,
+ .mstid = SPMI_MASTER_0,
+ .pmifid = PMIF_PMIFID_SPMI0,
+ .spmic = 0x0,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ .pmif_enable_clk_set = pmif_spmi_enable_clk_set,
+ .pmif_force_normal_mode = pmif_spmi_force_normal_mode,
+ .pmif_enable_swinf = pmif_spmi_enable_swinf,
+ .pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
+ .pmif_enable = pmif_spmi_enable,
+ .is_pmif_init_done = is_pmif_spmi_init_done,
+ .pmif_enable_reset = pmif_enable_soft_reset,
+ .pmif_cali_clock = mtk_spmi_cali_rd_clock_polarity,
+ .spmi_config_master = mtk_spmi_config_master,
+};
+
+static struct pmif mt6873_pmif_arb = {
+ .base = 0x0,
+ .regs = mt6xxx_regs,
+ .spmimst_base = 0x0,
+ .spmimst_regs = mt6xxx_spmi_regs,
+ .infra_base = 0x0,
+ .infra_regs = mt6xxx_infra_regs,
+ .topckgen_base = 0x0,
+ .topckgen_regs = mt6xxx_topckgen_regs,
+ .toprgu_base = 0x0,
+ .toprgu_regs = mt6xxx_toprgu_regs,
+ .swinf_ch_start = 0,
+ .ap_swinf_no = 0,
+ .write = 0x0,
+ .mstid = SPMI_MASTER_0,
+ .pmifid = PMIF_PMIFID_SPMI0,
+ .spmic = 0x0,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ .pmif_enable_clk_set = pmif_spmi_enable_clk_set,
+ .pmif_force_normal_mode = pmif_spmi_force_normal_mode,
+ .pmif_enable_swinf = pmif_spmi_enable_swinf,
+ .pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
+ .pmif_enable = pmif_spmi_enable,
+ .is_pmif_init_done = is_pmif_spmi_init_done,
+ .pmif_enable_reset = pmif_enable_soft_reset,
+ .pmif_cali_clock = mtk_spmi_cali_rd_clock_polarity,
+ .spmi_config_master = mtk_spmi_config_master_v2,
+};
+
+static struct pmif mt6853_pmif_m_arb = {
+ .base = 0x0,
+ .regs = mt6853_regs,
+ .spmimst_base = 0x0,
+ .spmimst_regs = mt6853_spmi_regs,
+ .infra_base = 0x0,
+ .infra_regs = mt6xxx_infra_regs,
+ .topckgen_base = 0x0,
+ .topckgen_regs = mt6xxx_topckgen_regs,
+ .toprgu_base = 0x0,
+ .toprgu_regs = mt6xxx_toprgu_regs,
+ .swinf_ch_start = 0,
+ .ap_swinf_no = 0,
+ .write = 0x0,
+ .mstid = SPMI_MASTER_1,
+ .pmifid = PMIF_PMIFID_SPMI1,
+ .spmic = 0x0,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ .pmif_enable_clk_set = pmif_spmi_enable_clk_set,
+ .pmif_force_normal_mode = pmif_spmi_force_normal_mode,
+ .pmif_enable_swinf = pmif_spmi_enable_swinf,
+ .pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
+ .pmif_enable = pmif_spmi_enable_m_v1,
+ .is_pmif_init_done = is_pmif_spmi_init_done,
+ .pmif_enable_reset = pmif_enable_soft_reset,
+ .pmif_cali_clock = mtk_spmi_cali_rd_clock_polarity_m_p_v1,
+ .spmi_config_master = mtk_spmi_config_master_m_v1,
+};
+
+static struct pmif mt6853_pmif_p_arb = {
+ .base = 0x0,
+ .regs = mt6853_regs,
+ .spmimst_base = 0x0,
+ .spmimst_regs = mt6853_spmi_regs,
+ .infra_base = 0x0,
+ .infra_regs = mt6xxx_infra_regs,
+ .topckgen_base = 0x0,
+ .topckgen_regs = mt6xxx_topckgen_regs,
+ .toprgu_base = 0x0,
+ .toprgu_regs = mt6xxx_toprgu_regs,
+ .swinf_ch_start = 0,
+ .ap_swinf_no = 0,
+ .write = 0x0,
+ .mstid = SPMI_MASTER_1,
+ .pmifid = PMIF_PMIFID_SPMI2,
+ .spmic = 0x0,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ .pmif_enable_clk_set = pmif_spmi_enable_clk_set,
+ .pmif_force_normal_mode = pmif_spmi_force_normal_mode,
+ .pmif_enable_swinf = pmif_spmi_enable_swinf,
+ .pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
+ .pmif_enable = pmif_spmi_enable_p_v1,
+ .is_pmif_init_done = is_pmif_spmi_init_done,
+ .pmif_enable_reset = pmif_enable_soft_reset_p_v1,
+ .pmif_cali_clock = mtk_spmi_cali_rd_clock_polarity_m_p_v1,
+ .spmi_config_master = mtk_spmi_config_master_p_v1,
+};
+
+static struct pmif mt6880_pmif_m_arb = {
+ .base = 0x0,
+ .regs = mt6880_regs,
+ .spmimst_base = 0x0,
+ .spmimst_regs = mt6880_spmi_regs,
+ .infra_base = 0x0,
+ .infra_regs = mt6xxx_infra_regs,
+ .topckgen_base = 0x0,
+ .topckgen_regs = mt6xxx_topckgen_regs,
+ .toprgu_base = 0x0,
+ .toprgu_regs = mt6xxx_toprgu_regs,
+ .swinf_ch_start = 0,
+ .ap_swinf_no = 0,
+ .write = 0x0,
+ .mstid = SPMI_MASTER_1,
+ .pmifid = PMIF_PMIFID_SPMI1,
+ .spmic = 0x0,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ .pmif_enable_clk_set = pmif_spmi_enable_clk_set_v2,
+ .pmif_force_normal_mode = pmif_spmi_force_normal_mode,
+ .pmif_enable_swinf = pmif_spmi_enable_swinf,
+ .pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
+ .pmif_enable = pmif_spmi_enable_m_v2,
+ .is_pmif_init_done = is_pmif_spmi_init_done,
+ .pmif_enable_reset = pmif_enable_soft_reset,
+ .pmif_cali_clock = mtk_spmi_cali_rd_clock_polarity_m_p_v2,
+ .spmi_config_master = mtk_spmi_config_master_m_v2,
+};
+
+static struct pmif mt6880_pmif_p_arb = {
+ .base = 0x0,
+ .regs = mt6880_regs,
+ .spmimst_base = 0x0,
+ .spmimst_regs = mt6880_spmi_regs,
+ .infra_base = 0x0,
+ .infra_regs = mt6xxx_infra_regs,
+ .topckgen_base = 0x0,
+ .topckgen_regs = mt6xxx_topckgen_regs,
+ .toprgu_base = 0x0,
+ .toprgu_regs = mt6xxx_toprgu_regs,
+ .swinf_ch_start = 0,
+ .ap_swinf_no = 0,
+ .write = 0x0,
+ .mstid = SPMI_MASTER_1,
+ .pmifid = PMIF_PMIFID_SPMI2,
+ .spmic = 0x0,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ .pmif_enable_clk_set = pmif_spmi_enable_clk_set_v2,
+ .pmif_force_normal_mode = pmif_spmi_force_normal_mode,
+ .pmif_enable_swinf = pmif_spmi_enable_swinf,
+ .pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
+ .pmif_enable = pmif_spmi_enable_p_v2,
+ .is_pmif_init_done = is_pmif_spmi_init_done,
+ .pmif_enable_reset = pmif_enable_soft_reset_p_v1,
+ .pmif_cali_clock = mtk_spmi_cali_rd_clock_polarity_m_p_v2,
+ .spmi_config_master = mtk_spmi_config_master_p_v2,
+};
+
+static const struct of_device_id pmif_match_table[] = {
+ {
+ .compatible = "mediatek,mt6885-pmif",
+ .data = &mt6885_pmif_arb,
+ }, {
+ .compatible = "mediatek,mt6873-pmif",
+ .data = &mt6873_pmif_arb,
+ }, {
+ .compatible = "mediatek,mt6853-pmif-m",
+ .data = &mt6853_pmif_m_arb,
+ }, {
+ .compatible = "mediatek,mt6853-pmif-p",
+ .data = &mt6853_pmif_p_arb,
+ }, {
+ .compatible = "mediatek,mt6880-pmif-m",
+ .data = &mt6880_pmif_m_arb,
+ }, {
+ .compatible = "mediatek,mt6880-pmif-p",
+ .data = &mt6880_pmif_p_arb,
+ }, {
+ /* sentinel */
+ },
+};
+MODULE_DEVICE_TABLE(of, pmif_match_table);
+static struct platform_driver pmif_driver;
+
+/*
+ * pmif timeout
+ */
+#if PMIF_TIMEOUT
+static int pmif_timeout_ns(struct spmi_controller *ctrl,
+ unsigned long long start_time_ns, unsigned long long timeout_time_ns)
+{
+ unsigned long long cur_time = 0;
+ unsigned long long elapse_time = 0;
+
+ /* get current tick */
+ cur_time = sched_clock(); /* ns */
+
+ /* avoid timer over flow exiting in FPGA env */
+ if (cur_time < start_time_ns)
+ start_time_ns = cur_time;
+
+ elapse_time = cur_time - start_time_ns;
+
+ /* check if timeout */
+ if (timeout_time_ns <= elapse_time) {
+ dev_notice(&ctrl->dev,
+ "[PMIF] Timeout start time: %lld\n", start_time_ns);
+ dev_notice(&ctrl->dev,
+ "[PMIF] Timeout cur time: %lld\n", cur_time);
+ dev_notice(&ctrl->dev,
+ "[PMIF] Timeout elapse time: %lld\n", elapse_time);
+ dev_notice(&ctrl->dev,
+ "[PMIF] Timeout set timeout: %lld\n", timeout_time_ns);
+ return 1;
+ }
+ return 0;
+}
+#else
+static int pmif_timeout_ns(struct spmi_controller *ctrl,
+ unsigned long long start_time_ns, unsigned long long timeout_time_ns)
+{
+ return 0;
+}
+
+#endif
+/*
+ * pmif define for FSM
+ */
+static inline bool pmif_is_fsm_idle(struct pmif *arb)
+{
+ u32 offset = 0, reg_rdata = 0;
+
+ offset = arb->regs[PMIF_SWINF_0_STA] + (0x40 * arb->ap_swinf_no);
+ reg_rdata = readl(arb->base + offset);
+ return PMIF_GET_SWINF_FSM(reg_rdata) == PMIF_SWINF_FSM_IDLE;
+}
+
+static inline bool pmif_is_fsm_vldclr(struct pmif *arb)
+{
+ u32 offset = 0, reg_rdata = 0;
+
+ offset = arb->regs[PMIF_SWINF_0_STA] + (0x40 * arb->ap_swinf_no);
+ reg_rdata = readl(arb->base + offset);
+ return PMIF_GET_SWINF_FSM(reg_rdata) == PMIF_SWINF_FSM_WFVLDCLR;
+}
+static inline void pmif_leave_fsm_vldclr(struct pmif *arb)
+{
+ u32 offset = 0;
+
+ offset = arb->regs[PMIF_SWINF_0_VLD_CLR] + (0x40 * arb->ap_swinf_no);
+ if (pmif_is_fsm_vldclr(arb))
+ writel(0x1, arb->base + offset);
+}
+
+static int pmif_wait_for_state(struct spmi_controller *ctrl,
+ bool (*fp)(struct pmif *))
+{
+ struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+ unsigned long long start_time_ns = 0, timeout_ns = 0;
+
+ start_time_ns = sched_clock();
+ timeout_ns = 10000 * 1000; /* 10000us */
+
+ do {
+ if (pmif_timeout_ns(ctrl, start_time_ns, timeout_ns)) {
+ if (fp(arb)) {
+ return 0;
+ } else if (fp(arb) == 0) {
+ dev_notice(&ctrl->dev, "[PMIF] FSM Timeout\n");
+ return -ETIMEDOUT;
+ }
+ }
+ if (fp(arb))
+ return 0;
+ } while (1);
+}
+
+/*
+ * Function : pmif_readl()
+ * Description : mtk pmif controller read api
+ * Parameter :
+ * Return :
+ */
+static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
+{
+ return readl(arb->base + arb->regs[reg]);
+}
+
+/*
+ * Function : pmif_writel()
+ * Description : mtk pmif controller write api
+ * Parameter :
+ * Return :
+ */
+static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
+{
+ writel(val, arb->base + arb->regs[reg]);
+}
+/*
+ * Function : mtk_spmi_readl()
+ * Description : mtk spmi controller read api
+ * Parameter :
+ * Return :
+ */
+u32 mtk_spmi_readl(struct pmif *arb, enum spmi_regs reg)
+{
+ return readl(arb->spmimst_base + arb->spmimst_regs[reg]);
+}
+
+/*
+ * Function : mtk_spmi_writel()
+ * Description : mtk spmi controller write api
+ * Parameter :
+ * Return :
+ */
+void mtk_spmi_writel(struct pmif *arb, u32 val,
+ enum spmi_regs reg)
+{
+ writel(val, arb->spmimst_base + arb->spmimst_regs[reg]);
+}
+
+static void pmif_enable_soft_reset(struct pmif *arb)
+{
+ writel(0x1 << 14,
+ arb->infra_base + arb->infra_regs[INFRA_GLOBALCON_RST2_SET]);
+ writel(0x1 << 14,
+ arb->infra_base + arb->infra_regs[INFRA_GLOBALCON_RST2_CLR]);
+}
+
+static void pmif_enable_soft_reset_p_v1(struct pmif *arb)
+{
+ writel(0x1,
+ arb->infra_base + arb->infra_regs[INFRA_GLOBALCON_RST2_SET]);
+ writel(0x1,
+ arb->infra_base + arb->infra_regs[INFRA_GLOBALCON_RST2_CLR]);
+}
+
+static void pmif_spmi_enable_clk_set(struct pmif *arb)
+{
+ /* sys_ck cg enable, turn off clock */
+ writel(0x0000000f,
+ arb->infra_base + arb->infra_regs[MODULE_SW_CG_0_SET]);
+
+ writel((0x1 << 15) | (0x1 << 12) | (0x7 << 8),
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_8_CLR]);
+ writel(0x1 << 2,
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE1]);
+
+ /* toggle SPMI sw reset */
+ arb->pmif_enable_reset(arb);
+
+ /* sys_ck cg enable, turn on clock */
+ writel(0x0000000f,
+ arb->infra_base + arb->infra_regs[MODULE_SW_CG_0_CLR]);
+}
+
+static void pmif_spmi_enable_clk_set_v2(struct pmif *arb)
+{
+ /* sys_ck cg enable, turn off clock */
+ writel(0x0000000f,
+ arb->infra_base + arb->infra_regs[MODULE_SW_CG_0_SET]);
+
+#if !defined(CONFIG_FPGA_EARLY_PORTING)
+ writel((0x1 << 31) | (0x1 << 28) | (0x7 << 24),
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_3_CLR]);
+ writel(0x1 << 15,
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE]);
+#endif
+
+ /* toggle SPMI sw reset */
+ arb->pmif_enable_reset(arb);
+
+ /* sys_ck cg enable, turn on clock */
+ writel(0x0000000f,
+ arb->infra_base + arb->infra_regs[MODULE_SW_CG_0_CLR]);
+}
+
+static void pmif_spmi_force_normal_mode(struct pmif *arb)
+{
+ /* Force SPMI in normal mode. */
+ pmif_writel(arb, pmif_readl(arb, PMIF_SPI_MODE_CTRL) & (~(0x3 << 9)),
+ PMIF_SPI_MODE_CTRL);
+ pmif_writel(arb, pmif_readl(arb, PMIF_SPI_MODE_CTRL) | (0x1 << 9),
+ PMIF_SPI_MODE_CTRL);
+#if defined(CONFIG_FPGA_EARLY_PORTING)
+ pmif_writel(arb, pmif_readl(arb, PMIF_SPI_MODE_CTRL) & (~(0x1 << 13)),
+ PMIF_SPI_MODE_CTRL);
+#endif
+}
+
+static void pmif_spmi_enable_swinf(struct pmif *arb, unsigned int chan_no,
+ unsigned int swinf_no)
+{
+ /* Enable swinf */
+ pmif_writel(arb, 0x1 << (chan_no + swinf_no), PMIF_INF_EN);
+
+ /* Enable arbitration */
+ pmif_writel(arb, 0x1 << (chan_no + swinf_no), PMIF_ARB_EN);
+
+}
+
+static void pmif_spmi_enable_cmdIssue(struct pmif *arb, bool en)
+{
+ /* Enable cmdIssue */
+ pmif_writel(arb, en, PMIF_CMDISSUE_EN);
+
+}
+
+static void pmif_spmi_enable(struct pmif *arb)
+{
+ pmif_writel(arb, 0x2F7, PMIF_INF_EN);
+ pmif_writel(arb, 0x2F7, PMIF_ARB_EN);
+ pmif_writel(arb, 0x3, PMIF_TIMER_CTRL);
+ pmif_writel(arb, 0x1, PMIF_INIT_DONE);
+}
+
+static void pmif_spmi_enable_m_v1(struct pmif *arb)
+{
+ pmif_writel(arb, 0x2F6, PMIF_INF_EN);
+ pmif_writel(arb, 0x2F6, PMIF_ARB_EN);
+ pmif_writel(arb, 0x3, PMIF_TIMER_CTRL);
+ pmif_writel(arb, 0x1, PMIF_INIT_DONE);
+}
+
+static void pmif_spmi_enable_p_v1(struct pmif *arb)
+{
+ pmif_writel(arb, 0xF1, PMIF_INF_EN);
+ pmif_writel(arb, 0xF1, PMIF_ARB_EN);
+ pmif_writel(arb, 0x3, PMIF_TIMER_CTRL);
+ pmif_writel(arb, 0x1, PMIF_INIT_DONE);
+}
+
+static void pmif_spmi_enable_m_v2(struct pmif *arb)
+{
+ pmif_writel(arb, 0x1FFF, PMIF_INF_EN);
+ pmif_writel(arb, 0x1FFF, PMIF_ARB_EN);
+ pmif_writel(arb, 0x3, PMIF_TIMER_CTRL);
+ pmif_writel(arb, 0x1, PMIF_INIT_DONE);
+}
+
+static void pmif_spmi_enable_p_v2(struct pmif *arb)
+{
+ pmif_writel(arb, 0x1FFF, PMIF_INF_EN);
+ pmif_writel(arb, 0x1FFF, PMIF_ARB_EN);
+ pmif_writel(arb, 0x3, PMIF_TIMER_CTRL);
+ pmif_writel(arb, 0x1, PMIF_INIT_DONE);
+}
+
+static int mtk_spmi_ctrl_op_st(struct spmi_controller *ctrl,
+ u8 opc, u8 sid)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+ u32 rdata = 0x0;
+ u8 cmd = 0;
+
+ /* Check the opcode */
+ if (opc == SPMI_CMD_RESET)
+ cmd = 0;
+ else if (opc == SPMI_CMD_SLEEP)
+ cmd = 1;
+ else if (opc == SPMI_CMD_SHUTDOWN)
+ cmd = 2;
+ else if (opc == SPMI_CMD_WAKEUP)
+ cmd = 3;
+
+ mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
+
+ rdata = mtk_spmi_readl(arb, SPMI_OP_ST_CTRL);
+ pr_notice("[SPMIMST]:pmif_ctrl_op_st 0x%x\r\n", rdata);
+
+ do {
+ rdata = mtk_spmi_readl(arb, SPMI_OP_ST_STA);
+ pr_notice("[SPMIMST]:pmif_ctrl_op_st 0x%x\r\n", rdata);
+
+ if (((rdata >> 0x1) & SPMI_OP_ST_NACK) == SPMI_OP_ST_NACK) {
+ spmi_dump_spmimst_record_reg(arb);
+ break;
+ }
+ } while ((rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY);
+
+ return 0;
+}
+
+/* Non-data command */
+static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
+{
+ return mtk_spmi_ctrl_op_st(ctrl, opc, sid);
+}
+
+static int mtk_spmi_enable_group_id(struct pmif *arb, u8 grpid)
+{
+ mtk_spmi_writel(arb, 0x1 << grpid, SPMI_GRP_ID_EN);
+
+ return 0;
+}
+
+static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
+ u16 addr, u8 *buf, size_t len)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+ int ret = 0, write = 0x0;
+ u32 offset = 0, data = 0;
+ u8 bc = len - 1;
+ unsigned long flags;
+
+ /* Check for argument validation. */
+ if ((arb->ap_swinf_no & ~(0x3)) != 0x0)
+ return -EINVAL;
+
+ if ((arb->pmifid & ~(0x3)) != 0x0)
+ return -EINVAL;
+
+ if ((sid & ~(0xf)) != 0x0)
+ return -EINVAL;
+
+ /* Check the opcode */
+ if (opc >= 0x60 && opc <= 0x7F)
+ opc = PMIF_CMD_REG;
+ else if (opc >= 0x20 && opc <= 0x2F)
+ opc = PMIF_CMD_EXT_REG_LONG; /* wk1 opc = PMIF_CMD_EXT_REG; */
+ else if (opc >= 0x38 && opc <= 0x3F)
+ opc = PMIF_CMD_EXT_REG_LONG;
+ else
+ return -EINVAL;
+
+ raw_spin_lock_irqsave(&arb->lock, flags);
+ /* Wait for Software Interface FSM state to be IDLE. */
+ ret = pmif_wait_for_state(ctrl, pmif_is_fsm_idle);
+ if (ret) {
+ pmif_leave_fsm_vldclr(arb);
+ raw_spin_unlock_irqrestore(&arb->lock, flags);
+ return ret;
+ }
+ /* Send the command. */
+ offset = arb->regs[PMIF_SWINF_0_ACC] + (0x40 * arb->ap_swinf_no);
+ writel((opc << 30) | (write << 29) | (sid << 24) | (bc << 16) | addr,
+ arb->base + offset);
+
+ /* Wait for Software Interface FSM state to be WFVLDCLR,
+ *
+ * read the data and clear the valid flag.
+ */
+ if (write == 0) {
+ ret = pmif_wait_for_state(ctrl, pmif_is_fsm_vldclr);
+ if (ret) {
+ raw_spin_unlock_irqrestore(&arb->lock, flags);
+ return ret;
+ }
+ offset =
+ arb->regs[PMIF_SWINF_0_RDATA_31_0] + (0x40 * arb->ap_swinf_no);
+
+ data = readl(arb->base + offset);
+ memcpy(buf, &data, (bc & 3) + 1);
+ offset =
+ arb->regs[PMIF_SWINF_0_VLD_CLR] + (0x40 * arb->ap_swinf_no);
+
+ writel(0x1, arb->base + offset);
+ }
+
+ raw_spin_unlock_irqrestore(&arb->lock, flags);
+
+ return 0x0;
+}
+
+static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
+ u16 addr, const u8 *buf, size_t len)
+{
+ struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+ int ret = 0, write = 0x1;
+ u32 offset = 0, data = 0;
+ u8 bc = len - 1;
+ unsigned long flags = 0;
+
+ /* Check for argument validation. */
+ if ((arb->ap_swinf_no & ~(0x3)) != 0x0)
+ return -EINVAL;
+
+ if ((arb->pmifid & ~(0x3)) != 0x0)
+ return -EINVAL;
+
+ if ((sid & ~(0xf)) != 0x0)
+ return -EINVAL;
+
+ /* Check the opcode */
+ if (opc >= 0x40 && opc <= 0x5F)
+ opc = PMIF_CMD_REG;
+ else if (opc <= 0x0F)
+ opc = PMIF_CMD_EXT_REG_LONG; /* wk1 opc = PMIF_CMD_EXT_REG; */
+ else if (opc >= 0x30 && opc <= 0x37)
+ opc = PMIF_CMD_EXT_REG_LONG;
+ else if (opc >= 0x80)
+ opc = PMIF_CMD_REG_0;
+ else
+ return -EINVAL;
+
+ raw_spin_lock_irqsave(&arb->lock, flags);
+
+ /* Wait for Software Interface FSM state to be IDLE. */
+ ret = pmif_wait_for_state(ctrl, pmif_is_fsm_idle);
+ if (ret) {
+ pmif_leave_fsm_vldclr(arb);
+ raw_spin_unlock_irqrestore(&arb->lock, flags);
+ return ret;
+ }
+ /* Set the write data. */
+ offset = arb->regs[PMIF_SWINF_0_WDATA_31_0] + (0x40 * arb->ap_swinf_no);
+ if (write == 1) {
+ memcpy(&data, buf, (bc & 3) + 1);
+ writel(data, arb->base + offset);
+ }
+
+ /* Send the command. */
+ offset = arb->regs[PMIF_SWINF_0_ACC] + (0x40 * arb->ap_swinf_no);
+ writel((opc << 30) | (write << 29) | (sid << 24) | (bc << 16) | addr,
+ arb->base + offset);
+ raw_spin_unlock_irqrestore(&arb->lock, flags);
+
+ return 0x0;
+}
+
+int is_pmif_spmi_init_done(struct pmif *arb)
+{
+ return pmif_readl(arb, PMIF_INIT_DONE) & 0x1;
+}
+
+static int mtk_spmi_config_master(struct pmif *arb,
+ unsigned int mstid, bool en)
+{
+ /* Software reset */
+ writel(0x85 << 24 | 0x1 << 4,
+ arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
+
+ writel(0x7 | (0x1 << 4) | (0x1 << 7),
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_16_CLR]);
+ writel(0x1 << 2,
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE2]);
+
+ /* Software reset */
+ writel(0x85 << 24,
+ arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
+
+ /* Enable SPMI */
+ mtk_spmi_writel(arb, en, SPMI_REQ_EN);
+
+ return 0;
+}
+
+static int mtk_spmi_config_master_v2(struct pmif *arb,
+ unsigned int mstid, bool en)
+{
+ /* Software reset */
+ writel(0x85 << 24 | 0x1 << 4,
+ arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
+
+ writel((0x7 << 8) | (0x1 << 12) | (0x1 << 15),
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_15_CLR]);
+ writel(0x1 << 30,
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE2]);
+
+ /* Software reset */
+ writel(0x85 << 24,
+ arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
+
+ /* Enable SPMI */
+ mtk_spmi_writel(arb, en, SPMI_REQ_EN);
+
+ return 0;
+}
+
+static int mtk_spmi_config_master_m_v1(struct pmif *arb,
+ unsigned int mstid, bool en)
+{
+ /* Software reset */
+ writel(0x85 << 24 | 0x3 << 3,
+ arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
+
+ writel((0x7 << 8) | (0x1 << 12) | (0x1 << 15),
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_15_CLR]);
+ writel(0x1 << 30,
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE2]);
+
+ /* Software reset */
+ writel(0x85 << 24,
+ arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
+
+ /* Enable master rcs */
+ mtk_spmi_writel(arb, 0x14 | arb->mstid, SPMI_RCS_CTRL);
+ /* Enable SPMI */
+ mtk_spmi_writel(arb, en, SPMI_REQ_EN);
+
+ return 0;
+}
+
+static int mtk_spmi_config_master_p_v1(struct pmif *arb,
+ unsigned int mstid, bool en)
+{
+ /* Enable master rcs */
+ mtk_spmi_writel(arb, 0x14 | arb->mstid, SPMI_RCS_CTRL);
+ /* Enable SPMI */
+ mtk_spmi_writel(arb, en, SPMI_REQ_EN);
+
+ return 0;
+}
+
+static int mtk_spmi_config_master_m_v2(struct pmif *arb,
+ unsigned int mstid, bool en)
+{
+ /* Software reset */
+ writel(0x85 << 24 | 0x1 << 4,
+ arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
+
+#if !defined(CONFIG_FPGA_EARLY_PORTING)
+ writel((0x7 << 16) | (0x1 << 20) | (0x1 << 23),
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_6_CLR]);
+ writel(0x3 << 16,
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_6_SET]);
+ writel(0x1 << 26,
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE]);
+#endif
+
+ /* Software reset */
+ writel(0x85 << 24,
+ arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
+
+ /* Enable master rcs */
+ mtk_spmi_writel(arb, 0x14 | arb->mstid, SPMI_RCS_CTRL);
+ /* Enable SPMI */
+ mtk_spmi_writel(arb, en, SPMI_REQ_EN);
+
+ return 0;
+}
+
+static int mtk_spmi_config_master_p_v2(struct pmif *arb,
+ unsigned int mstid, bool en)
+{
+ /* no need to reset SPMI master again */
+
+#if !defined(CONFIG_FPGA_EARLY_PORTING)
+ writel((0xF << 24) | (0x1 << 28) | (0x1 << 31),
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_6_CLR]);
+ writel(0x7 << 24,
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_6_SET]);
+ writel(0x1 << 27,
+ arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE]);
+#endif
+ /* Enable SPMI */
+ mtk_spmi_writel(arb, en, SPMI_REQ_EN);
+
+ return 0;
+}
+
+static int mtk_spmi_cali_rd_clock_polarity(struct pmif *arb)
+{
+#if defined(CONFIG_MTK_FPGA) || defined(CONFIG_FPGA_EARLY_PORTING)
+ unsigned int dly = 0, pol = 0;
+#else
+ unsigned int dly = 1, pol = 1;
+#endif
+
+ /* Indicate sampling clock polarity, 1: Positive 0: Negative */
+ mtk_spmi_writel(arb, (dly << 0x1) | pol, SPMI_SAMPL_CTRL);
+
+ return 0;
+}
+
+static int mtk_spmi_cali_rd_clock_polarity_m_p_v1(struct pmif *arb)
+{
+#if defined(CONFIG_MTK_FPGA) || defined(CONFIG_FPGA_EARLY_PORTING)
+ unsigned int dly = 0, pol = 0;
+#else
+ unsigned int dly = 0, pol = 1;
+#endif
+
+ /* Indicate sampling clock polarity, 1: Positive 0: Negative */
+ mtk_spmi_writel(arb, ((dly + 1) << 0x4) | (dly << 0x1) | pol,
+ SPMI_SAMPL_CTRL);
+
+ return 0;
+}
+
+static int mtk_spmi_cali_rd_clock_polarity_m_p_v2(struct pmif *arb)
+{
+#if defined(CONFIG_MTK_FPGA) || defined(CONFIG_FPGA_EARLY_PORTING)
+ unsigned int dly = 1, pol = 0;
+#else
+ unsigned int dly = 0, pol = 1;
+#endif
+
+ /* Indicate sampling clock polarity, 1: Positive 0: Negative */
+ mtk_spmi_writel(arb, ((dly + 1) << 0x4) | (dly << 0x1) | pol,
+ SPMI_SAMPL_CTRL);
+
+ return 0;
+}
+
+/*
+ * PMIF Exception IRQ Handler
+ */
+static void pmif_cmd_err_parity_err_irq_handler(int irq, void *data)
+{
+ spmi_dump_spmimst_all_reg();
+ spmi_dump_pmif_record_reg();
+ aee_kernel_warning("PMIF:parity error", "PMIF");
+}
+
+static void pmif_pmif_acc_vio_irq_handler(int irq, void *data)
+{
+ spmi_dump_pmif_acc_vio_reg();
+ aee_kernel_warning("PMIF:pmif_acc_vio", "PMIF");
+}
+
+static void pmif_pmic_acc_vio_irq_handler(int irq, void *data)
+{
+ spmi_dump_pmic_acc_vio_reg();
+ aee_kernel_warning("PMIF:pmic_acc_vio", "PMIF");
+}
+
+static void pmif_lat_limit_reached_irq_handler(int irq, void *data)
+{
+ spmi_dump_pmif_busy_reg();
+ spmi_dump_pmif_record_reg();
+}
+
+static void pmif_hw_monitor_irq_handler(int irq, void *data)
+{
+ spmi_dump_pmif_record_reg();
+ aee_kernel_warning("PMIF:pmif_hw_monitor_match", "PMIF");
+}
+
+static void pmif_wdt_irq_handler(int irq, void *data)
+{
+ spmi_dump_pmif_busy_reg();
+ spmi_dump_pmif_record_reg();
+ spmi_dump_wdt_reg();
+}
+
+static irqreturn_t pmif_event_0_irq_handler(int irq, void *data)
+{
+ struct pmif *arb = data;
+ int irq_f = 0, idx = 0;
+
+ __pm_stay_awake(arb->pmifThread_lock);
+ mutex_lock(&arb->pmif_mutex);
+ irq_f = pmif_readl(arb, PMIF_IRQ_FLAG_0);
+ if (irq_f == 0) {
+ mutex_unlock(&arb->pmif_mutex);
+ __pm_relax(arb->pmifThread_lock);
+ return IRQ_NONE;
+ }
+
+ for (idx = 0; idx < 31; idx++) {
+ if ((irq_f & (0x1 << idx)) != 0) {
+ switch (idx) {
+ default:
+ pr_notice("%s IRQ[%d] triggered\n",
+ __func__, idx);
+ spmi_dump_pmif_record_reg();
+ break;
+ }
+ pmif_writel(arb, irq_f, PMIF_IRQ_CLR_0);
+ break;
+ }
+ }
+ mutex_unlock(&arb->pmif_mutex);
+ __pm_relax(arb->pmifThread_lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t pmif_event_1_irq_handler(int irq, void *data)
+{
+ struct pmif *arb = data;
+ int irq_f = 0, idx = 0;
+
+ __pm_stay_awake(arb->pmifThread_lock);
+ mutex_lock(&arb->pmif_mutex);
+ irq_f = pmif_readl(arb, PMIF_IRQ_FLAG_1);
+ if (irq_f == 0) {
+ mutex_unlock(&arb->pmif_mutex);
+ __pm_relax(arb->pmifThread_lock);
+ return IRQ_NONE;
+ }
+
+ for (idx = 0; idx < 31; idx++) {
+ if ((irq_f & (0x1 << idx)) != 0) {
+ switch (idx) {
+ default:
+ pr_notice("%s IRQ[%d] triggered\n",
+ __func__, idx);
+ spmi_dump_pmif_record_reg();
+ break;
+ }
+ pmif_writel(arb, irq_f, PMIF_IRQ_CLR_1);
+ break;
+ }
+ }
+ mutex_unlock(&arb->pmif_mutex);
+ __pm_relax(arb->pmifThread_lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t pmif_event_2_irq_handler(int irq, void *data)
+{
+ struct pmif *arb = data;
+ int irq_f = 0, idx = 0;
+
+ __pm_stay_awake(arb->pmifThread_lock);
+ mutex_lock(&arb->pmif_mutex);
+ irq_f = pmif_readl(arb, PMIF_IRQ_FLAG_2);
+ if (irq_f == 0) {
+ mutex_unlock(&arb->pmif_mutex);
+ __pm_relax(arb->pmifThread_lock);
+ return IRQ_NONE;
+ }
+
+ for (idx = 0; idx < 31; idx++) {
+ if ((irq_f & (0x1 << idx)) != 0) {
+ switch (idx) {
+ case IRQ_PMIC_CMD_ERR_PARITY_ERR:
+ pmif_cmd_err_parity_err_irq_handler(irq, data);
+ break;
+ case IRQ_PMIF_ACC_VIO:
+ pmif_pmif_acc_vio_irq_handler(irq, data);
+ break;
+ case IRQ_PMIC_ACC_VIO:
+ pmif_pmic_acc_vio_irq_handler(irq, data);
+ break;
+ default:
+ pr_notice("%s IRQ[%d] triggered\n",
+ __func__, idx);
+ spmi_dump_pmif_record_reg();
+ break;
+ }
+ pmif_writel(arb, irq_f, PMIF_IRQ_CLR_2);
+ break;
+ }
+ }
+ mutex_unlock(&arb->pmif_mutex);
+ __pm_relax(arb->pmifThread_lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t pmif_event_3_irq_handler(int irq, void *data)
+{
+ struct pmif *arb = data;
+ int irq_f = 0, idx = 0;
+
+ __pm_stay_awake(arb->pmifThread_lock);
+ mutex_lock(&arb->pmif_mutex);
+ irq_f = pmif_readl(arb, PMIF_IRQ_FLAG_3);
+ if (irq_f == 0) {
+ mutex_unlock(&arb->pmif_mutex);
+ __pm_relax(arb->pmifThread_lock);
+ return IRQ_NONE;
+ }
+
+ for (idx = 0; idx < 31; idx++) {
+ if ((irq_f & (0x1 << idx)) != 0) {
+ switch (idx) {
+ case IRQ_LAT_LIMIT_REACHED:
+ pmif_lat_limit_reached_irq_handler(irq, data);
+ break;
+ case IRQ_HW_MONITOR:
+ pmif_hw_monitor_irq_handler(irq, data);
+ break;
+ case IRQ_WDT:
+ pmif_wdt_irq_handler(irq, data);
+ break;
+ case IRQ_PMIF_ACC_VIO_V2:
+ pmif_pmif_acc_vio_irq_handler(irq, data);
+ break;
+ case IRQ_PMIC_ACC_VIO_V2:
+ pmif_pmic_acc_vio_irq_handler(irq, data);
+ break;
+ default:
+ pr_notice("%s IRQ[%d] triggered\n",
+ __func__, idx);
+ spmi_dump_pmif_record_reg();
+ break;
+ }
+ pmif_writel(arb, irq_f, PMIF_IRQ_CLR_3);
+ break;
+ }
+ }
+ mutex_unlock(&arb->pmif_mutex);
+ __pm_relax(arb->pmifThread_lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t pmif_event_4_irq_handler(int irq, void *data)
+{
+ struct pmif *arb = data;
+ int irq_f = 0, idx = 0;
+
+ __pm_stay_awake(arb->pmifThread_lock);
+ mutex_lock(&arb->pmif_mutex);
+ irq_f = pmif_readl(arb, PMIF_IRQ_FLAG_4);
+ if (irq_f == 0) {
+ mutex_unlock(&arb->pmif_mutex);
+ __pm_relax(arb->pmifThread_lock);
+ return IRQ_NONE;
+ }
+
+ for (idx = 0; idx < 31; idx++) {
+ if ((irq_f & (0x1 << idx)) != 0) {
+ switch (idx) {
+ default:
+ pr_notice("%s IRQ[%d] triggered\n",
+ __func__, idx);
+ spmi_dump_pmif_record_reg();
+ break;
+ }
+ pmif_writel(arb, irq_f, PMIF_IRQ_CLR_4);
+ break;
+ }
+ }
+ mutex_unlock(&arb->pmif_mutex);
+ __pm_relax(arb->pmifThread_lock);
+
+ return IRQ_HANDLED;
+}
+
+static struct pmif_irq_desc pmif_event_irq[] = {
+ PMIF_IRQDESC(event_0),
+ PMIF_IRQDESC(event_1),
+ PMIF_IRQDESC(event_2),
+ PMIF_IRQDESC(event_3),
+ PMIF_IRQDESC(event_4),
+};
+
+static void pmif_irq_register(struct platform_device *pdev,
+ struct pmif *arb, int irq)
+{
+ int i = 0, ret = 0;
+ u32 irq_event_en[5] = {0};
+
+ for (i = 0; i < ARRAY_SIZE(pmif_event_irq); i++) {
+ if (!pmif_event_irq[i].name)
+ continue;
+ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
+ pmif_event_irq[i].irq_handler,
+ IRQF_TRIGGER_HIGH | IRQF_ONESHOT | IRQF_SHARED,
+ pmif_event_irq[i].name, arb);
+ if (ret < 0) {
+ dev_notice(&pdev->dev, "request %s irq fail\n",
+ pmif_event_irq[i].name);
+ continue;
+ }
+ pmif_event_irq[i].irq = irq;
+ }
+
+ ret = of_property_read_u32_array(pdev->dev.of_node, "irq_event_en",
+ irq_event_en, ARRAY_SIZE(irq_event_en));
+
+ pmif_writel(arb, irq_event_en[0] | pmif_readl(arb, PMIF_IRQ_EVENT_EN_0),
+ PMIF_IRQ_EVENT_EN_0);
+ pmif_writel(arb, irq_event_en[1] | pmif_readl(arb, PMIF_IRQ_EVENT_EN_1),
+ PMIF_IRQ_EVENT_EN_1);
+ pmif_writel(arb, irq_event_en[2] | pmif_readl(arb, PMIF_IRQ_EVENT_EN_2),
+ PMIF_IRQ_EVENT_EN_2);
+ pmif_writel(arb, irq_event_en[3] | pmif_readl(arb, PMIF_IRQ_EVENT_EN_3),
+ PMIF_IRQ_EVENT_EN_3);
+ pmif_writel(arb, irq_event_en[4] | pmif_readl(arb, PMIF_IRQ_EVENT_EN_4),
+ PMIF_IRQ_EVENT_EN_4);
+}
+
+static void rcs_irq_lock(struct irq_data *data)
+{
+ struct pmif *arb = irq_data_get_irq_chip_data(data);
+
+ mutex_lock(&arb->rcs_irqlock);
+}
+
+static void rcs_irq_sync_unlock(struct irq_data *data)
+{
+ struct pmif *arb = irq_data_get_irq_chip_data(data);
+
+ mutex_unlock(&arb->rcs_irqlock);
+}
+
+static void rcs_irq_enable(struct irq_data *data)
+{
+ unsigned int hwirq = irqd_to_hwirq(data);
+ struct pmif *arb = irq_data_get_irq_chip_data(data);
+
+ arb->rcs_enable_hwirq[hwirq] = true;
+}
+
+static void rcs_irq_disable(struct irq_data *data)
+{
+ unsigned int hwirq = irqd_to_hwirq(data);
+ struct pmif *arb = irq_data_get_irq_chip_data(data);
+
+ arb->rcs_enable_hwirq[hwirq] = false;
+}
+
+static const struct irq_chip rcs_irq_chip = {
+ .name = "rcs_irq",
+ .irq_bus_lock = rcs_irq_lock,
+ .irq_bus_sync_unlock = rcs_irq_sync_unlock,
+ .irq_enable = rcs_irq_enable,
+ .irq_disable = rcs_irq_disable,
+};
+
+static int rcs_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ struct pmif *arb = d->host_data;
+
+ irq_set_chip_data(virq, arb);
+ irq_set_chip(virq, &arb->irq_chip);
+ irq_set_nested_thread(virq, 1);
+ irq_set_parent(virq, arb->rcs_irq);
+ irq_set_noprobe(virq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops rcs_irq_domain_ops = {
+ .map = rcs_irq_map,
+ .xlate = irq_domain_xlate_onetwocell,
+};
+
+static irqreturn_t rcs_irq_handler(int irq, void *data)
+{
+ struct pmif *arb = data;
+ unsigned int slv_irq_sta;
+ int i;
+
+ for (i = 0; i < SPMI_MAX_SLAVE_ID; i++) {
+ slv_irq_sta = mtk_spmi_readl(arb, SPMI_SLV_3_0_EINT + (i / 4));
+ slv_irq_sta >>= (((i % 4) * 8) & 0xFF);
+ if (arb->rcs_enable_hwirq[i] && slv_irq_sta) {
+ dev_info(&arb->spmic->dev,
+ "hwirq=%d, sta=0x%x\n", i, slv_irq_sta);
+ handle_nested_irq(irq_find_mapping(arb->domain, i));
+ }
+ /* need to clear using 0xFF to avoid new irq happen
+ * after read SPMI_SLV_3_0_EINT + (i/4) value then use
+ * this value to clean
+ */
+ mtk_spmi_writel(arb, (0xFF << ((i % 4) * 8)),
+ SPMI_SLV_3_0_EINT + (i / 4));
+ }
+ return IRQ_HANDLED;
+}
+
+static int rcs_irq_register(struct platform_device *pdev,
+ struct pmif *arb, int irq)
+{
+ int i, ret = 0;
+
+ mutex_init(&arb->rcs_irqlock);
+ arb->rcs_enable_hwirq = devm_kcalloc(&pdev->dev, SPMI_MAX_SLAVE_ID,
+ sizeof(*arb->rcs_enable_hwirq),
+ GFP_KERNEL);
+ if (!arb->rcs_enable_hwirq)
+ return -ENOMEM;
+
+ arb->irq_chip = rcs_irq_chip;
+ arb->domain = irq_domain_add_linear(pdev->dev.of_node,
+ SPMI_MAX_SLAVE_ID,
+ &rcs_irq_domain_ops, arb);
+ if (!arb->domain) {
+ dev_notice(&pdev->dev, "Failed to create IRQ domain\n");
+ return -ENODEV;
+ }
+ /* clear all slave irq status */
+ for (i = 0; i < SPMI_MAX_SLAVE_ID; i++) {
+ mtk_spmi_writel(arb, (0xFF << ((i % 4) * 8)),
+ SPMI_SLV_3_0_EINT + (i / 4));
+ }
+ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
+ rcs_irq_handler, IRQF_ONESHOT,
+ rcs_irq_chip.name, arb);
+ if (ret < 0) {
+ dev_notice(&pdev->dev, "Failed to request IRQ=%d, ret = %d\n",
+ irq, ret);
+ return ret;
+ }
+ enable_irq_wake(irq);
+
+ return ret;
+}
+
+static int mtk_spmimst_init(struct platform_device *pdev, struct pmif *arb)
+{
+ struct resource *res = NULL;
+ int err = 0;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spmimst");
+ arb->spmimst_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(arb->spmimst_base)) {
+ err = PTR_ERR(arb->spmimst_base);
+ return err;
+ }
+
+ err = of_property_read_u32(pdev->dev.of_node, "grpid", &arb->grpid);
+ if (err) {
+ dev_notice(&pdev->dev, "[SPMIMST]:grpid unspecified.\n");
+ return -EINVAL;
+ }
+ /* set group id */
+ mtk_spmi_enable_group_id(arb, arb->grpid);
+
+ /* if spmimst not enabled, enable it */
+ if ((mtk_spmi_readl(arb, SPMI_REQ_EN) & 0x1) != 0x1) {
+ dev_info(&pdev->dev, "[SPMIMST]:enable spmimst.\n");
+ arb->spmi_config_master(arb, arb->mstid, true);
+ arb->pmif_cali_clock(arb);
+ }
+ pr_notice("[SPMIMST]:%s done\n", __func__);
+
+ return 0;
+}
+
+
+static int pmif_probe(struct platform_device *pdev)
+{
+ struct device_node *node = NULL;
+ const struct of_device_id *of_id =
+ of_match_device(pmif_match_table, &pdev->dev);
+ struct spmi_controller *ctrl = NULL;
+ struct pmif *arb = NULL;
+ struct resource *res = NULL;
+ u32 swinf_ch_start = 0, ap_swinf_no = 0;
+#if !defined(CONFIG_FPGA_EARLY_PORTING)
+ int pmif_clk26m = 0, spmimst_clk = 0;
+#endif
+ int err = 0;
+
+#if PMIF_BRINGUP
+ dev_notice(&pdev->dev, "[PMIF]bringup do nothing\n");
+ return 0;
+#endif
+ if (!of_id) {
+ dev_notice(&pdev->dev, "[PMIF]:Error: No device match found\n");
+ return -ENODEV;
+ }
+
+ ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*arb));
+ if (!ctrl)
+ return -ENOMEM;
+
+ /* re-assign of_id->data */
+ spmi_controller_set_drvdata(ctrl, (void *)of_id->data);
+ arb = spmi_controller_get_drvdata(ctrl);
+ arb->spmic = ctrl;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmif");
+ arb->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(arb->base)) {
+ err = PTR_ERR(arb->base);
+ goto err_put_ctrl;
+ }
+ /* pmif is not initialized, just init once */
+ node = of_find_compatible_node(NULL, NULL, "mediatek,infracfg_ao");
+ arb->infra_base = of_iomap(node, 0);
+ if (IS_ERR(arb->infra_base)) {
+ err = PTR_ERR(arb->infra_base);
+ goto err_put_ctrl;
+ }
+
+ node = of_find_compatible_node(NULL, NULL, "mediatek,topckgen");
+ arb->topckgen_base = of_iomap(node, 0);
+ if (IS_ERR(arb->topckgen_base)) {
+ err = PTR_ERR(arb->topckgen_base);
+ goto err_put_ctrl;
+ }
+
+ node = of_find_compatible_node(NULL, NULL, "mediatek,toprgu");
+ arb->toprgu_base = of_iomap(node, 0);
+ if (IS_ERR(arb->toprgu_base)) {
+ err = PTR_ERR(arb->toprgu_base);
+ goto err_put_ctrl;
+ }
+#if !defined(CONFIG_FPGA_EARLY_PORTING)
+ /* get pmif infracfg_ao clock */
+ arb->pmif_sys_ck = devm_clk_get(&pdev->dev, "pmif_sys_ck");
+ if (IS_ERR(arb->pmif_sys_ck)) {
+ dev_notice(&pdev->dev, "[PMIF]:failed to get ap clock: %ld\n",
+ PTR_ERR(arb->pmif_sys_ck));
+ return PTR_ERR(arb->pmif_sys_ck);
+ }
+
+ arb->pmif_tmr_ck = devm_clk_get(&pdev->dev, "pmif_tmr_ck");
+ if (IS_ERR(arb->pmif_tmr_ck)) {
+ dev_notice(&pdev->dev, "[PMIF]:failed to get tmr clock: %ld\n",
+ PTR_ERR(arb->pmif_tmr_ck));
+ return PTR_ERR(arb->pmif_tmr_ck);
+ }
+
+ /* get pmif topckgen clock */
+ arb->pmif_clk_mux = devm_clk_get(&pdev->dev, "pmif_clk_mux");
+ if (IS_ERR(arb->pmif_clk_mux)) {
+ dev_notice(&pdev->dev, "[PMIF]:failed to get clock: %ld\n",
+ PTR_ERR(arb->pmif_clk_mux));
+ return PTR_ERR(arb->pmif_clk_mux);
+ }
+ /* now enable pmif/spmimst clock */
+ pmif_clk26m =
+ readl(arb->infra_base + arb->infra_regs[PMICW_CLOCK_CTRL]);
+
+ if ((pmif_clk26m & 0x1) == 0x1) {
+ arb->pmif_clk26m = devm_clk_get(&pdev->dev, "pmif_clk26m");
+ if (IS_ERR(arb->pmif_clk26m)) {
+ dev_notice(&pdev->dev,
+ "[PMIF]:failed to get clock: %ld\n",
+ PTR_ERR(arb->pmif_clk26m));
+ return PTR_ERR(arb->pmif_clk26m);
+ }
+ dev_info(&pdev->dev, "[PMIF]:enable clk26m.\n");
+ err = clk_prepare_enable(arb->pmif_clk26m);
+ if (err)
+ return err;
+ } else {
+ arb->pmif_clk_mux_parent = devm_clk_get(&pdev->dev,
+ "pmif_clk_osc_d10");
+ dev_info(&pdev->dev, "[PMIF]:enable ulposc1 osc d10.\n");
+ if (IS_ERR(arb->pmif_clk_mux_parent)) {
+ dev_notice(&pdev->dev,
+ "[PMIF]:failed to get clock: %ld\n",
+ PTR_ERR(arb->pmif_clk_mux_parent));
+ return PTR_ERR(arb->pmif_clk_mux_parent);
+ }
+ err = clk_prepare_enable(arb->pmif_clk_mux);
+ if (err)
+ return err;
+ err = clk_set_parent(arb->pmif_clk_mux,
+ arb->pmif_clk_mux_parent);
+ if (err)
+ return err;
+ }
+ err = clk_prepare_enable(arb->pmif_sys_ck);
+ if (err)
+ return err;
+ err = clk_prepare_enable(arb->pmif_tmr_ck);
+ if (err)
+ return err;
+
+ /* get spmimst topckgen clock */
+ arb->spmimst_clk_mux = devm_clk_get(&pdev->dev, "spmimst_clk_mux");
+ if (IS_ERR(arb->spmimst_clk_mux)) {
+ dev_notice(&pdev->dev, "[SPMIMST]:failed to get clock: %ld\n",
+ PTR_ERR(arb->spmimst_clk_mux));
+ return PTR_ERR(arb->spmimst_clk_mux);
+ }
+ if (of_device_is_compatible(ctrl->dev.parent->of_node,
+ "mediatek,mt6885-pmif")) {
+ spmimst_clk =
+ readl(arb->topckgen_base + arb->topckgen_regs[CLK_CFG_16]);
+ spmimst_clk = 0x7;
+ } else if (of_device_is_compatible(ctrl->dev.parent->of_node,
+ "mediatek,mt6880-pmif-m")) {
+ spmimst_clk =
+ readl(arb->topckgen_base + arb->topckgen_regs[CLK_CFG_6]);
+ spmimst_clk = (spmimst_clk >> 16) & 0x7;
+ } else if (of_device_is_compatible(ctrl->dev.parent->of_node,
+ "mediatek,mt6880-pmif-p")) {
+ spmimst_clk =
+ readl(arb->topckgen_base + arb->topckgen_regs[CLK_CFG_6]);
+ spmimst_clk = (spmimst_clk >> 24) & 0xF;
+ } else {
+ spmimst_clk =
+ readl(arb->topckgen_base + arb->topckgen_regs[CLK_CFG_15]);
+ spmimst_clk = (spmimst_clk >> 0x8) & 0x7;
+ }
+ switch (spmimst_clk) {
+ case 0:
+ arb->spmimst_clk_mux_parent =
+ devm_clk_get(&pdev->dev, "spmimst_clk26m");
+ dev_info(&pdev->dev, "[SPMIMST]:enable clk26m.\n");
+ break;
+ case 3:
+ arb->spmimst_clk_mux_parent =
+ devm_clk_get(&pdev->dev, "spmimst_clk_osc_d10");
+ dev_info(&pdev->dev, "[SPMIMST]:enable ulposc1 osc d10.\n");
+ break;
+ case 7:
+ arb->spmimst_clk_mux_parent =
+ devm_clk_get(&pdev->dev, "spmimst_clk_mainpll_d7_d8");
+ dev_info(&pdev->dev, "[SPMIMST]:enable mainpll d7 d8.\n");
+ break;
+ }
+ if (IS_ERR(arb->spmimst_clk_mux_parent)) {
+ dev_notice(&pdev->dev,
+ "[SPMIMST]:failed to get clock: %ld\n",
+ PTR_ERR(arb->spmimst_clk_mux_parent));
+ return PTR_ERR(arb->spmimst_clk_mux_parent);
+ }
+ err = clk_prepare_enable(arb->spmimst_clk_mux);
+ if (err)
+ return err;
+ err = clk_set_parent(arb->spmimst_clk_mux, arb->spmimst_clk_mux_parent);
+ if (err)
+ return err;
+#else
+ dev_notice(&pdev->dev, "[PMIF]:no need to get clock at fpga\n");
+#endif /* #if defined(CONFIG_MTK_FPGA) || defined(CONFIG_FPGA_EARLY_PORTING) */
+
+ err = of_property_read_u32(pdev->dev.of_node,
+ "swinf_ch_start", &swinf_ch_start);
+ if (err) {
+ dev_notice(&pdev->dev, "[PMIF]:swinf_ch_start unspecified.\n");
+ goto err_put_ctrl;
+ }
+ arb->swinf_ch_start = swinf_ch_start;
+
+ err = of_property_read_u32(pdev->dev.of_node,
+ "ap_swinf_no", &ap_swinf_no);
+ if (err) {
+ dev_notice(&pdev->dev, "[PMIF]:ap_swinf_no unspecified.\n");
+ goto err_put_ctrl;
+ }
+ arb->ap_swinf_no = ap_swinf_no;
+
+ if (arb->is_pmif_init_done(arb) == 0) {
+ /* pmif initialize start */
+ arb->pmif_enable_clk_set(arb);
+ arb->pmif_force_normal_mode(arb);
+ /* Enable SWINF and arbitration for AP. */
+ arb->pmif_enable_swinf(arb,
+ arb->swinf_ch_start, arb->ap_swinf_no);
+ arb->pmif_enable_cmdIssue(arb, true);
+
+ arb->pmif_enable(arb);
+ /* pmif initialize end */
+ }
+
+ raw_spin_lock_init(&arb->lock);
+ arb->pmifThread_lock =
+ wakeup_source_register(NULL, "pmif wakelock");
+ mutex_init(&arb->pmif_mutex);
+
+ ctrl->cmd = pmif_arb_cmd;
+ ctrl->read_cmd = pmif_spmi_read_cmd;
+ ctrl->write_cmd = pmif_spmi_write_cmd;
+
+ if (arb->is_pmif_init_done(arb)) {
+ /* pmif already done, call spmi master driver init */
+ err = mtk_spmimst_init(pdev, arb);
+ if (err)
+ goto err_put_ctrl;
+ }
+ if (arb->pmifid != PMIF_PMIFID_SPMI2) {
+ /* enable debugger for SPMI-M */
+ spmi_pmif_dbg_init(ctrl);
+ spmi_pmif_create_attr(&pmif_driver.driver);
+ }
+ arb->irq = platform_get_irq_byname(pdev, "pmif_irq");
+ if (arb->irq < 0) {
+ err = arb->irq;
+ goto err_put_ctrl;
+ }
+ pmif_irq_register(pdev, arb, arb->irq);
+
+ arb->rcs_irq = platform_get_irq_byname(pdev, "rcs_irq");
+ if (arb->rcs_irq < 0) {
+ dev_notice(&pdev->dev,
+ "Failed to get rcs_irq, ret = %d\n", arb->rcs_irq);
+ } else {
+ err = rcs_irq_register(pdev, arb, arb->rcs_irq);
+ if (err)
+ goto err_domain_remove;
+ }
+
+ platform_set_drvdata(pdev, ctrl);
+
+ err = spmi_controller_add(ctrl);
+ if (err)
+ goto err_domain_remove;
+
+ return 0;
+
+err_domain_remove:
+ if (arb->domain)
+ irq_domain_remove(arb->domain);
+#if !defined(CONFIG_FPGA_EARLY_PORTING)
+ clk_disable_unprepare(arb->spmimst_clk_mux);
+ clk_disable_unprepare(arb->pmif_tmr_ck);
+ clk_disable_unprepare(arb->pmif_sys_ck);
+ if ((pmif_clk26m & 0x1) == 0x1)
+ clk_disable_unprepare(arb->pmif_clk26m);
+ else
+ clk_disable_unprepare(arb->pmif_clk_mux);
+#endif
+err_put_ctrl:
+ spmi_controller_put(ctrl);
+ return err;
+}
+
+static int pmif_remove(struct platform_device *pdev)
+{
+ struct spmi_controller *ctrl = platform_get_drvdata(pdev);
+ struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+
+ if (arb->domain)
+ irq_domain_remove(arb->domain);
+ spmi_controller_remove(ctrl);
+ spmi_controller_put(ctrl);
+ return 0;
+}
+
+static struct platform_driver pmif_driver = {
+ .probe = pmif_probe,
+ .remove = pmif_remove,
+ .driver = {
+ .name = "pmif",
+ .of_match_table = of_match_ptr(pmif_match_table),
+ },
+};
+
+static int __init mtk_pmif_init(void)
+{
+ int ret = 0;
+
+ ret = platform_driver_register(&pmif_driver);
+ if (ret)
+ return -ENODEV;
+ return 0;
+}
+postcore_initcall(mtk_pmif_init);
+
+/* Module information */
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIF module");
+MODULE_AUTHOR("Argus Lin <argus.lin@mediatek.com>");
+MODULE_ALIAS("platform:pmif");
diff --git a/src/kernel/linux/v4.19/drivers/spmi/spmi-pmic-arb.c b/src/kernel/linux/v4.19/drivers/spmi/spmi-pmic-arb.c
new file mode 100644
index 0000000..360b821
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/spmi/spmi-pmic-arb.c
@@ -0,0 +1,1333 @@
+/*
+ * Copyright (c) 2012-2015, 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/bitmap.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spmi.h>
+
+/* PMIC Arbiter configuration registers */
+#define PMIC_ARB_VERSION 0x0000
+#define PMIC_ARB_VERSION_V2_MIN 0x20010000
+#define PMIC_ARB_VERSION_V3_MIN 0x30000000
+#define PMIC_ARB_VERSION_V5_MIN 0x50000000
+#define PMIC_ARB_INT_EN 0x0004
+
+/* PMIC Arbiter channel registers offsets */
+#define PMIC_ARB_CMD 0x00
+#define PMIC_ARB_CONFIG 0x04
+#define PMIC_ARB_STATUS 0x08
+#define PMIC_ARB_WDATA0 0x10
+#define PMIC_ARB_WDATA1 0x14
+#define PMIC_ARB_RDATA0 0x18
+#define PMIC_ARB_RDATA1 0x1C
+
+/* Mapping Table */
+#define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N)))
+#define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF)
+#define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1)
+#define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF)
+#define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1)
+#define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
+
+#define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
+#define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */
+#define PMIC_ARB_APID_VALID BIT(15)
+#define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))
+#define INVALID_EE 0xFF
+
+/* Ownership Table */
+#define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N)))
+#define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7)
+
+/* Channel Status fields */
+enum pmic_arb_chnl_status {
+ PMIC_ARB_STATUS_DONE = BIT(0),
+ PMIC_ARB_STATUS_FAILURE = BIT(1),
+ PMIC_ARB_STATUS_DENIED = BIT(2),
+ PMIC_ARB_STATUS_DROPPED = BIT(3),
+};
+
+/* Command register fields */
+#define PMIC_ARB_CMD_MAX_BYTE_COUNT 8
+
+/* Command Opcodes */
+enum pmic_arb_cmd_op_code {
+ PMIC_ARB_OP_EXT_WRITEL = 0,
+ PMIC_ARB_OP_EXT_READL = 1,
+ PMIC_ARB_OP_EXT_WRITE = 2,
+ PMIC_ARB_OP_RESET = 3,
+ PMIC_ARB_OP_SLEEP = 4,
+ PMIC_ARB_OP_SHUTDOWN = 5,
+ PMIC_ARB_OP_WAKEUP = 6,
+ PMIC_ARB_OP_AUTHENTICATE = 7,
+ PMIC_ARB_OP_MSTR_READ = 8,
+ PMIC_ARB_OP_MSTR_WRITE = 9,
+ PMIC_ARB_OP_EXT_READ = 13,
+ PMIC_ARB_OP_WRITE = 14,
+ PMIC_ARB_OP_READ = 15,
+ PMIC_ARB_OP_ZERO_WRITE = 16,
+};
+
+/*
+ * PMIC arbiter version 5 uses different register offsets for read/write vs
+ * observer channels.
+ */
+enum pmic_arb_channel {
+ PMIC_ARB_CHANNEL_RW,
+ PMIC_ARB_CHANNEL_OBS,
+};
+
+/* Maximum number of support PMIC peripherals */
+#define PMIC_ARB_MAX_PERIPHS 512
+#define PMIC_ARB_TIMEOUT_US 100
+#define PMIC_ARB_MAX_TRANS_BYTES (8)
+
+#define PMIC_ARB_APID_MASK 0xFF
+#define PMIC_ARB_PPID_MASK 0xFFF
+
+/* interrupt enable bit */
+#define SPMI_PIC_ACC_ENABLE_BIT BIT(0)
+
+#define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
+ ((((slave_id) & 0xF) << 28) | \
+ (((periph_id) & 0xFF) << 20) | \
+ (((irq_id) & 0x7) << 16) | \
+ (((apid) & 0x1FF) << 0))
+
+#define hwirq_to_sid(hwirq) (((hwirq) >> 28) & 0xF)
+#define hwirq_to_per(hwirq) (((hwirq) >> 20) & 0xFF)
+#define hwirq_to_irq(hwirq) (((hwirq) >> 16) & 0x7)
+#define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x1FF)
+
+struct pmic_arb_ver_ops;
+
+struct apid_data {
+ u16 ppid;
+ u8 write_ee;
+ u8 irq_ee;
+};
+
+/**
+ * spmi_pmic_arb - SPMI PMIC Arbiter object
+ *
+ * @rd_base: on v1 "core", on v2 "observer" register base off DT.
+ * @wr_base: on v1 "core", on v2 "chnls" register base off DT.
+ * @intr: address of the SPMI interrupt control registers.
+ * @cnfg: address of the PMIC Arbiter configuration registers.
+ * @lock: lock to synchronize accesses.
+ * @channel: execution environment channel to use for accesses.
+ * @irq: PMIC ARB interrupt.
+ * @ee: the current Execution Environment
+ * @min_apid: minimum APID (used for bounding IRQ search)
+ * @max_apid: maximum APID
+ * @mapping_table: in-memory copy of PPID -> APID mapping table.
+ * @domain: irq domain object for PMIC IRQ domain
+ * @spmic: SPMI controller object
+ * @ver_ops: version dependent operations.
+ * @ppid_to_apid in-memory copy of PPID -> APID mapping table.
+ */
+struct spmi_pmic_arb {
+ void __iomem *rd_base;
+ void __iomem *wr_base;
+ void __iomem *intr;
+ void __iomem *cnfg;
+ void __iomem *core;
+ resource_size_t core_size;
+ raw_spinlock_t lock;
+ u8 channel;
+ int irq;
+ u8 ee;
+ u16 min_apid;
+ u16 max_apid;
+ u32 *mapping_table;
+ DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
+ struct irq_domain *domain;
+ struct spmi_controller *spmic;
+ const struct pmic_arb_ver_ops *ver_ops;
+ u16 *ppid_to_apid;
+ u16 last_apid;
+ struct apid_data apid_data[PMIC_ARB_MAX_PERIPHS];
+};
+
+/**
+ * pmic_arb_ver: version dependent functionality.
+ *
+ * @ver_str: version string.
+ * @ppid_to_apid: finds the apid for a given ppid.
+ * @non_data_cmd: on v1 issues an spmi non-data command.
+ * on v2 no HW support, returns -EOPNOTSUPP.
+ * @offset: on v1 offset of per-ee channel.
+ * on v2 offset of per-ee and per-ppid channel.
+ * @fmt_cmd: formats a GENI/SPMI command.
+ * @owner_acc_status: on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
+ * on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn.
+ * @acc_enable: on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
+ * on v2 address of SPMI_PIC_ACC_ENABLEn.
+ * @irq_status: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
+ * on v2 address of SPMI_PIC_IRQ_STATUSn.
+ * @irq_clear: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
+ * on v2 address of SPMI_PIC_IRQ_CLEARn.
+ * @apid_map_offset: offset of PMIC_ARB_REG_CHNLn
+ */
+struct pmic_arb_ver_ops {
+ const char *ver_str;
+ int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
+ /* spmi commands (read_cmd, write_cmd, cmd) functionality */
+ int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type);
+ u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
+ int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
+ /* Interrupts controller functionality (offset of PIC registers) */
+ void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
+ u16 n);
+ void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
+ void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
+ void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
+ u32 (*apid_map_offset)(u16 n);
+};
+
+static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
+ u32 offset, u32 val)
+{
+ writel_relaxed(val, pmic_arb->wr_base + offset);
+}
+
+static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,
+ u32 offset, u32 val)
+{
+ writel_relaxed(val, pmic_arb->rd_base + offset);
+}
+
+/**
+ * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
+ * @bc: byte count -1. range: 0..3
+ * @reg: register's address
+ * @buf: output parameter, length must be bc + 1
+ */
+static void
+pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)
+{
+ u32 data = __raw_readl(pmic_arb->rd_base + reg);
+
+ memcpy(buf, &data, (bc & 3) + 1);
+}
+
+/**
+ * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register
+ * @bc: byte-count -1. range: 0..3.
+ * @reg: register's address.
+ * @buf: buffer to write. length must be bc + 1.
+ */
+static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,
+ u32 reg, u8 bc)
+{
+ u32 data = 0;
+
+ memcpy(&data, buf, (bc & 3) + 1);
+ __raw_writel(data, pmic_arb->wr_base + reg);
+}
+
+static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
+ void __iomem *base, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
+{
+ struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+ u32 status = 0;
+ u32 timeout = PMIC_ARB_TIMEOUT_US;
+ u32 offset;
+ int rc;
+
+ rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
+ if (rc < 0)
+ return rc;
+
+ offset = rc;
+ offset += PMIC_ARB_STATUS;
+
+ while (timeout--) {
+ status = readl_relaxed(base + offset);
+
+ if (status & PMIC_ARB_STATUS_DONE) {
+ if (status & PMIC_ARB_STATUS_DENIED) {
+ dev_err(&ctrl->dev, "%s: transaction denied (0x%x)\n",
+ __func__, status);
+ return -EPERM;
+ }
+
+ if (status & PMIC_ARB_STATUS_FAILURE) {
+ dev_err(&ctrl->dev, "%s: transaction failed (0x%x)\n",
+ __func__, status);
+ return -EIO;
+ }
+
+ if (status & PMIC_ARB_STATUS_DROPPED) {
+ dev_err(&ctrl->dev, "%s: transaction dropped (0x%x)\n",
+ __func__, status);
+ return -EIO;
+ }
+
+ return 0;
+ }
+ udelay(1);
+ }
+
+ dev_err(&ctrl->dev, "%s: timeout, status 0x%x\n",
+ __func__, status);
+ return -ETIMEDOUT;
+}
+
+static int
+pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
+{
+ struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+ unsigned long flags;
+ u32 cmd;
+ int rc;
+ u32 offset;
+
+ rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
+ if (rc < 0)
+ return rc;
+
+ offset = rc;
+ cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);
+
+ raw_spin_lock_irqsave(&pmic_arb->lock, flags);
+ pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
+ rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,
+ PMIC_ARB_CHANNEL_RW);
+ raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
+
+ return rc;
+}
+
+static int
+pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)
+{
+ return -EOPNOTSUPP;
+}
+
+/* Non-data command */
+static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
+{
+ struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+
+ dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);
+
+ /* Check for valid non-data command */
+ if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
+ return -EINVAL;
+
+ return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
+}
+
+static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
+ u16 addr, u8 *buf, size_t len)
+{
+ struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+ unsigned long flags;
+ u8 bc = len - 1;
+ u32 cmd;
+ int rc;
+ u32 offset;
+
+ rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
+ PMIC_ARB_CHANNEL_OBS);
+ if (rc < 0)
+ return rc;
+
+ offset = rc;
+ if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
+ dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
+ PMIC_ARB_MAX_TRANS_BYTES, len);
+ return -EINVAL;
+ }
+
+ /* Check the opcode */
+ if (opc >= 0x60 && opc <= 0x7F)
+ opc = PMIC_ARB_OP_READ;
+ else if (opc >= 0x20 && opc <= 0x2F)
+ opc = PMIC_ARB_OP_EXT_READ;
+ else if (opc >= 0x38 && opc <= 0x3F)
+ opc = PMIC_ARB_OP_EXT_READL;
+ else
+ return -EINVAL;
+
+ cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
+
+ raw_spin_lock_irqsave(&pmic_arb->lock, flags);
+ pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
+ rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,
+ PMIC_ARB_CHANNEL_OBS);
+ if (rc)
+ goto done;
+
+ pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
+ min_t(u8, bc, 3));
+
+ if (bc > 3)
+ pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1,
+ bc - 4);
+
+done:
+ raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
+ return rc;
+}
+
+static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
+ u16 addr, const u8 *buf, size_t len)
+{
+ struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+ unsigned long flags;
+ u8 bc = len - 1;
+ u32 cmd;
+ int rc;
+ u32 offset;
+
+ rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
+ PMIC_ARB_CHANNEL_RW);
+ if (rc < 0)
+ return rc;
+
+ offset = rc;
+ if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
+ dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
+ PMIC_ARB_MAX_TRANS_BYTES, len);
+ return -EINVAL;
+ }
+
+ /* Check the opcode */
+ if (opc >= 0x40 && opc <= 0x5F)
+ opc = PMIC_ARB_OP_WRITE;
+ else if (opc <= 0x0F)
+ opc = PMIC_ARB_OP_EXT_WRITE;
+ else if (opc >= 0x30 && opc <= 0x37)
+ opc = PMIC_ARB_OP_EXT_WRITEL;
+ else if (opc >= 0x80)
+ opc = PMIC_ARB_OP_ZERO_WRITE;
+ else
+ return -EINVAL;
+
+ cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
+
+ /* Write data to FIFOs */
+ raw_spin_lock_irqsave(&pmic_arb->lock, flags);
+ pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
+ min_t(u8, bc, 3));
+ if (bc > 3)
+ pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1,
+ bc - 4);
+
+ /* Start the transaction */
+ pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
+ rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,
+ PMIC_ARB_CHANNEL_RW);
+ raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
+
+ return rc;
+}
+
+enum qpnpint_regs {
+ QPNPINT_REG_RT_STS = 0x10,
+ QPNPINT_REG_SET_TYPE = 0x11,
+ QPNPINT_REG_POLARITY_HIGH = 0x12,
+ QPNPINT_REG_POLARITY_LOW = 0x13,
+ QPNPINT_REG_LATCHED_CLR = 0x14,
+ QPNPINT_REG_EN_SET = 0x15,
+ QPNPINT_REG_EN_CLR = 0x16,
+ QPNPINT_REG_LATCHED_STS = 0x18,
+};
+
+struct spmi_pmic_arb_qpnpint_type {
+ u8 type; /* 1 -> edge */
+ u8 polarity_high;
+ u8 polarity_low;
+} __packed;
+
+/* Simplified accessor functions for irqchip callbacks */
+static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
+ size_t len)
+{
+ struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ u8 sid = hwirq_to_sid(d->hwirq);
+ u8 per = hwirq_to_per(d->hwirq);
+
+ if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
+ (per << 8) + reg, buf, len))
+ dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
+ d->irq);
+}
+
+static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
+{
+ struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ u8 sid = hwirq_to_sid(d->hwirq);
+ u8 per = hwirq_to_per(d->hwirq);
+
+ if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid,
+ (per << 8) + reg, buf, len))
+ dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
+ d->irq);
+}
+
+static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
+{
+ u16 ppid = pmic_arb->apid_data[apid].ppid;
+ u8 sid = ppid >> 8;
+ u8 per = ppid & 0xFF;
+ u8 irq_mask = BIT(id);
+
+ writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
+
+ if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
+ (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1))
+ dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
+ irq_mask, ppid);
+
+ if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
+ (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1))
+ dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
+ irq_mask, ppid);
+}
+
+static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
+{
+ unsigned int irq;
+ u32 status;
+ int id;
+ u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF;
+ u8 per = pmic_arb->apid_data[apid].ppid & 0xFF;
+
+ status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid));
+ while (status) {
+ id = ffs(status) - 1;
+ status &= ~BIT(id);
+ irq = irq_find_mapping(pmic_arb->domain,
+ spec_to_hwirq(sid, per, id, apid));
+ if (irq == 0) {
+ cleanup_irq(pmic_arb, apid, id);
+ continue;
+ }
+ generic_handle_irq(irq);
+ }
+}
+
+static void pmic_arb_chained_irq(struct irq_desc *desc)
+{
+ struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc);
+ const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ int first = pmic_arb->min_apid >> 5;
+ int last = pmic_arb->max_apid >> 5;
+ u8 ee = pmic_arb->ee;
+ u32 status, enable;
+ int i, id, apid;
+
+ chained_irq_enter(chip, desc);
+
+ for (i = first; i <= last; ++i) {
+ status = readl_relaxed(
+ ver_ops->owner_acc_status(pmic_arb, ee, i));
+ while (status) {
+ id = ffs(status) - 1;
+ status &= ~BIT(id);
+ apid = id + i * 32;
+ enable = readl_relaxed(
+ ver_ops->acc_enable(pmic_arb, apid));
+ if (enable & SPMI_PIC_ACC_ENABLE_BIT)
+ periph_interrupt(pmic_arb, apid);
+ }
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static void qpnpint_irq_ack(struct irq_data *d)
+{
+ struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ u8 irq = hwirq_to_irq(d->hwirq);
+ u16 apid = hwirq_to_apid(d->hwirq);
+ u8 data;
+
+ writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
+
+ data = BIT(irq);
+ qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
+}
+
+static void qpnpint_irq_mask(struct irq_data *d)
+{
+ u8 irq = hwirq_to_irq(d->hwirq);
+ u8 data = BIT(irq);
+
+ qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
+}
+
+static void qpnpint_irq_unmask(struct irq_data *d)
+{
+ struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
+ u8 irq = hwirq_to_irq(d->hwirq);
+ u16 apid = hwirq_to_apid(d->hwirq);
+ u8 buf[2];
+
+ writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
+ ver_ops->acc_enable(pmic_arb, apid));
+
+ qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);
+ if (!(buf[0] & BIT(irq))) {
+ /*
+ * Since the interrupt is currently disabled, write to both the
+ * LATCHED_CLR and EN_SET registers so that a spurious interrupt
+ * cannot be triggered when the interrupt is enabled
+ */
+ buf[0] = BIT(irq);
+ buf[1] = BIT(irq);
+ qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2);
+ }
+}
+
+static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
+{
+ struct spmi_pmic_arb_qpnpint_type type;
+ irq_flow_handler_t flow_handler;
+ u8 irq = hwirq_to_irq(d->hwirq);
+
+ qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
+
+ if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
+ type.type |= BIT(irq);
+ if (flow_type & IRQF_TRIGGER_RISING)
+ type.polarity_high |= BIT(irq);
+ if (flow_type & IRQF_TRIGGER_FALLING)
+ type.polarity_low |= BIT(irq);
+
+ flow_handler = handle_edge_irq;
+ } else {
+ if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
+ (flow_type & (IRQF_TRIGGER_LOW)))
+ return -EINVAL;
+
+ type.type &= ~BIT(irq); /* level trig */
+ if (flow_type & IRQF_TRIGGER_HIGH)
+ type.polarity_high |= BIT(irq);
+ else
+ type.polarity_low |= BIT(irq);
+
+ flow_handler = handle_level_irq;
+ }
+
+ qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
+ irq_set_handler_locked(d, flow_handler);
+
+ return 0;
+}
+
+static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+
+ return irq_set_irq_wake(pmic_arb->irq, on);
+}
+
+static int qpnpint_get_irqchip_state(struct irq_data *d,
+ enum irqchip_irq_state which,
+ bool *state)
+{
+ u8 irq = hwirq_to_irq(d->hwirq);
+ u8 status = 0;
+
+ if (which != IRQCHIP_STATE_LINE_LEVEL)
+ return -EINVAL;
+
+ qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1);
+ *state = !!(status & BIT(irq));
+
+ return 0;
+}
+
+static int qpnpint_irq_request_resources(struct irq_data *d)
+{
+ struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ u16 periph = hwirq_to_per(d->hwirq);
+ u16 apid = hwirq_to_apid(d->hwirq);
+ u16 sid = hwirq_to_sid(d->hwirq);
+ u16 irq = hwirq_to_irq(d->hwirq);
+
+ if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
+ dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
+ sid, periph, irq, pmic_arb->ee,
+ pmic_arb->apid_data[apid].irq_ee);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static struct irq_chip pmic_arb_irqchip = {
+ .name = "pmic_arb",
+ .irq_ack = qpnpint_irq_ack,
+ .irq_mask = qpnpint_irq_mask,
+ .irq_unmask = qpnpint_irq_unmask,
+ .irq_set_type = qpnpint_irq_set_type,
+ .irq_set_wake = qpnpint_irq_set_wake,
+ .irq_get_irqchip_state = qpnpint_get_irqchip_state,
+ .irq_request_resources = qpnpint_irq_request_resources,
+ .flags = IRQCHIP_MASK_ON_SUSPEND,
+};
+
+static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
+ struct device_node *controller,
+ const u32 *intspec,
+ unsigned int intsize,
+ unsigned long *out_hwirq,
+ unsigned int *out_type)
+{
+ struct spmi_pmic_arb *pmic_arb = d->host_data;
+ u16 apid, ppid;
+ int rc;
+
+ dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
+ intspec[0], intspec[1], intspec[2]);
+
+ if (irq_domain_get_of_node(d) != controller)
+ return -EINVAL;
+ if (intsize != 4)
+ return -EINVAL;
+ if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
+ return -EINVAL;
+
+ ppid = intspec[0] << 8 | intspec[1];
+ rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
+ if (rc < 0) {
+ dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
+ intspec[0], intspec[1], intspec[2], rc);
+ return rc;
+ }
+
+ apid = rc;
+ /* Keep track of {max,min}_apid for bounding search during interrupt */
+ if (apid > pmic_arb->max_apid)
+ pmic_arb->max_apid = apid;
+ if (apid < pmic_arb->min_apid)
+ pmic_arb->min_apid = apid;
+
+ *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid);
+ *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
+
+ dev_dbg(&pmic_arb->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
+
+ return 0;
+}
+
+static int qpnpint_irq_domain_map(struct irq_domain *d,
+ unsigned int virq,
+ irq_hw_number_t hwirq)
+{
+ struct spmi_pmic_arb *pmic_arb = d->host_data;
+
+ dev_dbg(&pmic_arb->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq);
+
+ irq_set_chip_and_handler(virq, &pmic_arb_irqchip, handle_level_irq);
+ irq_set_chip_data(virq, d->host_data);
+ irq_set_noprobe(virq);
+ return 0;
+}
+
+static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
+{
+ u32 *mapping_table = pmic_arb->mapping_table;
+ int index = 0, i;
+ u16 apid_valid;
+ u16 apid;
+ u32 data;
+
+ apid_valid = pmic_arb->ppid_to_apid[ppid];
+ if (apid_valid & PMIC_ARB_APID_VALID) {
+ apid = apid_valid & ~PMIC_ARB_APID_VALID;
+ return apid;
+ }
+
+ for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
+ if (!test_and_set_bit(index, pmic_arb->mapping_table_valid))
+ mapping_table[index] = readl_relaxed(pmic_arb->cnfg +
+ SPMI_MAPPING_TABLE_REG(index));
+
+ data = mapping_table[index];
+
+ if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) {
+ if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
+ index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
+ } else {
+ apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
+ pmic_arb->ppid_to_apid[ppid]
+ = apid | PMIC_ARB_APID_VALID;
+ pmic_arb->apid_data[apid].ppid = ppid;
+ return apid;
+ }
+ } else {
+ if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
+ index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
+ } else {
+ apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
+ pmic_arb->ppid_to_apid[ppid]
+ = apid | PMIC_ARB_APID_VALID;
+ pmic_arb->apid_data[apid].ppid = ppid;
+ return apid;
+ }
+ }
+ }
+
+ return -ENODEV;
+}
+
+/* v1 offset per ee */
+static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
+{
+ return 0x800 + 0x80 * pmic_arb->channel;
+}
+
+static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
+{
+ struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
+ u32 regval, offset;
+ u16 id, apid;
+
+ for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
+ offset = pmic_arb->ver_ops->apid_map_offset(apid);
+ if (offset >= pmic_arb->core_size)
+ break;
+
+ regval = readl_relaxed(pmic_arb->cnfg +
+ SPMI_OWNERSHIP_TABLE_REG(apid));
+ apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
+ apidd->write_ee = apidd->irq_ee;
+
+ regval = readl_relaxed(pmic_arb->core + offset);
+ if (!regval)
+ continue;
+
+ id = (regval >> 8) & PMIC_ARB_PPID_MASK;
+ pmic_arb->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
+ apidd->ppid = id;
+ if (id == ppid) {
+ apid |= PMIC_ARB_APID_VALID;
+ break;
+ }
+ }
+ pmic_arb->last_apid = apid & ~PMIC_ARB_APID_VALID;
+
+ return apid;
+}
+
+static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
+{
+ u16 apid_valid;
+
+ apid_valid = pmic_arb->ppid_to_apid[ppid];
+ if (!(apid_valid & PMIC_ARB_APID_VALID))
+ apid_valid = pmic_arb_find_apid(pmic_arb, ppid);
+ if (!(apid_valid & PMIC_ARB_APID_VALID))
+ return -ENODEV;
+
+ return apid_valid & ~PMIC_ARB_APID_VALID;
+}
+
+static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
+{
+ struct apid_data *apidd = pmic_arb->apid_data;
+ struct apid_data *prev_apidd;
+ u16 i, apid, ppid;
+ bool valid, is_irq_ee;
+ u32 regval, offset;
+
+ /*
+ * In order to allow multiple EEs to write to a single PPID in arbiter
+ * version 5, there is more than one APID mapped to each PPID.
+ * The owner field for each of these mappings specifies the EE which is
+ * allowed to write to the APID. The owner of the last (highest) APID
+ * for a given PPID will receive interrupts from the PPID.
+ */
+ for (i = 0; ; i++, apidd++) {
+ offset = pmic_arb->ver_ops->apid_map_offset(i);
+ if (offset >= pmic_arb->core_size)
+ break;
+
+ regval = readl_relaxed(pmic_arb->core + offset);
+ if (!regval)
+ continue;
+ ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
+ is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
+
+ regval = readl_relaxed(pmic_arb->cnfg +
+ SPMI_OWNERSHIP_TABLE_REG(i));
+ apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
+
+ apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
+
+ valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
+ apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
+ prev_apidd = &pmic_arb->apid_data[apid];
+
+ if (valid && is_irq_ee &&
+ prev_apidd->write_ee == pmic_arb->ee) {
+ /*
+ * Duplicate PPID mapping after the one for this EE;
+ * override the irq owner
+ */
+ prev_apidd->irq_ee = apidd->irq_ee;
+ } else if (!valid || is_irq_ee) {
+ /* First PPID mapping or duplicate for another EE */
+ pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
+ }
+
+ apidd->ppid = ppid;
+ pmic_arb->last_apid = i;
+ }
+
+ /* Dump the mapping table for debug purposes. */
+ dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
+ for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {
+ apid = pmic_arb->ppid_to_apid[ppid];
+ if (apid & PMIC_ARB_APID_VALID) {
+ apid &= ~PMIC_ARB_APID_VALID;
+ apidd = &pmic_arb->apid_data[apid];
+ dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
+ ppid, apid, apidd->write_ee, apidd->irq_ee);
+ }
+ }
+
+ return 0;
+}
+
+static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
+{
+ if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
+ return -ENODEV;
+
+ return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
+}
+
+/* v2 offset per ppid and per ee */
+static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
+{
+ u16 apid;
+ u16 ppid;
+ int rc;
+
+ ppid = sid << 8 | ((addr >> 8) & 0xFF);
+ rc = pmic_arb_ppid_to_apid_v2(pmic_arb, ppid);
+ if (rc < 0)
+ return rc;
+
+ apid = rc;
+ return 0x1000 * pmic_arb->ee + 0x8000 * apid;
+}
+
+/*
+ * v5 offset per ee and per apid for observer channels and per apid for
+ * read/write channels.
+ */
+static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
+{
+ u16 apid;
+ int rc;
+ u32 offset = 0;
+ u16 ppid = (sid << 8) | (addr >> 8);
+
+ rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
+ if (rc < 0)
+ return rc;
+
+ apid = rc;
+ switch (ch_type) {
+ case PMIC_ARB_CHANNEL_OBS:
+ offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
+ break;
+ case PMIC_ARB_CHANNEL_RW:
+ offset = 0x10000 * apid;
+ break;
+ }
+
+ return offset;
+}
+
+static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
+{
+ return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
+}
+
+static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
+{
+ return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
+}
+
+static void __iomem *
+pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+{
+ return pmic_arb->intr + 0x20 * m + 0x4 * n;
+}
+
+static void __iomem *
+pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+{
+ return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n;
+}
+
+static void __iomem *
+pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+{
+ return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
+}
+
+static void __iomem *
+pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+{
+ return pmic_arb->intr + 0x10000 * m + 0x4 * n;
+}
+
+static void __iomem *
+pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
+{
+ return pmic_arb->intr + 0x200 + 0x4 * n;
+}
+
+static void __iomem *
+pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
+{
+ return pmic_arb->intr + 0x1000 * n;
+}
+
+static void __iomem *
+pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
+{
+ return pmic_arb->wr_base + 0x100 + 0x10000 * n;
+}
+
+static void __iomem *
+pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
+{
+ return pmic_arb->intr + 0x600 + 0x4 * n;
+}
+
+static void __iomem *
+pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
+{
+ return pmic_arb->intr + 0x4 + 0x1000 * n;
+}
+
+static void __iomem *
+pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
+{
+ return pmic_arb->wr_base + 0x104 + 0x10000 * n;
+}
+
+static void __iomem *
+pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
+{
+ return pmic_arb->intr + 0xA00 + 0x4 * n;
+}
+
+static void __iomem *
+pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
+{
+ return pmic_arb->intr + 0x8 + 0x1000 * n;
+}
+
+static void __iomem *
+pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
+{
+ return pmic_arb->wr_base + 0x108 + 0x10000 * n;
+}
+
+static u32 pmic_arb_apid_map_offset_v2(u16 n)
+{
+ return 0x800 + 0x4 * n;
+}
+
+static u32 pmic_arb_apid_map_offset_v5(u16 n)
+{
+ return 0x900 + 0x4 * n;
+}
+
+static const struct pmic_arb_ver_ops pmic_arb_v1 = {
+ .ver_str = "v1",
+ .ppid_to_apid = pmic_arb_ppid_to_apid_v1,
+ .non_data_cmd = pmic_arb_non_data_cmd_v1,
+ .offset = pmic_arb_offset_v1,
+ .fmt_cmd = pmic_arb_fmt_cmd_v1,
+ .owner_acc_status = pmic_arb_owner_acc_status_v1,
+ .acc_enable = pmic_arb_acc_enable_v1,
+ .irq_status = pmic_arb_irq_status_v1,
+ .irq_clear = pmic_arb_irq_clear_v1,
+ .apid_map_offset = pmic_arb_apid_map_offset_v2,
+};
+
+static const struct pmic_arb_ver_ops pmic_arb_v2 = {
+ .ver_str = "v2",
+ .ppid_to_apid = pmic_arb_ppid_to_apid_v2,
+ .non_data_cmd = pmic_arb_non_data_cmd_v2,
+ .offset = pmic_arb_offset_v2,
+ .fmt_cmd = pmic_arb_fmt_cmd_v2,
+ .owner_acc_status = pmic_arb_owner_acc_status_v2,
+ .acc_enable = pmic_arb_acc_enable_v2,
+ .irq_status = pmic_arb_irq_status_v2,
+ .irq_clear = pmic_arb_irq_clear_v2,
+ .apid_map_offset = pmic_arb_apid_map_offset_v2,
+};
+
+static const struct pmic_arb_ver_ops pmic_arb_v3 = {
+ .ver_str = "v3",
+ .ppid_to_apid = pmic_arb_ppid_to_apid_v2,
+ .non_data_cmd = pmic_arb_non_data_cmd_v2,
+ .offset = pmic_arb_offset_v2,
+ .fmt_cmd = pmic_arb_fmt_cmd_v2,
+ .owner_acc_status = pmic_arb_owner_acc_status_v3,
+ .acc_enable = pmic_arb_acc_enable_v2,
+ .irq_status = pmic_arb_irq_status_v2,
+ .irq_clear = pmic_arb_irq_clear_v2,
+ .apid_map_offset = pmic_arb_apid_map_offset_v2,
+};
+
+static const struct pmic_arb_ver_ops pmic_arb_v5 = {
+ .ver_str = "v5",
+ .ppid_to_apid = pmic_arb_ppid_to_apid_v5,
+ .non_data_cmd = pmic_arb_non_data_cmd_v2,
+ .offset = pmic_arb_offset_v5,
+ .fmt_cmd = pmic_arb_fmt_cmd_v2,
+ .owner_acc_status = pmic_arb_owner_acc_status_v5,
+ .acc_enable = pmic_arb_acc_enable_v5,
+ .irq_status = pmic_arb_irq_status_v5,
+ .irq_clear = pmic_arb_irq_clear_v5,
+ .apid_map_offset = pmic_arb_apid_map_offset_v5,
+};
+
+static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
+ .map = qpnpint_irq_domain_map,
+ .xlate = qpnpint_irq_domain_dt_translate,
+};
+
+static int spmi_pmic_arb_probe(struct platform_device *pdev)
+{
+ struct spmi_pmic_arb *pmic_arb;
+ struct spmi_controller *ctrl;
+ struct resource *res;
+ void __iomem *core;
+ u32 *mapping_table;
+ u32 channel, ee, hw_ver;
+ int err;
+
+ ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
+ if (!ctrl)
+ return -ENOMEM;
+
+ pmic_arb = spmi_controller_get_drvdata(ctrl);
+ pmic_arb->spmic = ctrl;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
+ core = devm_ioremap_resource(&ctrl->dev, res);
+ if (IS_ERR(core)) {
+ err = PTR_ERR(core);
+ goto err_put_ctrl;
+ }
+
+ pmic_arb->core_size = resource_size(res);
+
+ pmic_arb->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID,
+ sizeof(*pmic_arb->ppid_to_apid),
+ GFP_KERNEL);
+ if (!pmic_arb->ppid_to_apid) {
+ err = -ENOMEM;
+ goto err_put_ctrl;
+ }
+
+ hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
+
+ if (hw_ver < PMIC_ARB_VERSION_V2_MIN) {
+ pmic_arb->ver_ops = &pmic_arb_v1;
+ pmic_arb->wr_base = core;
+ pmic_arb->rd_base = core;
+ } else {
+ pmic_arb->core = core;
+
+ if (hw_ver < PMIC_ARB_VERSION_V3_MIN)
+ pmic_arb->ver_ops = &pmic_arb_v2;
+ else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
+ pmic_arb->ver_ops = &pmic_arb_v3;
+ else
+ pmic_arb->ver_ops = &pmic_arb_v5;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "obsrvr");
+ pmic_arb->rd_base = devm_ioremap_resource(&ctrl->dev, res);
+ if (IS_ERR(pmic_arb->rd_base)) {
+ err = PTR_ERR(pmic_arb->rd_base);
+ goto err_put_ctrl;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "chnls");
+ pmic_arb->wr_base = devm_ioremap_resource(&ctrl->dev, res);
+ if (IS_ERR(pmic_arb->wr_base)) {
+ err = PTR_ERR(pmic_arb->wr_base);
+ goto err_put_ctrl;
+ }
+ }
+
+ dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
+ pmic_arb->ver_ops->ver_str, hw_ver);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
+ pmic_arb->intr = devm_ioremap_resource(&ctrl->dev, res);
+ if (IS_ERR(pmic_arb->intr)) {
+ err = PTR_ERR(pmic_arb->intr);
+ goto err_put_ctrl;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg");
+ pmic_arb->cnfg = devm_ioremap_resource(&ctrl->dev, res);
+ if (IS_ERR(pmic_arb->cnfg)) {
+ err = PTR_ERR(pmic_arb->cnfg);
+ goto err_put_ctrl;
+ }
+
+ pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
+ if (pmic_arb->irq < 0) {
+ err = pmic_arb->irq;
+ goto err_put_ctrl;
+ }
+
+ err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
+ if (err) {
+ dev_err(&pdev->dev, "channel unspecified.\n");
+ goto err_put_ctrl;
+ }
+
+ if (channel > 5) {
+ dev_err(&pdev->dev, "invalid channel (%u) specified.\n",
+ channel);
+ err = -EINVAL;
+ goto err_put_ctrl;
+ }
+
+ pmic_arb->channel = channel;
+
+ err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
+ if (err) {
+ dev_err(&pdev->dev, "EE unspecified.\n");
+ goto err_put_ctrl;
+ }
+
+ if (ee > 5) {
+ dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);
+ err = -EINVAL;
+ goto err_put_ctrl;
+ }
+
+ pmic_arb->ee = ee;
+ mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
+ sizeof(*mapping_table), GFP_KERNEL);
+ if (!mapping_table) {
+ err = -ENOMEM;
+ goto err_put_ctrl;
+ }
+
+ pmic_arb->mapping_table = mapping_table;
+ /* Initialize max_apid/min_apid to the opposite bounds, during
+ * the irq domain translation, we are sure to update these */
+ pmic_arb->max_apid = 0;
+ pmic_arb->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
+
+ platform_set_drvdata(pdev, ctrl);
+ raw_spin_lock_init(&pmic_arb->lock);
+
+ ctrl->cmd = pmic_arb_cmd;
+ ctrl->read_cmd = pmic_arb_read_cmd;
+ ctrl->write_cmd = pmic_arb_write_cmd;
+
+ if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
+ err = pmic_arb_read_apid_map_v5(pmic_arb);
+ if (err) {
+ dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n",
+ err);
+ goto err_put_ctrl;
+ }
+ }
+
+ dev_dbg(&pdev->dev, "adding irq domain\n");
+ pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
+ &pmic_arb_irq_domain_ops, pmic_arb);
+ if (!pmic_arb->domain) {
+ dev_err(&pdev->dev, "unable to create irq_domain\n");
+ err = -ENOMEM;
+ goto err_put_ctrl;
+ }
+
+ irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq,
+ pmic_arb);
+ err = spmi_controller_add(ctrl);
+ if (err)
+ goto err_domain_remove;
+
+ return 0;
+
+err_domain_remove:
+ irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
+ irq_domain_remove(pmic_arb->domain);
+err_put_ctrl:
+ spmi_controller_put(ctrl);
+ return err;
+}
+
+static int spmi_pmic_arb_remove(struct platform_device *pdev)
+{
+ struct spmi_controller *ctrl = platform_get_drvdata(pdev);
+ struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+ spmi_controller_remove(ctrl);
+ irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
+ irq_domain_remove(pmic_arb->domain);
+ spmi_controller_put(ctrl);
+ return 0;
+}
+
+static const struct of_device_id spmi_pmic_arb_match_table[] = {
+ { .compatible = "qcom,spmi-pmic-arb", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);
+
+static struct platform_driver spmi_pmic_arb_driver = {
+ .probe = spmi_pmic_arb_probe,
+ .remove = spmi_pmic_arb_remove,
+ .driver = {
+ .name = "spmi_pmic_arb",
+ .of_match_table = spmi_pmic_arb_match_table,
+ },
+};
+module_platform_driver(spmi_pmic_arb_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:spmi_pmic_arb");
diff --git a/src/kernel/linux/v4.19/drivers/spmi/spmi.c b/src/kernel/linux/v4.19/drivers/spmi/spmi.c
new file mode 100644
index 0000000..aa3edab
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/spmi/spmi.c
@@ -0,0 +1,603 @@
+/*
+ * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/idr.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/spmi.h>
+#include <linux/pm_runtime.h>
+
+#include <dt-bindings/spmi/spmi.h>
+#define CREATE_TRACE_POINTS
+#include <trace/events/spmi.h>
+
+static bool is_registered;
+static DEFINE_IDA(ctrl_ida);
+
+static void spmi_dev_release(struct device *dev)
+{
+ struct spmi_device *sdev = to_spmi_device(dev);
+ kfree(sdev);
+}
+
+static const struct device_type spmi_dev_type = {
+ .release = spmi_dev_release,
+};
+
+static void spmi_ctrl_release(struct device *dev)
+{
+ struct spmi_controller *ctrl = to_spmi_controller(dev);
+ ida_simple_remove(&ctrl_ida, ctrl->nr);
+ kfree(ctrl);
+}
+
+static const struct device_type spmi_ctrl_type = {
+ .release = spmi_ctrl_release,
+};
+
+static int spmi_device_match(struct device *dev, struct device_driver *drv)
+{
+ if (of_driver_match_device(dev, drv))
+ return 1;
+
+ if (drv->name)
+ return strncmp(dev_name(dev), drv->name,
+ SPMI_NAME_SIZE) == 0;
+
+ return 0;
+}
+
+/**
+ * spmi_device_add() - add a device previously constructed via spmi_device_alloc()
+ * @sdev: spmi_device to be added
+ */
+int spmi_device_add(struct spmi_device *sdev)
+{
+ struct spmi_controller *ctrl = sdev->ctrl;
+ int err;
+
+ dev_set_name(&sdev->dev, "%d-%02x", ctrl->nr, sdev->usid);
+
+ err = device_add(&sdev->dev);
+ if (err < 0) {
+ dev_err(&sdev->dev, "Can't add %s, status %d\n",
+ dev_name(&sdev->dev), err);
+ goto err_device_add;
+ }
+
+ dev_dbg(&sdev->dev, "device %s registered\n", dev_name(&sdev->dev));
+
+err_device_add:
+ return err;
+}
+EXPORT_SYMBOL_GPL(spmi_device_add);
+
+/**
+ * spmi_device_remove(): remove an SPMI device
+ * @sdev: spmi_device to be removed
+ */
+void spmi_device_remove(struct spmi_device *sdev)
+{
+ device_unregister(&sdev->dev);
+}
+EXPORT_SYMBOL_GPL(spmi_device_remove);
+
+static inline int
+spmi_cmd(struct spmi_controller *ctrl, u8 opcode, u8 sid)
+{
+ int ret;
+
+ if (!ctrl || !ctrl->cmd || ctrl->dev.type != &spmi_ctrl_type)
+ return -EINVAL;
+
+ ret = ctrl->cmd(ctrl, opcode, sid);
+ trace_spmi_cmd(opcode, sid, ret);
+ return ret;
+}
+
+static inline int spmi_read_cmd(struct spmi_controller *ctrl, u8 opcode,
+ u8 sid, u16 addr, u8 *buf, size_t len)
+{
+ int ret;
+
+ if (!ctrl || !ctrl->read_cmd || ctrl->dev.type != &spmi_ctrl_type)
+ return -EINVAL;
+
+ trace_spmi_read_begin(opcode, sid, addr);
+ ret = ctrl->read_cmd(ctrl, opcode, sid, addr, buf, len);
+ trace_spmi_read_end(opcode, sid, addr, ret, len, buf);
+ return ret;
+}
+
+static inline int spmi_write_cmd(struct spmi_controller *ctrl, u8 opcode,
+ u8 sid, u16 addr, const u8 *buf, size_t len)
+{
+ int ret;
+
+ if (!ctrl || !ctrl->write_cmd || ctrl->dev.type != &spmi_ctrl_type)
+ return -EINVAL;
+
+ trace_spmi_write_begin(opcode, sid, addr, len, buf);
+ ret = ctrl->write_cmd(ctrl, opcode, sid, addr, buf, len);
+ trace_spmi_write_end(opcode, sid, addr, ret);
+ return ret;
+}
+
+/**
+ * spmi_register_read() - register read
+ * @sdev: SPMI device.
+ * @addr: slave register address (5-bit address).
+ * @buf: buffer to be populated with data from the Slave.
+ *
+ * Reads 1 byte of data from a Slave device register.
+ */
+int spmi_register_read(struct spmi_device *sdev, u8 addr, u8 *buf)
+{
+ /* 5-bit register address */
+ if (addr > 0x1F)
+ return -EINVAL;
+
+ return spmi_read_cmd(sdev->ctrl, SPMI_CMD_READ, sdev->usid, addr,
+ buf, 1);
+}
+EXPORT_SYMBOL_GPL(spmi_register_read);
+
+/**
+ * spmi_ext_register_read() - extended register read
+ * @sdev: SPMI device.
+ * @addr: slave register address (8-bit address).
+ * @buf: buffer to be populated with data from the Slave.
+ * @len: the request number of bytes to read (up to 16 bytes).
+ *
+ * Reads up to 16 bytes of data from the extended register space on a
+ * Slave device.
+ */
+int spmi_ext_register_read(struct spmi_device *sdev, u8 addr, u8 *buf,
+ size_t len)
+{
+ /* 8-bit register address, up to 16 bytes */
+ if (len == 0 || len > 16)
+ return -EINVAL;
+
+ return spmi_read_cmd(sdev->ctrl, SPMI_CMD_EXT_READ, sdev->usid, addr,
+ buf, len);
+}
+EXPORT_SYMBOL_GPL(spmi_ext_register_read);
+
+/**
+ * spmi_ext_register_readl() - extended register read long
+ * @sdev: SPMI device.
+ * @addr: slave register address (16-bit address).
+ * @buf: buffer to be populated with data from the Slave.
+ * @len: the request number of bytes to read (up to 8 bytes).
+ *
+ * Reads up to 8 bytes of data from the extended register space on a
+ * Slave device using 16-bit address.
+ */
+int spmi_ext_register_readl(struct spmi_device *sdev, u16 addr, u8 *buf,
+ size_t len)
+{
+ /* 16-bit register address, up to 8 bytes */
+ if (len == 0 || len > 8)
+ return -EINVAL;
+
+ return spmi_read_cmd(sdev->ctrl, SPMI_CMD_EXT_READL, sdev->usid, addr,
+ buf, len);
+}
+EXPORT_SYMBOL_GPL(spmi_ext_register_readl);
+
+/**
+ * spmi_register_write() - register write
+ * @sdev: SPMI device
+ * @addr: slave register address (5-bit address).
+ * @data: buffer containing the data to be transferred to the Slave.
+ *
+ * Writes 1 byte of data to a Slave device register.
+ */
+int spmi_register_write(struct spmi_device *sdev, u8 addr, u8 data)
+{
+ /* 5-bit register address */
+ if (addr > 0x1F)
+ return -EINVAL;
+
+ return spmi_write_cmd(sdev->ctrl, SPMI_CMD_WRITE, sdev->usid, addr,
+ &data, 1);
+}
+EXPORT_SYMBOL_GPL(spmi_register_write);
+
+/**
+ * spmi_register_zero_write() - register zero write
+ * @sdev: SPMI device.
+ * @data: the data to be written to register 0 (7-bits).
+ *
+ * Writes data to register 0 of the Slave device.
+ */
+int spmi_register_zero_write(struct spmi_device *sdev, u8 data)
+{
+ return spmi_write_cmd(sdev->ctrl, SPMI_CMD_ZERO_WRITE, sdev->usid, 0,
+ &data, 1);
+}
+EXPORT_SYMBOL_GPL(spmi_register_zero_write);
+
+/**
+ * spmi_ext_register_write() - extended register write
+ * @sdev: SPMI device.
+ * @addr: slave register address (8-bit address).
+ * @buf: buffer containing the data to be transferred to the Slave.
+ * @len: the request number of bytes to read (up to 16 bytes).
+ *
+ * Writes up to 16 bytes of data to the extended register space of a
+ * Slave device.
+ */
+int spmi_ext_register_write(struct spmi_device *sdev, u8 addr, const u8 *buf,
+ size_t len)
+{
+ /* 8-bit register address, up to 16 bytes */
+ if (len == 0 || len > 16)
+ return -EINVAL;
+
+ return spmi_write_cmd(sdev->ctrl, SPMI_CMD_EXT_WRITE, sdev->usid, addr,
+ buf, len);
+}
+EXPORT_SYMBOL_GPL(spmi_ext_register_write);
+
+/**
+ * spmi_ext_register_writel() - extended register write long
+ * @sdev: SPMI device.
+ * @addr: slave register address (16-bit address).
+ * @buf: buffer containing the data to be transferred to the Slave.
+ * @len: the request number of bytes to read (up to 8 bytes).
+ *
+ * Writes up to 8 bytes of data to the extended register space of a
+ * Slave device using 16-bit address.
+ */
+int spmi_ext_register_writel(struct spmi_device *sdev, u16 addr, const u8 *buf,
+ size_t len)
+{
+ /* 4-bit Slave Identifier, 16-bit register address, up to 8 bytes */
+ if (len == 0 || len > 8)
+ return -EINVAL;
+
+ return spmi_write_cmd(sdev->ctrl, SPMI_CMD_EXT_WRITEL, sdev->usid,
+ addr, buf, len);
+}
+EXPORT_SYMBOL_GPL(spmi_ext_register_writel);
+
+/**
+ * spmi_command_reset() - sends RESET command to the specified slave
+ * @sdev: SPMI device.
+ *
+ * The Reset command initializes the Slave and forces all registers to
+ * their reset values. The Slave shall enter the STARTUP state after
+ * receiving a Reset command.
+ */
+int spmi_command_reset(struct spmi_device *sdev)
+{
+ return spmi_cmd(sdev->ctrl, SPMI_CMD_RESET, sdev->usid);
+}
+EXPORT_SYMBOL_GPL(spmi_command_reset);
+
+/**
+ * spmi_command_sleep() - sends SLEEP command to the specified SPMI device
+ * @sdev: SPMI device.
+ *
+ * The Sleep command causes the Slave to enter the user defined SLEEP state.
+ */
+int spmi_command_sleep(struct spmi_device *sdev)
+{
+ return spmi_cmd(sdev->ctrl, SPMI_CMD_SLEEP, sdev->usid);
+}
+EXPORT_SYMBOL_GPL(spmi_command_sleep);
+
+/**
+ * spmi_command_wakeup() - sends WAKEUP command to the specified SPMI device
+ * @sdev: SPMI device.
+ *
+ * The Wakeup command causes the Slave to move from the SLEEP state to
+ * the ACTIVE state.
+ */
+int spmi_command_wakeup(struct spmi_device *sdev)
+{
+ return spmi_cmd(sdev->ctrl, SPMI_CMD_WAKEUP, sdev->usid);
+}
+EXPORT_SYMBOL_GPL(spmi_command_wakeup);
+
+/**
+ * spmi_command_shutdown() - sends SHUTDOWN command to the specified SPMI device
+ * @sdev: SPMI device.
+ *
+ * The Shutdown command causes the Slave to enter the SHUTDOWN state.
+ */
+int spmi_command_shutdown(struct spmi_device *sdev)
+{
+ return spmi_cmd(sdev->ctrl, SPMI_CMD_SHUTDOWN, sdev->usid);
+}
+EXPORT_SYMBOL_GPL(spmi_command_shutdown);
+
+static int spmi_drv_probe(struct device *dev)
+{
+ const struct spmi_driver *sdrv = to_spmi_driver(dev->driver);
+ struct spmi_device *sdev = to_spmi_device(dev);
+ int err;
+
+ pm_runtime_get_noresume(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ err = sdrv->probe(sdev);
+ if (err)
+ goto fail_probe;
+
+ return 0;
+
+fail_probe:
+ pm_runtime_disable(dev);
+ pm_runtime_set_suspended(dev);
+ pm_runtime_put_noidle(dev);
+ return err;
+}
+
+static int spmi_drv_remove(struct device *dev)
+{
+ const struct spmi_driver *sdrv = to_spmi_driver(dev->driver);
+
+ pm_runtime_get_sync(dev);
+ sdrv->remove(to_spmi_device(dev));
+ pm_runtime_put_noidle(dev);
+
+ pm_runtime_disable(dev);
+ pm_runtime_set_suspended(dev);
+ pm_runtime_put_noidle(dev);
+ return 0;
+}
+
+static int spmi_drv_uevent(struct device *dev, struct kobj_uevent_env *env)
+{
+ int ret;
+
+ ret = of_device_uevent_modalias(dev, env);
+ if (ret != -ENODEV)
+ return ret;
+
+ return 0;
+}
+
+static struct bus_type spmi_bus_type = {
+ .name = "spmi",
+ .match = spmi_device_match,
+ .probe = spmi_drv_probe,
+ .remove = spmi_drv_remove,
+ .uevent = spmi_drv_uevent,
+};
+
+/**
+ * spmi_controller_alloc() - Allocate a new SPMI device
+ * @ctrl: associated controller
+ *
+ * Caller is responsible for either calling spmi_device_add() to add the
+ * newly allocated controller, or calling spmi_device_put() to discard it.
+ */
+struct spmi_device *spmi_device_alloc(struct spmi_controller *ctrl)
+{
+ struct spmi_device *sdev;
+
+ sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
+ if (!sdev)
+ return NULL;
+
+ sdev->ctrl = ctrl;
+ device_initialize(&sdev->dev);
+ sdev->dev.parent = &ctrl->dev;
+ sdev->dev.bus = &spmi_bus_type;
+ sdev->dev.type = &spmi_dev_type;
+ return sdev;
+}
+EXPORT_SYMBOL_GPL(spmi_device_alloc);
+
+/**
+ * spmi_controller_alloc() - Allocate a new SPMI controller
+ * @parent: parent device
+ * @size: size of private data
+ *
+ * Caller is responsible for either calling spmi_controller_add() to add the
+ * newly allocated controller, or calling spmi_controller_put() to discard it.
+ * The allocated private data region may be accessed via
+ * spmi_controller_get_drvdata()
+ */
+struct spmi_controller *spmi_controller_alloc(struct device *parent,
+ size_t size)
+{
+ struct spmi_controller *ctrl;
+ int id;
+
+ if (WARN_ON(!parent))
+ return NULL;
+
+ ctrl = kzalloc(sizeof(*ctrl) + size, GFP_KERNEL);
+ if (!ctrl)
+ return NULL;
+
+ device_initialize(&ctrl->dev);
+ ctrl->dev.type = &spmi_ctrl_type;
+ ctrl->dev.bus = &spmi_bus_type;
+ ctrl->dev.parent = parent;
+ ctrl->dev.of_node = parent->of_node;
+ spmi_controller_set_drvdata(ctrl, &ctrl[1]);
+
+ id = ida_simple_get(&ctrl_ida, 0, 0, GFP_KERNEL);
+ if (id < 0) {
+ dev_err(parent,
+ "unable to allocate SPMI controller identifier.\n");
+ spmi_controller_put(ctrl);
+ return NULL;
+ }
+
+ ctrl->nr = id;
+ dev_set_name(&ctrl->dev, "spmi-%d", id);
+
+ dev_dbg(&ctrl->dev, "allocated controller 0x%p id %d\n", ctrl, id);
+ return ctrl;
+}
+EXPORT_SYMBOL_GPL(spmi_controller_alloc);
+
+static void of_spmi_register_devices(struct spmi_controller *ctrl)
+{
+ struct device_node *node;
+ int err;
+
+ if (!ctrl->dev.of_node)
+ return;
+
+ for_each_available_child_of_node(ctrl->dev.of_node, node) {
+ struct spmi_device *sdev;
+ u32 reg[2];
+
+ dev_dbg(&ctrl->dev, "adding child %pOF\n", node);
+
+ err = of_property_read_u32_array(node, "reg", reg, 2);
+ if (err) {
+ dev_err(&ctrl->dev,
+ "node %pOF err (%d) does not have 'reg' property\n",
+ node, err);
+ continue;
+ }
+
+ if (reg[1] != SPMI_USID) {
+ dev_err(&ctrl->dev,
+ "node %pOF contains unsupported 'reg' entry\n",
+ node);
+ continue;
+ }
+
+ if (reg[0] >= SPMI_MAX_SLAVE_ID) {
+ dev_err(&ctrl->dev, "invalid usid on node %pOF\n", node);
+ continue;
+ }
+
+ dev_dbg(&ctrl->dev, "read usid %02x\n", reg[0]);
+
+ sdev = spmi_device_alloc(ctrl);
+ if (!sdev)
+ continue;
+
+ sdev->dev.of_node = node;
+ sdev->usid = (u8) reg[0];
+
+ err = spmi_device_add(sdev);
+ if (err) {
+ dev_err(&sdev->dev,
+ "failure adding device. status %d\n", err);
+ spmi_device_put(sdev);
+ }
+ }
+}
+
+/**
+ * spmi_controller_add() - Add an SPMI controller
+ * @ctrl: controller to be registered.
+ *
+ * Register a controller previously allocated via spmi_controller_alloc() with
+ * the SPMI core.
+ */
+int spmi_controller_add(struct spmi_controller *ctrl)
+{
+ int ret;
+
+ /* Can't register until after driver model init */
+ if (WARN_ON(!is_registered))
+ return -EAGAIN;
+
+ ret = device_add(&ctrl->dev);
+ if (ret)
+ return ret;
+
+ if (IS_ENABLED(CONFIG_OF))
+ of_spmi_register_devices(ctrl);
+
+ dev_dbg(&ctrl->dev, "spmi-%d registered: dev:%p\n",
+ ctrl->nr, &ctrl->dev);
+
+ return 0;
+};
+EXPORT_SYMBOL_GPL(spmi_controller_add);
+
+/* Remove a device associated with a controller */
+static int spmi_ctrl_remove_device(struct device *dev, void *data)
+{
+ struct spmi_device *spmidev = to_spmi_device(dev);
+ if (dev->type == &spmi_dev_type)
+ spmi_device_remove(spmidev);
+ return 0;
+}
+
+/**
+ * spmi_controller_remove(): remove an SPMI controller
+ * @ctrl: controller to remove
+ *
+ * Remove a SPMI controller. Caller is responsible for calling
+ * spmi_controller_put() to discard the allocated controller.
+ */
+void spmi_controller_remove(struct spmi_controller *ctrl)
+{
+ int dummy;
+
+ if (!ctrl)
+ return;
+
+ dummy = device_for_each_child(&ctrl->dev, NULL,
+ spmi_ctrl_remove_device);
+ device_del(&ctrl->dev);
+}
+EXPORT_SYMBOL_GPL(spmi_controller_remove);
+
+/**
+ * spmi_driver_register() - Register client driver with SPMI core
+ * @sdrv: client driver to be associated with client-device.
+ *
+ * This API will register the client driver with the SPMI framework.
+ * It is typically called from the driver's module-init function.
+ */
+int __spmi_driver_register(struct spmi_driver *sdrv, struct module *owner)
+{
+ sdrv->driver.bus = &spmi_bus_type;
+ sdrv->driver.owner = owner;
+ return driver_register(&sdrv->driver);
+}
+EXPORT_SYMBOL_GPL(__spmi_driver_register);
+
+static void __exit spmi_exit(void)
+{
+ bus_unregister(&spmi_bus_type);
+}
+module_exit(spmi_exit);
+
+static int __init spmi_init(void)
+{
+ int ret;
+
+ ret = bus_register(&spmi_bus_type);
+ if (ret)
+ return ret;
+
+ is_registered = true;
+ return 0;
+}
+postcore_initcall(spmi_init);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("SPMI module");
+MODULE_ALIAS("platform:spmi");
diff --git a/src/kernel/linux/v4.19/drivers/spmi/spmi_sw.h b/src/kernel/linux/v4.19/drivers/spmi/spmi_sw.h
new file mode 100644
index 0000000..758e143
--- /dev/null
+++ b/src/kernel/linux/v4.19/drivers/spmi/spmi_sw.h
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Argus Lin <argus.lin@mediatek.com>
+ */
+#ifndef __SPMI_SW_H__
+#define __SPMI_SW_H__
+
+#include <linux/pmif.h>
+#include <linux/spmi.h>
+
+#define DEFAULT_VALUE_READ_TEST (0x5a)
+#define DEFAULT_VALUE_WRITE_TEST (0xa5)
+
+enum spmi_regs {
+ SPMI_OP_ST_CTRL,
+ SPMI_GRP_ID_EN,
+ SPMI_OP_ST_STA,
+ SPMI_SAMPL_CTRL,
+ SPMI_REQ_EN,
+ SPMI_RCS_CTRL,
+ SPMI_SLV_3_0_EINT,
+ SPMI_SLV_7_4_EINT,
+ SPMI_SLV_B_8_EINT,
+ SPMI_SLV_F_C_EINT,
+ SPMI_REC_CTRL,
+ SPMI_REC0,
+ SPMI_REC1,
+ SPMI_REC2,
+ SPMI_REC3,
+ SPMI_REC4,
+ SPMI_REC_CMD_DEC,
+ SPMI_DEC_DBG,
+ SPMI_MST_DBG,
+ SPMI_NUM_REGS
+};
+
+/* pmif debug API declaration */
+extern void spmi_dump_wdt_reg(void);
+extern void spmi_dump_pmif_acc_vio_reg(void);
+extern void spmi_dump_pmic_acc_vio_reg(void);
+extern void spmi_dump_pmif_busy_reg(void);
+extern void spmi_dump_pmif_swinf_reg(void);
+extern void spmi_dump_pmif_all_reg(void);
+extern void spmi_dump_pmif_record_reg(void);
+/* spmi debug API declaration */
+extern void spmi_dump_spmimst_all_reg(void);
+/* pmic debug API declaration */
+extern int spmi_pmif_create_attr(struct device_driver *driver);
+extern int spmi_pmif_dbg_init(struct spmi_controller *ctrl);
+#endif /*__SPMI_SW_H__*/